TW201304622A - 無核心層之封裝基板及其製法 - Google Patents

無核心層之封裝基板及其製法 Download PDF

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TW201304622A
TW201304622A TW100124353A TW100124353A TW201304622A TW 201304622 A TW201304622 A TW 201304622A TW 100124353 A TW100124353 A TW 100124353A TW 100124353 A TW100124353 A TW 100124353A TW 201304622 A TW201304622 A TW 201304622A
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layer
dielectric
package substrate
metal
circuit
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TW100124353A
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TWI475935B (zh
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Tzyy-Jang Tseng
Chung-Wen Ho
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Unimicron Technology Corp
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Priority to TW100124353A priority Critical patent/TWI475935B/zh
Priority to CN201110215624.1A priority patent/CN102867807B/zh
Priority to US13/417,858 priority patent/US9257379B2/en
Publication of TW201304622A publication Critical patent/TW201304622A/zh
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Publication of TWI475935B publication Critical patent/TWI475935B/zh
Priority to US14/985,448 priority patent/US9484223B2/en

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Abstract

一種無核心層之封裝基板，係包括：由至少一介電層、線路層與導電結構所組成之線路增層結構、埋設於該線路增層結構最下層介電層中之電性接觸墊、設於該線路增層結構最上層線路層上之複數金屬凸塊、設於該線路增層結構最上層表面與該金屬凸塊上且外露該金屬凸塊之介電保護層。該金屬凸塊具有金屬柱及設於該金屬柱上之翼部，藉由該金屬凸塊之翼部之全部頂表面係完全外露，以增加該金屬凸塊與晶片之間的結合力。

Description

無核心層之封裝基板及其製法
　　本發明係有關一種封裝基板，尤指一種無核心層（coreless）之封裝基板及其製法。
　　隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前半導體封裝結構已開發出不同的封裝型態，例如：打線式或覆晶式，係於一封裝基板上設置半導體晶片，且該半導體晶片藉由導線或焊錫凸塊電性連接至該封裝基板上。為了滿足半導體封裝件高整合度（integration）及微型化（miniaturization）的封裝需求，以供更多主、被動元件及線路載接，封裝基板亦逐漸由雙層電路板演變成多層電路板（multi-layer board），俾於有限的空間下運用層間連接技術（interlayer connection）以擴大封裝基板上可供利用的線路佈局面積，並能配合高線路密度之積體電路（integrated circuit）的使用需求，且降低封裝基板的厚度，而能達到封裝結構輕薄短小及提高電性功能之目的。
　　習知技術中，封裝基板係由一具有內層線路之核心板及對稱形成於其兩側之線路增層結構所構成。因使用核心板將導致整體結構厚度增加，故難以滿足電子產品功能不斷提昇而體積卻不斷縮小的需求。
　　因此，遂發展出無核心層（coreless）之封裝基板，以縮短導線長度及降低整體結構厚度而符合高頻化、微小化的趨勢。如第1圖所示之無核心層之封裝基板1，其製法係包括：於一承載板（圖未示）上形成第一介電層10，且於該第一介電層10上形成具有複數第一電性接觸墊110之第一線路層11；於該第一介電層10與第一線路層11上形成線路增層結構12，該線路增層結構12具有至少一第二介電層120，且於該第二介電層120上形成有第二線路層121，並藉由導電盲孔122電性連接該第一與第二線路層11,121，又最上層之第二線路層121具有複數第二電性接觸墊123；移除該承載板，以外露該第一介電層10；於該第一介電層10、最上層之第二介電層120與第二線路層121上形成如綠漆之防焊層14a,14b；於該防焊層14a,14b與第一介電層10上形成複數開孔140a,140b，以對應外露各該第一及第二電性接觸墊110,123之部分頂表面；於該開孔140a,140b中形成金屬凸塊13a,13b，以結合焊球15a,15b，令上側焊球15b用以接置晶片之焊錫凸塊（圖未示），而下側焊球15a用以接置電路板（圖未示）。
　　惟，習知封裝基板1中，需於該防焊層14a,14b上形成開孔140a,140b，而焊球15a,15b與開孔140a,140b之間的對位不易，因而增加製程難度。
　　再者，該防焊層14b之開孔140b僅露出該第二電性接觸墊123之部分頂表面，而非外露全部頂表面，以致於該金屬凸塊13b的頂表面之面積縮小，導致於後續接置晶片時，該金屬凸塊13b與晶片之間的結合力減小，使該晶片容易脫落因而損毀。
　　又，為了避免該上側焊球15b之間相連接而產生短路，且需考量該防焊層14b之開孔140b之尺寸以維持該金屬凸塊13b之結合力，故各該第二電性接觸墊123之間的距離需增加，使該第二電性接觸墊123之間距無法細間距化，導致難以提高該第二電性接觸墊123的佈設密度。
　　因此，如何克服上述習知技術中之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明提供一種無核心層之封裝基板之製法，係包括：提供一具有相對兩表面之承載板，且於該承載板之表面上形成複數電性接觸墊；於該承載板及該些電性接觸墊上形成線路增層結構，該線路增層結構具有至少一介電層、設於各該介電層上之線路層、及設於各該介電層中且電性連接各該線路層之複數導電結構，該電性接觸墊係埋設於該最下層之介電層中，且該最下層之介電層中之導電結構係電性連接該些電性接觸墊；於該最上層之線路層上形成複數金屬凸塊；於該最上層之介電層與最上層之線路層上形成介電保護層，以包覆該些金屬凸塊；移除該介電保護層之部分材質及該金屬凸塊之部分材質，使該金屬凸塊具有金屬柱及設於該金屬柱上之翼部，以外露該些翼部之全部頂表面，俾供電性連接半導體晶片；以及移除該承載板，使各該電性接觸墊外露於該最下層之介電層表面。
　　依上述製法可知，係藉由該金屬凸塊之全部頂表面完全外露該介電保護層，而無需於該介電保護層上形成開孔，可避免如習知技術之焊球與開孔之間的對位問題，故於後續接置半導體晶片時，只需將半導體晶片直接放置於該金屬凸塊上即可，因而使製程簡易化。
　　再者，該金屬凸塊之全部頂表面係完全外露，相較於習知技術，不僅增加該金屬凸塊與半導體晶片之間的結合面積，使該金屬凸塊與半導體晶片之間的結合力增加，故該晶片不會脫落及損毀。
　　又，因該金屬凸塊面積較小，使該金屬凸塊之間的距離可縮小，故各該金屬凸塊之間的距離可細間距化，以提高金屬凸塊的佈設密度。
　　另外，依前述之本發明無核心層之封裝基板之製法，本發明復提供一種無核心式封裝基板及該製法之更具體技術，詳如後述。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。　　
　　須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下方”、“上方”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
　　請參閱第2A至2E圖，係為本發明無核心層之封裝基板之製法之剖視示意圖。
　　如第2A圖所示，首先，提供一具有相對兩表面之承載板20，且於該承載板20之兩表面上形成複數電性接觸墊21。
　　接著，於該承載板20及該些電性接觸墊21上形成線路增層結構22，該線路增層結構22具有至少一介電層220、設於各該介電層220上之線路層221、及設於各該介電層220中且電性連接各該線路層221之複數導電結構（於此為導電盲孔222），該電性接觸墊21係埋設於該最下層之介電層220中，且該最下層之介電層中之導電盲孔222係電性連接該些電性接觸墊21。
　　於本實施例中，該承載板20之相對兩表面上設有剝離層201，令該些電性接觸墊21與該最下層之介電層220結合於該剝離層201上。另外，該剝離層201上可形成銅層，以電鍍形成該第一電性接觸墊21。
　　如第2B圖所示，於該線路增層結構22上藉由圖案化製程，以於阻層23a開口區中之該最上層之線路層221上形成複數具有金屬柱230及設於該金屬柱230上之蕈狀結構231的金屬凸塊23。
　　其中，形成該金屬凸塊23之材料係為銅、鎳、錫、金、銀或銅錫合金，且該圖案化製程可為加成法、半加成法、減成法、電鍍、無電鍍沉積（electroless plating deposit）、化學沉積或印刷之方式形成該蕈狀金屬凸塊23。然而，有關形成蕈狀金屬凸塊之方式與材料種類繁多，並不限於上述。
　　如第2C圖所示，移除該阻層23a，再於該最上層之介電層220與最上層之線路層221上形成介電保護層24a，以包覆該些金屬凸塊23。
　　如第2D圖所示，經整平製程，如刷磨、機械研磨、或化學機械研磨（Chemical Mechanical Polishing）等方式，以移除該介電保護層24a之部分材料及蕈狀結構231之部分材料，使該蕈狀結構231成為翼部231’而外露。於本實施例中，該些金屬凸塊23之翼部231’表面係與該介電保護層24之表面齊平，且該翼部231’之寬度W大於該金屬柱230之端面直徑D。
　　如第2E圖所示，藉由分離該剝離層201以移除該承載板20，使各該電性接觸墊21外露於該最下層之介電層220表面，以製作出本發明無核心層之封裝基板2。
　　如第2E’圖所示，若該剝離層201上具有銅層，則於移除該承載板20後，需以蝕刻方式移除該銅層，使該電性接觸墊21’微凹於該最下層之介電層220表面。
　　請參閱第3及4圖，藉由切單製程，以取得單一封裝基板2a，且將半導體晶片4藉由焊錫凸塊40覆晶結合至該金屬凸塊23之翼部231’外露表面上，再於該半導體晶片4與該介電保護層24之間形成底膠41以包覆該焊錫凸塊40，並於該電性接觸墊21之外露表面上結合例如焊球3、針腳之導電元件以接置例如電路板或封裝結構之電子裝置（圖未示）。
　　另外，請參閱第3’、3”、4’及4”圖，係為第2A圖之其他製程。如第3’圖所示，於製作該線路增層結構22時，可於該介電層220中藉由雷射灼燒或電漿蝕刻形成線路槽220a，使線路層221’形成於該線路槽220a中，且同時形成導電盲孔222，以形成嵌埋式線路層221’。亦或，如第3”圖所示，導電結構為導電柱222’，以電性連接各層線路層221’及第一電性接觸墊21，且該線路層221’與該導電柱222’係分開製作。
　　於第3’及3”圖中，該線路槽220a之另一種製程，係可先於介電層220上形成高分子薄膜（圖未示），形成薄膜之材料可為液態或固態之高分子材料；再以雷射燒蝕貫穿該薄膜與介電層220而形成該線路槽220a，且以電漿增強該線路槽220a之表面極性強度；接著，藉由浸鍍方式，於該些線路槽220a之孔壁上形成活化層（圖未示），亦即將該介電層220浸泡於含有金屬顆粒之化學溶液中，使該些金屬顆粒作為活化層而附著該些線路槽220a之孔壁上；最後，藉由剝除、研磨或化學蝕刻方式移除該高分子薄膜，而保留該線路槽220a之孔壁上之金屬顆粒，使該線路層221’形成於該線路槽220a中之活化層上。其中，形成活化層的材料可為鈀、鉑、金或銀，且鈀材可以來自於氯化物錫鈀膠體或硫酸鈀螯合物（chelator）。
　　本發明之製法係藉由整平製程，使該金屬凸塊23之全部頂表面完全外露於該介電保護層24，以避免如習知技術之於防焊層上形成開孔，故於後續接置半導體晶片4時，半導體晶片4不需以開孔對位，而係將半導體晶片4之焊錫凸塊40直接放置於該金屬凸塊23上即可，不需再於該金屬凸塊23上形成如第1圖所示之焊球15b，因而使製程簡易化。
　　再者，該金屬凸塊23之全部頂表面係完全外露於該介電保護層24，可增加該金屬凸塊23與該焊錫凸塊40之間的結合面積，使該金屬凸塊23與該焊錫凸塊40之間的結合力增加，因而該半導體晶片4不會脫落及損毀。
　　又，因該金屬凸塊23之面積較小，使該金屬凸塊23之間的距離可縮小，故各該金屬凸塊23之間的距離可達細間距設計，以提高該金屬凸塊23的佈設密度。
　　本發明復提供一種無核心層之封裝基板2a，係包括：線路增層結構22、設於該線路增層結構22下方之複數電性接觸墊21、設於該線路增層結構22上方之複數金屬凸塊23、以及設於該線路增層結構22與該金屬凸塊23上之介電保護層24。
　　所述之線路增層結構22係具有至少一介電層220、設於各該介電層220上之線路層221、及設於各該介電層220中且電性連接各該線路層221之複數導電盲孔222。於一實施例中，線路層221’可嵌埋於該介電層220中，如第3’圖所示。於另一實施例中，以導電柱222’取代導電盲孔222，以電性連接各層線路層221’，如第3”圖所示。
　　所述之電性接觸墊21係嵌埋於該最下層之介電層220，且電性連接部分該導電盲孔222或導電柱222’，又該電性接觸墊21外露於該最下層之介電層220表面。其中，該電性接觸墊21可齊平於該最下層之介電層220表面、或該電性接觸墊21’可微凹於該最下層之介電層220表面。
　　所述之金屬凸塊23係設於該最上層之線路層221上，且具有金屬柱230及設於該金屬柱230上之翼部231’。
　　所述之介電保護層24係設於該最上層之介電層220、最上層之線路層221與該些金屬凸塊23上，且外露該些金屬凸塊23之全部頂表面，令該金屬凸塊23之外露表面供電性連接半導體晶片4。又該些金屬凸塊23之表面可與該介電保護層24之表面齊平。
　　綜上所述，本發明無核心層之封裝基板及其製法，主要藉由介電保護層取代習知之防焊層，使該介電保護層無需開孔即可外露該金屬凸塊之全部頂表面，以於後續接置半導體晶片時，可使製程簡易化。
　　再者，該金屬凸塊之全部頂表面完全外露於該介電保護層，可增加該金屬凸塊的結合力，而避免該半導體晶片脫落及損毀。
　　又，該金屬凸塊之全部頂表面完全外露於該介電保護層，故各該金屬凸塊之間距可作細間距設計，以達到提高該電性接觸墊的佈設密度之目的。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2a．．．封裝基板
10．．．第一介電層
11．．．第一線路層
110．．．第一電性接觸墊
12,22．．．線路增層結構
120．．．第二介電層
121．．．第二線路層
122,222．．．導電盲孔
123．．．第二電性接觸墊
13a,13b,,23．．．金屬凸塊
14a,14b．．．防焊層
140a,140b．．．開孔
15a,15b．．．焊球
20．．．承載板
201．．．剝離層
21,21’．．．電性接觸墊
220．．．介電層
220a．．．線路槽
221,221’．．．線路層
222’．．．導電柱
23a．．．阻層
230．．．金屬柱
231．．．蕈狀結構
231’．．．翼部
24,24a．．．介電保護層
3．．．焊球
4．．．半導體晶片
40．．．焊錫凸塊
41．．．底膠
W．．．寬度
D．．．端面直徑
　　第1圖係為習知無核心層之封裝基板的剖視示意圖；
　　第2A至2E圖係為本發明無核心層之封裝基板之製法的剖視示意圖；其中，第2E’圖係為第2E圖之另一實施態樣；
　　第3、3’及3”圖係為本發明無核心層之封裝基板的不同實施例之剖視示意圖；以及
　　第4、4’及4”圖係為本發明無核心層之封裝基板後續應用的不同實施例之剖視示意圖。
2a．．．封裝基板
21．．．電性接觸墊
22．．．線路增層結構
220．．．介電層
221．．．線路層
222．．．導電盲孔
23．．．金屬凸塊
230．．．金屬柱
231’．．．翼部
24．．．介電保護層

Claims (17)

  1. 一種無核心層之封裝基板，係包括：
    　　線路增層結構，係具有至少一介電層、設於各該介電層上之線路層、及設於各該介電層中且電性連接各該線路層之複數導電結構；
    　　複數電性接觸墊，係嵌埋於該最下層之介電層，且電性連接部分該導電結構，並外露於該最下層之介電層表面；
    　　複數金屬凸塊，係設於該最上層之線路層上，且具有金屬柱及設於該金屬柱上之翼部；
    　　介電保護層，係設於該最上層之介電層、最上層之線路層與該些金屬凸塊上，且外露該些金屬凸塊之翼部全部頂表面，令該翼部之外露頂表面供電性連接半導體晶片。
  2. 如申請專利範圍第1項所述之無核心層之封裝基板，其中，該線路層嵌埋於該介電層中。
  3. 如申請專利範圍第1項所述之無核心層之封裝基板，其中，該導電結構係為導電盲孔或導電柱。
  4. 如申請專利範圍第1項所述之無核心層之封裝基板，其中，該電性接觸墊表面之高度齊平或低於該最下層之介電層表面之高度。
  5. 如申請專利範圍第1項所述之無核心層之封裝基板，其中，該些金屬凸塊之翼部之表面與該介電保護層之表面齊平。
  6. 如申請專利範圍第1項所述之無核心層之封裝基板，其中，該翼部之寬度大於該金屬柱之端面直徑。
  7. 一種無核心層之封裝基板之製法，係包括：
    　　提供一具有相對兩表面之承載板，且於該承載板之表面上形成複數電性接觸墊；
    　　於該承載板及該些電性接觸墊上形成線路增層結構，該線路增層結構具有至少一介電層、設於各該介電層上之線路層、及設於各該介電層中且電性連接各該線路層之複數導電結構，該電性接觸墊係埋設於該最下層之介電層中，且部分該導電結構係電性連接該些電性接觸墊；
    　　於該最上層之線路層上形成複數金屬凸塊；
    　　於該最上層之介電層與最上層之線路層上形成介電保護層，以包覆該些金屬凸塊；
    　　移除該介電保護層之部分材質及該金屬凸塊之部分材質，使該金屬凸塊具有金屬柱及設於該金屬柱上之翼部，以外露該些翼部之全部頂表面，俾供電性連接半導體晶片；以及
    　　移除該承載板，使各該電性接觸墊外露於該最下層之介電層表面。
  8. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該承載板之相對兩表面上設有剝離層，以令該些電性接觸墊與該最下層之介電層結合於該剝離層上，且藉由分離該剝離層以移除該承載板。
  9. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該介電層中形成有線路槽，以於該線路槽中形成該線路層。
  10. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該導電結構係為導電盲孔或導電柱。
  11. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該介電保護層係以塗佈方式形成之。
  12. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，形成該金屬凸塊之材料係為銅、鎳、錫、金、銀或銅錫合金。
  13. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該金屬凸塊係以加成法、半加成法、減成法、電鍍、無電鍍沉積、化學沉積或印刷之方式形成。
  14. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，移除該介電保護層之部分材質之方式係以整平製程，令該些翼部之表面與該介電保護層之表面齊平，以外露該些翼部之全部頂表面。
  15. 如申請專利範圍第14項所述之無核心層之封裝基板之製法，其中，該整平製程係以刷磨、機械研磨、或化學機械研磨方式進行。
  16. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，形成該翼部之製程係包括：先於該最上層之線路層上形成具有金屬柱及設於該金屬柱上之蕈狀結構的該些金屬凸塊，再移除該介電保護層之部分材料及蕈狀結構之部分材料，使該蕈狀結構成為翼部。
  17. 如申請專利範圍第7項所述之無核心層之封裝基板之製法，其中，該翼部之寬度大於該金屬柱之端面直徑。
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