201241978 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種覆晶裝置，特別是關於一種具有介質 層之覆晶裝置》 【先前技術】 在應用覆晶（COG)技術的顯示裝置中，透明基板的電極 端子係與驅動1C連接而驅動顯示裝置。覆晶技術通常是指 1C晶片（如驅動1C)可直接與透明基板連接而無需其他類似 撓性電路（Flexible Printed Circuit)的元件。通常電極端子 可傳輸自1C晶片的訊號至透明基板的電極，而使透明基板 的電極可驅動顯示裝置。1C晶片的接觸墊係透過凸塊連接 電極端子並輸出訊號而驅動顯示裝置。 隨著近年來電子機器裝置（電子裝置）小型化、薄型化之 發展’半導體元件中更高密度封裝技術的需求很大。目前 使用引線架以封裝半導體裝置之方法已無法迎合高密度封 裝之需求。此外’在諸多用以接合半導體元件之晶粒黏接 材料中，以使用樹脂糊膠為主之方法係為目前之主流。 由於覆晶封裝技術係將半導體元件封裝在最小面積内， 可與目前小尺寸高密度之電子機器裝置之發展相呼應，故 頗受曝目。該覆晶封裝所用之半導體元件之鋁電極上形成 有凸塊’且該凸塊係與電路基板上之配線電性連接。至於 凸塊之組成，主要是使用焊錫，且該焊錫凸塊係形成在鋁 電極端子上’而該鋁電極端子則曝露且藉由層積或電鍍而 電性連接於晶片之内部配線。 201241978 如果此種以覆晶連接方式之半導體裝置係以如此方式來 處理，則用以連接之電極端子會曝露於大氣，若經歷例如 迴焊（solder reflow)步驟等後續製程之受熱歷程 history)中’會有巨大應力作用於凸塊之連接部，因為晶片 與基板之熱膨服係數差異甚大，而產生封裝可靠性方面的 問題》 ，為解決此問題，75採用-種方法，係在凸塊連接於基板 後，用樹脂糊膠或黏合膜填入半導體元件與基板間之間 隙，然後使之可硬化並固定，而將半導體元件敎:減 板上，以改善連接部之可靠性。 -般而言m封裝之半導體元件具有許多電極端 子’且因電路設計上的問題’該等電極端子係配設在半導 體元件周圍。因此’在填充樹脂糊膠時，如果利用毛細管 現象將液態樹脂從該等半導體元件之兩電極間之間隙注 入’則樹脂不能充分擴散，很容易產生未填充部份，而導 致各種操作上之缺失，例如半導體元件之動作容易不穩 定、及耐座可靠性很低的問題。而且，當晶片尺寸更小時， 基板會因溢流之液態樹脂而污毕 T采 冋時，當電極間距很窄 時’樹脂不容易注入。此外，* & α + 卜在覆日日連接式半導體元件内 填入樹脂，要花太長時間，B U , 疋故不利於固化步驟的量產問 題。 囚此在榎晶接合技術中， 、方性導電接合（anisotropic conductive bonding)是政由 ，、 種重要且不易被取代的方 法，相較於上述焊接方式， 異方性導電接合係能以低溫低 201241978 壓°的條件達到高密度的電性連通。然而，目前所採用的 異方性導電接合膠膜（A c F )係在一半固化樹脂内封設有複 ^個等球徑的導電球，並且該些導電球的分散密度必須相 當均勻，故異方性導電接合膠膜的成本很高。此外，當覆 晶壓合力量過大，導電球通常無法順利地電性接觸晶片凸 塊與基板的接觸墊；再者，當覆晶壓合力量過大，導電球 表面的電鍍層易於破裂，導致電性斷路，因此可作業參數 範圍顯得狹窄，故覆晶接合良率與產品可靠性需要作進一 步的改善。 【發明内容】 本發明之一目的係提供一種能有效減少異方性導電接合 膠膜並減少成本的覆晶裝置，可避免覆晶壓合力量過大時 晶片凸塊與基板的導線（或接觸墊）接觸不良的問題。此外， 本發明亦可避免過多異方性導電接合膠膜電性連接晶片與 基板所造成的短路問題。因此本發明可避免使用過多不必 要的異方性導電接合膠膜，纟同時具有相同的接合功效， 進而達到節省成本的目的。 為達上述目的，本發明揭示一種覆晶裝置，其包含一含 有表面及凸出該表面之至少一凸塊的第一基板、含有至少 一導線之一第二基板以及具有一預設高度之一介質層。該 介質層連接該第一基版與該第二基板，使該第一基板與該 第二基板之間形成-絕緣空間，且該介質層環繞該絕緣空 間。 為達上述目的，本發明揭示另一種覆晶裝置，其包含一 201241978 第一基板、一第二基板以及一介質層。該第一基板含有一 表面以及凸出該表面之複數個凸塊，該些凸塊沿該表面邊 緣間隔排列。該第二基板含有至少一導線，上述該些凸塊 的部分投影面積位於該至少一導線内，該介質層設置於該 第一基板與該第二基板之間，並連接該第一基板與該第二 基板。由於該介質層具有一預設高度，因此該第一基板與 該第二基板之間形成一絕緣空間，且該介質層環繞該絕緣 空間，此外該介質層的表面積重疊該些凸塊的投影面積。 【實施方式】 在下文中本發明的實施例係配合所附圖式以闡述細節。 說明書所提及的「一實施例」、「實施範例」、「本實施例」 等等，意指包含在本發明之該實施例所述有關之特殊特 性、構造、或特徵。說明書中各處出現之「此實施例中」 的片語，並不必然全部指相同的實施例。 圖4為圖3沿切線A_A，的剖面圖。由圖4可以清楚地觀 察到介質層薄膜3係由介質層13及膠帶23所組成。相較 於習知技術所示之圖i，可以觀察到圖丨之介質層薄膜2 係由整片的異方性導電膠膜21及膠帶22所組成，因此習 知技術之介質層薄膜2與本發明的介質層薄膜3最大的差 異在於本發明的介質層13並非整片。具體而言，本發明的 介質層13並非覆蓋全部膠帶23,而是在膠帶23上環繞以 形成一絕緣空間4 〇 較佳為異方性導電膠 131及導電粒子132。 如圖4所示之實施例中，介質層13 膜13’異方性導電膠膜13包含膠材 201241978 異方性導電膠13為-種内部分佈有導電粒子132的黏著膠 膜，其主要的功能在於可提供兩種接合物體垂直方向的電 |·生導通於水平方向貝j具有絕緣效果。自於其具有低操 作度、黏著製程簡單及良好的接著能力等優點’並同時 具有導電及絕緣的效果’現今已被廣泛地運用在液晶顯示 器的模組構裝上，做為元件間的互連材料。 一般而s，導電粒子132通常係由金（Au)等導電材質所 構成，且導電粒子132通常是由一層金屬箔層（圖未示）包 覆或電鍍於絕緣粒子（圖未示）所構成。因此若覆晶壓合力 里過大，導電粒子132表面的金屬箔層或電鍍層將容易破 裂而造成電性斷路。本發明之異方性導電膠膜丨3環繞一絕 緣空間4，該絕緣空間4可避免覆晶壓合力量過大時，導 電粒子132表面的金屬箔層因為互相碰撞而損壞。這是因 為絕緣空間4提供導電粒子132及膠材ηι位移的空間， 因此‘異方性導電膠膜13受到強大的壓合力時，可以往絕 緣空間4擴展’而不至於彼此過度碰撞。 參照圖3所示之第一基板u(如半導體晶片）於其邊緣四 周具有複數個凸塊112，凸塊112彼此間隔排列^具體而 s ’凸塊112係沿該表面邊緣間隔排列。而這些凸塊1丄2 係與異方性導電膠膜13相對應設置。在此實施例中，第一 基板11與異方異方性導電膠膜13的連接製程為捲帶自動 接合（Tape Automated Bonding ;以下簡稱TAB )製程來進 行連接。 TAB製程黏接時’第一基板11(如驅動晶片）係以覆晶方 201241978 式透過一異方性導電膠膜13為黏接媒介。藉此，將其接點 固定於第二基板12(如軟帶式基板）表面接點之相對應位 置°並施加壓力，壓合第一基板11及第二基板12兩者， 使兩者各自之接點受到擠壓，進而接觸位於接點之間的導 電粒子’而導通各接點之間。使第一基板11及第二基板 12形成電路連接。 如圖5所示之第一基板11、異方性導電膠膜13及第二 基板12的結合實施例中，第一基板11含有一表面111以 及凸出該表面之至少一凸塊112。具體而言，表面ill 為第一基板11的下表面，凸塊112凸出表面並具有兩接觸 點113。在其他實施例（圖未示）中，凸塊的接觸點丨丨3可因 應不同的設計需求或強度需求而設計成不同數目的接觸點 113或甚至省略接觸點113。 在此實施例中，第一基板11的凸塊112相對應於介質層 13(異方性導電膠膜）設置。換言之，該些凸塊112的垂直 投影面積位於該介質層13内。當介質層薄膜3與第一基板 11藉由異方性導電膠膜13連接後，即可將膠帶23移除， 膠帶移除後第一基板11及異方性導電膠膜13可藉由異方 性導電膠膜13與第二基板12的至少一導線121電性連 接，而產生如圖6所示的覆晶裝置10。其中，為了使不同 物件之間的黏著能力及導通性能達到最佳的效果，在不同 物件連接時，可採用相同或不同特性的異方性導電膠膜13 進行黏合，而使得電子裝置在製造的過程的每一次接合製 程中’所使用的異方性導電膠膜可能為相同或不同型號。 201241978 而二圖：所示之覆晶裝置10的實施例中，各層的順序由上 ::為含有表面⑴及凸出表面⑴之至少一凸塊ιΐ2 土板11、具有-預設高度之介質層13以及含有至 i 一 Ιϊ121之第二基板12。換言之，介質層13設置於 土 U之凸塊112下方，而第二基板12的導線121 :設置於介質層13的下方。且該些凸塊112的部分投影面 積位於該至少一導線121内。 在此實施例中，介質層13的面積略大於凸塊ιΐ2或導線 121的面積，然而在其他實施例(圖未示)中，介質層13的 面積亦可因應设計的需求而設計成略小於或等於凸塊112 或導線121的面積。另外’在此實施例中’介質層13的表 面積重疊於該些凸力112的投影面積，然而在其他實施例 (圖未不)中’介質層13的表面積亦可部分重疊於該些凸塊 112的投影面積即可。 在圖6所示之實施例中，第-基板11係選自晶片及半導 體線路板，而第二基板12係選自玻璃線路板、電路薄膜、 面板、軟性電路板及印刷電路板，且介質層13可為異方性 導電膠膜，但於其他實施例中，介質層13亦可為其他可導 電的材質。在此實施例中，異方性導電膠膜13電性連接該 二凸塊112及該些導線121，且該介質層13設置於該些凸 塊112及該些導線121之間。 由於異方性導電膠膜13具有一預設高度，因此可使第__ 基板11與第二基板12之間間隔至少上述預設高度，也因 此於該第-基板11與該第二基板12之間形成—絕緣空間 -10- 201241978 4，同時該介質層13(異方性導電膠膜）環繞該絕緣空間4。 若將圖6的實施例相較於圖1及圖2的先前技術而言， 先前技術的介質層21並無此絕緣空間4 ’因此當覆晶裝置 如圖2所示壓合時，介質層21可能於中間攏起而使上下基 板接觸，是故產生短路。由於本發明的異方性導電膠膜13 環繞一絕緣空間4，因此當覆晶裝置10壓合時並不會產生 中間攏起的現象，是故可避免因中間攏起而使上下基板接 觸的短路現象。 綜上所述，本發明之介質層13環繞而形成一絕緣空間， 此一設計可避免介質層因壓合時所產生的中間攏起現象， 是故可避免因中間攏起而使上下基板接觸的短路缺陷。此 外此一設計能避免使用過多不必要的異方性導電接合膠 膜，並同時具有相同的接合功效，進而達到節省成本的目 的。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修[因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾’並為以下之中請專利範圍所涵蓋。 【圖式簡單說明】 圖1係習知介質層之示意圖； 圖2係習知的覆晶裝置之剖面圖； 一基板與介質層接合 圖3顯示根據本發明一實施例之第 之俯視圖； 201241978 圖4係圖3本發明一實施例之第一基板與介質層接合之 切線A-A'之剖面圖； 圖5係本發明一實施例之第一基板、第二基板與介質層 接合之剖面圖；以及 圖6係本發明一實施例之完成覆晶裝置的剖面圖。 【主要元件符號說明】 2 介質層薄膜 3 介質層薄膜 4 絕緣空間 10 覆晶裝置 11 第一基板 111 表面 112 凸塊 113 接觸點 12 第二基板 121 導線 13 介質層 13 異方性導電膠膜 131 膠材 13 2 導電粒子 21 異方性導電膠膜 21 介質層 22 膠帶 -12- 201241978 23 膠帶201241978 VI. Description of the Invention: [Technical Field] The present invention relates to a flip chip device, and more particularly to a flip chip device having a dielectric layer. [Prior Art] In a display device using a flip chip (COG) technology The electrode terminal of the transparent substrate is connected to the drive 1C to drive the display device. Flip-chip technology generally refers to a 1C wafer (such as drive 1C) that can be directly connected to a transparent substrate without the need for other components such as Flexible Printed Circuits. Typically, the electrode terminals can transmit signals from the 1C wafer to the electrodes of the transparent substrate, such that the electrodes of the transparent substrate can drive the display device. The contact pads of the 1C wafer drive the display device through the bumps connecting the electrode terminals and outputting signals. With the recent development of miniaturization and thinning of electronic equipment (electronic devices), there is a great demand for higher density packaging technology in semiconductor devices. Current methods of using leadframes to package semiconductor devices have not been able to meet the demands of high-density packaging. Further, in many die bonding materials for bonding semiconductor elements, a method mainly using a resin paste is currently in the mainstream. Since the flip chip packaging technology encapsulates the semiconductor component in a minimum area, it can be closely related to the development of the current small-sized and high-density electronic machine device. A bump ' is formed on the aluminum electrode of the semiconductor element used in the flip chip package, and the bump is electrically connected to the wiring on the circuit board. As for the composition of the bumps, solder is mainly used, and the solder bumps are formed on the aluminum electrode terminals, and the aluminum electrode terminals are exposed and electrically connected to the internal wiring of the wafer by lamination or plating. 201241978 If such a flip-chip connection semiconductor device is processed in such a manner, the electrode terminals for connection are exposed to the atmosphere, and if subjected to a heat history of a subsequent process such as a solder reflow step, 'There will be a huge stress on the joint of the bumps, because the thermal expansion coefficient between the wafer and the substrate is very different, which causes problems in package reliability. To solve this problem, 75 is a method based on bumps. After being connected to the substrate, a gap between the semiconductor element and the substrate is filled with a resin paste or an adhesive film, and then it can be hardened and fixed, and the semiconductor element is smashed to reduce the reliability of the connection portion. In general, a m-packaged semiconductor device has a plurality of electrode terminals ' and is problematic in circuit design." The electrode terminals are disposed around the semiconductor elements. Therefore, when the resin paste is filled, if the liquid resin is injected from the gap between the electrodes of the semiconductor elements by capillary action, the resin cannot be sufficiently diffused, and an unfilled portion is easily generated, resulting in various operational defects. For example, the operation of the semiconductor element is likely to be unstable, and the reliability of the seat is low. Moreover, when the wafer size is smaller, the substrate is contaminated by the overflowing liquid resin, and when the electrode pitch is narrow, the resin is not easily injected. In addition, * & α + Bu is filled with resin in the day-to-day connected semiconductor element, which takes too long, B U , which is disadvantageous for the mass production of the curing step. In the twinning bonding technique, anisotropic conductive bonding is a political, important and difficult to replace method. Compared with the above welding method, the anisotropic conductive bonding system can be low in temperature. 201241978 The condition of pressure reached a high-density electrical connection. However, the anisotropic conductive bonding film (A c F ) currently used is provided with a plurality of conductive balls of equal spherical diameter in a half of the cured resin, and the dispersion density of the conductive balls must be relatively uniform, so The cost of the anisotropic conductive bonding film is high. In addition, when the flip chip pressing force is too large, the conductive ball usually cannot smoothly contact the contact pad of the wafer bump and the substrate smoothly; further, when the flip chip pressing force is too large, the plating layer on the surface of the conductive ball is easily broken, resulting in electricity. Because of the open circuit, the range of operating parameters is narrow, so the flip chip bonding yield and product reliability need to be further improved. SUMMARY OF THE INVENTION An object of the present invention is to provide a flip chip device capable of effectively reducing an anisotropic conductive bonding film and reducing cost, and avoiding wires (or contact pads of a wafer bump and a substrate when the flip chip pressing force is excessively large) The problem of poor contact. In addition, the present invention can also avoid the short circuit problem caused by the electrical connection between the wafer and the substrate by the excessively anisotropic conductive bonding film. Therefore, the present invention can avoid the use of an excessive amount of an anisotropic conductive bonding film, which has the same bonding efficiency, thereby achieving cost saving. In order to achieve the above object, the present invention discloses a flip chip device comprising a first substrate including a surface and at least one bump protruding from the surface, a second substrate including at least one wire, and one of a predetermined height Medium layer. The dielectric layer connects the first substrate and the second substrate such that an insulating space is formed between the first substrate and the second substrate, and the dielectric layer surrounds the insulating space. To achieve the above object, the present invention discloses another flip chip device comprising a 201241978 first substrate, a second substrate, and a dielectric layer. The first substrate includes a surface and a plurality of bumps protruding from the surface, the bumps being spaced along the edge of the surface. The second substrate includes at least one wire, and a portion of the projections of the bumps is located in the at least one wire. The dielectric layer is disposed between the first substrate and the second substrate, and connects the first substrate and the The second substrate. Since the dielectric layer has a predetermined height, an insulating space is formed between the first substrate and the second substrate, and the dielectric layer surrounds the insulating space, and the surface area of the dielectric layer overlaps the projected area of the bumps. . [Embodiment] Hereinafter, embodiments of the present invention are incorporated in the drawings to explain the details. The "an embodiment", "an embodiment", "the embodiment" and the like referred to in the specification mean a particular feature, structure, or feature as described in the embodiment of the invention. The phrase "in this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Figure 4 is a cross-sectional view of Figure 3 taken along line A-A. As is apparent from Fig. 4, the dielectric layer film 3 is composed of the dielectric layer 13 and the tape 23. Compared with the figure i shown in the prior art, it can be observed that the dielectric layer film 2 of the figure is composed of the entire anisotropic conductive film 21 and the tape 22, so the dielectric layer film 2 of the prior art is The biggest difference of the dielectric layer film 3 of the present invention is that the dielectric layer 13 of the present invention is not a monolith. Specifically, the dielectric layer 13 of the present invention does not cover the entire tape 23, but surrounds the tape 23 to form an insulating space 4, preferably an anisotropic conductive paste 131 and conductive particles 132. In the embodiment shown in FIG. 4, the dielectric layer 13 film 13' anisotropic conductive film 13 comprises a glue material 201241978. The anisotropic conductive glue 13 is an adhesive film with conductive particles 132 distributed therein, the main The function is to provide two kinds of electric power in the vertical direction of the joint object. Since it has the advantages of low operation, simple adhesion process and good adhesion ability, and has both conductive and insulating effects, it has been widely used in the module assembly of liquid crystal displays as a mutual component. Even materials. Generally, the conductive particles 132 are usually made of a conductive material such as gold (Au), and the conductive particles 132 are usually covered by a metal foil layer (not shown) or plated with insulating particles (not shown). . Therefore, if the flip chip pressing force is too large, the metal foil layer or the plating layer on the surface of the conductive particles 132 will be easily broken and cause an electrical disconnection. The anisotropic conductive film 3 of the present invention surrounds an insulating space 4 which prevents the metal foil layer on the surface of the conductive particles 132 from colliding with each other when the over-cladding force is excessively large. This is because the insulating space 4 provides a space in which the conductive particles 132 and the adhesive material ηι are displaced. Therefore, when the anisotropic conductive adhesive film 13 is subjected to a strong pressing force, it can be expanded toward the insulating space 4 without excessive collision with each other. Referring to the first substrate u (e.g., a semiconductor wafer) shown in Fig. 3, a plurality of bumps 112 are provided on the periphery thereof for four weeks, and the bumps 112 are spaced apart from each other. Specifically, the bumps 112 are spaced apart along the edge of the surface. These bumps 1丄2 are provided corresponding to the anisotropic conductive film 13. In this embodiment, the connection process of the first substrate 11 and the anisotropic conductive film 13 is a Tape Automated Bonding (TAB) process for connection. When the TAB process is bonded, the first substrate 11 (such as a driving wafer) is passed through an anisotropic conductive film 13 as a bonding medium by a flip chip. Thereby, the contacts are fixed to the corresponding positions of the surface contacts of the second substrate 12 (such as the flexible tape substrate) and pressure is applied to press the first substrate 11 and the second substrate 12 to make the two The contacts are squeezed to contact the conductive particles between the contacts to conduct between the contacts. The first substrate 11 and the second substrate 12 are electrically connected. In the combined embodiment of the first substrate 11, the anisotropic conductive film 13 and the second substrate 12 as shown in FIG. 5, the first substrate 11 includes a surface 111 and at least one bump 112 protruding from the surface. Specifically, the surface ill is the lower surface of the first substrate 11, and the bump 112 protrudes from the surface and has two contact points 113. In other embodiments (not shown), the contact points 凸3 of the bumps may be designed to different numbers of contact points 113 or even the contact points 113 depending on different design requirements or strength requirements. In this embodiment, the bumps 112 of the first substrate 11 are disposed corresponding to the dielectric layer 13 (the anisotropic conductive film). In other words, the vertical projected areas of the bumps 112 are located within the dielectric layer 13. When the dielectric layer film 3 and the first substrate 11 are connected by the anisotropic conductive film 13, the tape 23 can be removed, and after the tape is removed, the first substrate 11 and the anisotropic conductive film 13 can be different. The square conductive film 13 is electrically connected to at least one of the wires 121 of the second substrate 12 to produce a flip chip device 10 as shown in FIG. In order to achieve the best effect between the adhesion and the conduction performance between different objects, when the different objects are connected, the anisotropic conductive film 13 of the same or different characteristics may be used for bonding, so that the electronic device is manufactured. The anisotropic conductive film used in each bonding process of the process may be the same or different models. 201241978 and FIG. 2: In the embodiment of the flip chip device 10 shown, the order of the layers is as follows:: at least one bump ι 2 earth plate 11 having a surface (1) and a convex surface (1), and a medium having a preset height Layer 13 and a second substrate 12 containing i to 121. In other words, the dielectric layer 13 is disposed under the bumps 112 of the soil U, and the wires 121 of the second substrate 12 are disposed below the dielectric layer 13. And a portion of the projection area of the bumps 112 is located in the at least one wire 121. In this embodiment, the area of the dielectric layer 13 is slightly larger than the area of the bump ι 2 or the wire 121. However, in other embodiments (not shown), the area of the dielectric layer 13 may be designed to be slightly different according to the design requirements. Less than or equal to the area of the bump 112 or the wire 121. In addition, in this embodiment, the surface area of the dielectric layer 13 is overlapped with the projected area of the convex forces 112. However, in other embodiments (not shown), the surface area of the dielectric layer 13 may partially overlap the bumps. The projected area of 112 is sufficient. In the embodiment shown in FIG. 6, the first substrate 11 is selected from the group consisting of a wafer and a semiconductor circuit board, and the second substrate 12 is selected from the group consisting of a glass circuit board, a circuit film, a panel, a flexible circuit board, and a printed circuit board, and the medium The layer 13 can be an anisotropic conductive film, but in other embodiments, the dielectric layer 13 can also be other electrically conductive materials. In this embodiment, the anisotropic conductive film 13 is electrically connected to the two bumps 112 and the wires 121, and the dielectric layer 13 is disposed between the bumps 112 and the wires 121. Since the anisotropic conductive film 13 has a predetermined height, the first substrate 11 and the second substrate 12 can be separated by at least the predetermined height, and thus the first substrate 11 and the second substrate 12 are An insulating space -10- 201241978 4 is formed between the dielectric layer 13 (the anisotropic conductive film) surrounding the insulating space 4. If the embodiment of FIG. 6 is compared to the prior art of FIGS. 1 and 2, the prior art dielectric layer 21 does not have this insulating space 4'. Therefore, when the flip chip device is pressed as shown in FIG. 2, the dielectric layer 21 may be brought up in the middle to bring the upper and lower substrates into contact, so that a short circuit occurs. Since the anisotropic conductive film 13 of the present invention surrounds an insulating space 4, when the flip chip device 10 is pressed, the phenomenon of the intermediate winding does not occur, so that the upper and lower substrates are prevented from coming into contact due to the intermediate gathering. Short circuit phenomenon. In summary, the dielectric layer 13 of the present invention surrounds to form an insulating space. This design can avoid the intermediate gathering phenomenon caused by the pressing of the dielectric layer, so that the upper and lower substrates can be avoided from being contacted by the middle. Short circuit defect. In addition, this design avoids the use of too many unnecessary anisotropic conductive bonding films and at the same time has the same bonding effect, thereby achieving cost-saving objectives. The technical content and technical features of the present invention have been disclosed as above, but those skilled in the art can still make various alternatives and modifications without departing from the spirit of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of protection of the present invention should not be The invention is intended to be limited to the scope of the invention, and is intended to be BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional dielectric layer; FIG. 2 is a cross-sectional view of a conventional flip chip device; a substrate and a dielectric layer are bonded; FIG. 3 shows a plan view according to an embodiment of the present invention; 201241978 4 is a cross-sectional view of a tangent line A-A' of a first substrate and a dielectric layer in accordance with an embodiment of the present invention; FIG. 5 is a cross-sectional view showing a first substrate and a second substrate bonded to a dielectric layer according to an embodiment of the present invention; Figure 6 and Figure 6 are cross-sectional views of a completed flip chip device in accordance with one embodiment of the present invention. [Main component symbol description] 2 dielectric layer film 3 dielectric layer film 4 insulating space 10 flip chip device 11 first substrate 111 surface 112 bump 113 contact point 12 second substrate 121 wire 13 dielectric layer 13 anisotropic conductive film 131 Adhesive material 13 2 Conductive particles 21 Anisotropic conductive film 21 Dielectric layer 22 Tape -12- 201241978 23 Tape