TW201332071A - 承載板、半導體封裝件及其製法 - Google Patents

承載板、半導體封裝件及其製法 Download PDF

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TW201332071A
TW201332071A TW101102490A TW101102490A TW201332071A TW 201332071 A TW201332071 A TW 201332071A TW 101102490 A TW101102490 A TW 101102490A TW 101102490 A TW101102490 A TW 101102490A TW 201332071 A TW201332071 A TW 201332071A
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wafer
semiconductor package
layer
active surface
encapsulant
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TW101102490A
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TWI446501B (zh
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張江城
李孟宗
黃榮邦
邱世冠
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矽品精密工業股份有限公司
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Priority to TW101102490A priority Critical patent/TWI446501B/zh
Priority to CN201210034211.8A priority patent/CN103219297B/zh
Priority to US13/440,180 priority patent/US8680692B2/en
Publication of TW201332071A publication Critical patent/TW201332071A/zh
Priority to US14/174,988 priority patent/US9899237B2/en
Application granted granted Critical
Publication of TWI446501B publication Critical patent/TWI446501B/zh

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種半導體封裝件之製法，係包括：形成離型層於一具凹部之承載板表面上；置放晶片於該凹部之離型層上；形成封裝膠體於該晶片與離型層上；移除該離型層與承載板；以及形成線路結構於該封裝膠體與晶片上。藉由凹部之設計，以利於晶片對位，可避免晶片移位而導致產品可靠度不佳之問題。本發明復提供該半導體封裝件。

Description

承載板、半導體封裝件及其製法
本發明係關於半導體封裝件及其製法，特別是關於一種提升可靠度之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
第6452265號美國專利與第7202107號美國專利係提供一種晶圓級封裝之製法。請參閱第1A至1E圖，係為習知半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一導熱膠層11於一承載板10上。
如第1B圖所示，置放複數晶片12於該導熱膠層11上，該些晶片12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a結合於該導熱膠層11上。
如第1C圖所示，形成一封裝膠體13於該晶片12與該導熱膠層11上。
如第1D圖所示，移除該導熱膠層11與該承載板10，以外露該晶片12之作用面12a。
如第1E圖所示，形成一線路結構14於該封裝膠體13與該晶片12之作用面12a上，令該線路結構14電性連接該晶片12之電極墊120。
惟，習知半導體封裝件1之製法中，將晶片12置放於該具有導熱膠層11之平板形承載板10上時，因不易對位而容易造成晶片12移位，導致產品可靠度不佳。
再者，該導熱膠層11具有黏性，故該導熱膠層11常於製程中受其熱膨脹係數(Coefficient of thermal expansion,CTE)影響而發生伸縮現象而造成晶片12位置偏移之問題，例如：形成封裝膠體13時，因導熱膠層11受熱軟化而造成晶片12位移，導致後續進行線路增層製程時所形成之線路結構14無法精確連接晶片12之電極墊120而造成電性不良，致使產品可靠度不佳。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種半導體封裝件，係包括：封裝膠體，係具有凸部；晶片，係嵌埋於該封裝膠體之凸部中，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面與電極墊係外露於該封裝膠體之凸部表面；以及線路結構，係設於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
本發明復提供一種半導體封裝件之製法，係包括：提供一表面具有凹部之承載板，且該承載板表面上具有離型層；置放晶片於該凹部之離型層上，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該晶片係藉其作用面結合於該離型層上；形成封裝膠體於該晶片與該離型層上；移除該離型層與該承載板，以外露該晶片之作用面；以及形成線路結構於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
本發明又提供一種用於製作半導體封裝件之承載板，其具有凹部以及形成於表面上之離型層。
前述之製法中，形成該承載板之材質可為玻璃或金屬，且形成該離型層之材質可為疏水性材質、無機物或高分子聚合物。
前述之製法中，該凹部可具有複數個，且各該凹部係陣列排設於該承載板上。因此，前述之製法復可包括，於形成線路結構於該封裝膠體與該晶片之作用面上後，進行切單製程。
前述之製法中，可先移除該承載板，再移除該離型層；或者，可同時移除該離型層與該承載板。
前述之半導體封裝件及其製法中，該線路結構可具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該晶片之電極墊。
另外，該最外層之介電層上可形成有絕緣保護層，該絕緣保護層具有開孔，以令該線路層之部分表面外露於該開孔，可供結合導電元件。
由上可知，本發明半導體封裝件及其製法，主要藉由形成凹部於該承載板上，以利於晶片放置對位，可避免晶片移位而導致後續製程(如線路增層製程)進行困難及產品可靠度不佳之問題。
再者，該離型層不具黏性，故該離型層於製程中不受其熱膨脹係數(CTE)影響，因而不會發生伸縮現象而造成晶片位置偏移之問題，因而可避免後續製程(如線路增層製程)進行困難所造成之電性不良，俾可提升產品可靠度。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2G圖，係為本發明之半導體封裝件2之製法之剖面示意圖。
如第2A及2A’圖所示，提供一表面上具有複數凹部200之承載板20。於本實施例中，形成該承載板20之材質係為玻璃或金屬，且各該凹部200係陣列排設於該承載板20上。
如第2B圖所示，形成一離型層21於該承載板20表面與該些凹部200表面上。
於本實施例中，該離型層21之材質係為疏水性材質、無機物或高分子聚合物，如聚對二甲苯(Poly-para-xylylene,parylene)，且可利用電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PECVD)之方式形成該離型層21。
本發明之製法藉由離型層21取代習知技術之導熱膠材，以達到降低製作成本之目的。
如第2C圖所示，置放晶片22於各該凹部200之離型層21上，該晶片22具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，且該作用面22a結合於該離型層21上。
本發明藉由形成凹部200，以利於晶片22對位置放，可避免晶片之位置偏移過大。
再者，該離型層21不具黏性，特別對玻璃材之承載板20不具黏性，故於製程中該離型層21之熱膨脹係數(Coefficient of thermal expansion,CTE)不會發生伸縮而造成晶片22移位之問題，因而後續進行線路增層製程時，其線路結構可有效精確電性連接至晶片22之電極墊220而使電性正常，以提升產品之可靠度。
如第2D圖所示，形成一封裝膠體23於該晶片22與該離型層21上。
於本實施例中，形成該封裝膠體23之材質可為聚亞醯胺(Polyimide,PI)，其利用塗佈之方式形成。
再者，該封裝膠體23亦可利用壓合(lamination)或模壓(molding)之方式形成，且其材料並不限於上述。
如第2E圖所示，移除該離型層21與該承載板20，以外露該晶片22之作用面22a，且該封裝膠體23具有凸部230。
於本實施例中，係先從該離型層21上移除該承載板20，再從該封裝膠體23與晶片22上移除該離型層21。
於另一實施例中，亦可從該封裝膠體23與晶片22上分離該離型層21，以同時移除該離型層21與該承載板20，如第2E’圖所示。
如第2F圖所示，進行線路增層製程以形成一線路結構24於該封裝膠體23與該晶片22之作用面22a上，令該線路結構24電性連接該晶片22之電極墊220。
於本實施例中，該線路結構24具有至少一介電層240、形成於該介電層240上之線路層241、及形成於該介電層240中之導電盲孔242，且該導電盲孔242電性連接該線路層241與該晶片22之電極墊220。其中，該介電層240可依需求為多層，而增加線路層241以符合封裝件之線路佈設需求。
接著，形成一絕緣保護層25於該最外層之介電層240上，該絕緣保護層25具有複數開孔250，以令該線路層241之部分表面對應外露於各該開孔250，俾供結合導電元件26。其中，該導電元件26可為銲球、凸塊或銲針等，並無特別限制。
如第2G圖所示，沿切割線L(如第2F圖所示)進行切單製程，以切割出複數個半導體封裝件2。
本發明提供一種半導體封裝件2，係包括：具有凸部230之封裝膠體23、嵌入該凸部230中之晶片22、以及設於該封裝膠體23上之線路結構24。
所述之晶片22具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，且該作用面22a與電極墊220係外露於該封裝膠體23之凸部230表面。
所述之線路結構24復設於該晶片22之作用面22a上，令該線路結構24電性連接該電極墊220。其中，該線路結構24具有至少一介電層240、形成於該介電層240上之線路層241、及形成於該介電層240中之導電盲孔242，且該導電盲孔242電性連接該線路層241與該電極墊220。
另外，該最外層之介電層240上形成有絕緣保護層25，該絕緣保護層25具有複數開孔250，以令該線路層241之部分表面外露於各該開孔250，俾供結合導電元件26。
綜上所述，本發明之半導體封裝件及其製法，係藉由凹部之設計，以利於晶片對位，而提升產品之可靠度。
再者，該離型層因不具黏性而不會造成晶片移位，亦可提升產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2．．．半導體封裝件
10,20．．．承載板
11．．．導熱膠層
12,22．．．晶片
12a,22a．．．作用面
12b,22b．．．非作用面
120,220．．．電極墊
13,23．．．封裝膠體
14,24．．．線路結構
200．．．凹部
21．．．離型層
230．．．凸部
240．．．介電層
241．．．線路層
242．．．導電盲孔
25．．．絕緣保護層
250．．．開孔
26．．．導電元件
L．．．切割線
第1A至1E圖係為習知半導體封裝件之製法之剖面示意圖；以及
第2A至2G圖係為本發明之半導體封裝件之製法之剖面示意圖；其中，第2A’圖係為第2A圖之上視示意圖，第2E’圖係為第2E圖之另一實施例。
20．．．承載板
200．．．凹部
21．．．離型層
22．．．晶片
23．．．封裝膠體

Claims (15)

  1. 一種半導體封裝件，係包括：封裝膠體，係具有凸部；晶片，係嵌埋於該封裝膠體之凸部中，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面與電極墊係外露於該封裝膠體之凸部表面；以及線路結構，係設於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路結構具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該晶片之電極墊。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該最外層之介電層上形成有絕緣保護層，該絕緣保護層具有開孔，以令該線路層之部分表面外露於該開孔，俾供結合導電元件。
  4. 一種半導體封裝件之製法，係包括：提供一表面具有凹部之承載板，且該承載板表面上具有離型層；置放晶片於該凹部之離型層上，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該晶片係藉其作用面結合於該離型層上；形成封裝膠體於該晶片與該離型層上；移除該離型層與該承載板，以外露該晶片之作用面；以及形成線路結構於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
  5. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，形成該承載板之材質係為玻璃或金屬。
  6. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，該凹部具有複數個，且各該凹部係陣列排設於該承載板上。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，復包括，於形成線路結構於該封裝膠體與該晶片之作用面上後，進行切單製程。
  8. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，該離型層之材質係為疏水性材質、無機物或高分子聚合物。
  9. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，係先移除該承載板，再移除該離型層。
  10. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，係同時移除該離型層與該承載板。
  11. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，該線路結構具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該晶片之電極墊。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該最外層之介電層上形成有絕緣保護層，該絕緣保護層具有開孔，以令該線路層之部分表面外露於該開孔，俾供結合導電元件。
  13. 一種用於製作半導體封裝件之承載板，其具有凹部以及形成於表面上之離型層。
  14. 如申請專利範圍第13項所述之承載板，其中，該承載板之材質係為玻璃或金屬。
  15. 如申請專利範圍第13項所述之承載板，其中，該離型層之材質係為疏水性材質、無機物或高分子聚合物。
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