CN109545757A - The encapsulating structure and packaging method of chip - Google Patents
The encapsulating structure and packaging method of chip Download PDFInfo
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- CN109545757A CN109545757A CN201811382626.8A CN201811382626A CN109545757A CN 109545757 A CN109545757 A CN 109545757A CN 201811382626 A CN201811382626 A CN 201811382626A CN 109545757 A CN109545757 A CN 109545757A
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- chip
- plastic packaging
- packaging layer
- electrical contact
- contact end
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of encapsulating structure of chip and packaging methods, chip is packaged using the package substrate with through-hole, first chip is set in through-hole, the first surface of package substrate is covered by the second plastic packaging layer, and fill through-hole, to which the first chip is fixed with package substrate, the second surface of the package substrate is covered by the first plastic packaging layer, and the covering through-hole, the second chip is fixed away from the side of the package substrate in the second plastic packaging layer, and then the encapsulating structure is formed, device architecture is simple.And the first chip and the second plastic packaging layer in through-hole are carried by the first plastic packaging layer, when encapsulating structure is under pressure close to the side of the second chip, the pressure can be buffered by the first plastic packaging layer, to avoid the back side periphery of first chip and the second plastic packaging layer intersection Problem of Failure as caused by the pressure, reliability is improved.
Description
Technical field
The present invention relates to chip encapsulation technology fields, saying more, are related to encapsulating structure and the encapsulation side of a kind of chip
Method.
Background technique
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And in work, huge convenience is brought for daily life and work, it is indispensable to become current people
Important tool.
Electronic equipment realizes that the main component of preset function is chip, with being constantly progressive for integrated circuit technique, chip
Integrated level it is higher and higher, the function of chip is stronger and stronger, and the size of chip is smaller and smaller, thus chip needs pass through envelope
Dress forms encapsulating structure, in order to which chip is electrically connected with external circuit.
It is chip package that a kind of simple chip-packaging structure of structure, which is designed, in order to which chip is electrically connected with external circuit
Technical field urgent problem to be solved.
Summary of the invention
In view of this, it is simple structure can be formed the invention discloses a kind of encapsulating structure of chip and packaging method
Chip-packaging structure, and be electrically connected with external circuit convenient for chip.
To achieve the goals above, the present invention provides following scheme:
A kind of encapsulating structure of chip, the encapsulating structure include:
Package substrate, the package substrate include opposite first surface and second surface, run through the first surface
And the through-hole of the second surface, the package substrate further include the interconnection circuit for being electrically connected with external circuit；
First plastic packaging layer, the first plastic packaging layer covers the second surface, and covers the through-hole；
First chip, first chip are at least partially disposed in the through-hole, and first chip has on the contrary just
Face and the back side, the back side are fixed with the first plastic packaging layer, and first chip is electrically connected with the interconnection circuit；
Second plastic packaging layer, the second plastic packaging layer cover the first surface, and fill first chip and lead to described
Gap between hole；
Second chip, second chip are fixed on the side surface that the second plastic packaging layer deviates from the package substrate,
Second chip is electrically connected with the interconnection circuit.
Preferably, in above-mentioned encapsulating structure, the front of first chip includes boss and the encirclement boss
Groove；The boss exposes the first surface, and the boss includes the first functional unit, and the groove includes and described first
First weld pad of functional unit electrical connection；
The second plastic packaging layer is flushed with the boss, covers the groove.
Preferably, in above-mentioned encapsulating structure, first chip is without departing from the first surface；The second plastic packaging layer
First chip is completely covered.
Preferably, in above-mentioned encapsulating structure, the interconnection circuit includes: the first electrical contact positioned at the first surface
End, positioned at the second electrical contact end of the second surface, and electrical connection first electrical contact end and second electrical contact
The route at end；Second electrical contact end is for being electrically connected the external circuit；
First chip is electrically connected with corresponding first electrical contact end, second chip and corresponding described the
The electrical connection of one electrical contact end.
Preferably, in above-mentioned encapsulating structure, first chip passes through conducting wire and corresponding first electrical contact end
Electrical connection, the second plastic packaging layer cover the conducting wire.
Preferably, in above-mentioned encapsulating structure, the first plastic packaging layer has expose second electrical contact end first
Opening.
Preferably, in above-mentioned encapsulating structure, the second plastic packaging layer has the second opening, and second opening is for revealing
First electrical contact end of electrical connection corresponding with second chip out.
Preferably, in above-mentioned encapsulating structure, second chip has opposite front and the back side, and the back side is fixed
On the surface of the second plastic packaging layer, and its back side has the third electrical contact end being electrically connected with the interconnection circuit.
Preferably, in above-mentioned encapsulating structure, second chip has opposite front and the back side, and the back side is fixed
On the surface of the second plastic packaging layer, front has the second weld pad, and second weld pad passes through conducting wire and the interconnection circuit
Electrical connection.
Preferably, in above-mentioned encapsulating structure, further includes: be fixed on second chip away from second encapsulated layer one
The cover board of side.
Preferably, in above-mentioned encapsulating structure, second chip is sensitive chip, and the cover board is euphotic cover plate.
Preferably, in above-mentioned encapsulating structure, the cover board is fixed by the bracket in the second plastic packaging layer surface, described
Second chip described in support wraps.
Preferably, in above-mentioned encapsulating structure, the interconnection circuit includes the first branch and second branch, and described first
Chip is electrically connected with the first branch, and second chip is electrically connected with the second branch.
The present invention has also proposed a kind of packaging method of chip, and the packaging method includes:
One substrate is provided, the substrate includes multiple package substrates, there is cutting channel between the adjacent package substrate,
The package substrate includes opposite first surface and second surface, through the first surface and the second surface
Through-hole, the package substrate further include the interconnection circuit for being electrically connected with external circuit；
First chip is set in the through-hole, first chip is at least partially disposed in the through-hole, and described first
Chip has opposite front and the back side, and the back side is towards the second surface, first chip and the interconnection circuit
Electrical connection；
The second plastic packaging layer is formed, the second plastic packaging layer covers the first surface, and fills first chip and institute
State the gap of through-hole；
The first plastic packaging layer is formed, the first plastic packaging layer covers the second surface and the through-hole；
Fix the second chip away from a side surface of the package substrate in the second plastic packaging layer, second chip with
The interconnection circuit electrical connection；
Based on the cutting channel, divide the second plastic packaging layer, the substrate and the first plastic packaging layer, is formed more
The encapsulating structure of a simple grain.
Preferably, in above-mentioned packaging method, the front of first chip includes boss and the encirclement boss
Groove；The boss exposes the first surface, and the boss includes the first functional unit, and the groove includes and described first
First weld pad of functional unit electrical connection；
It is described to form the second plastic packaging layer and include:
Form the second plastic packaging layer for covering the first surface and first chip front side；
To the second plastic packaging layer carry out reduction processing, expose the boss so that the second plastic packaging layer with it is described convex
Platform flushes, and covers the groove.
Preferably, in above-mentioned packaging method, first chip is without departing from the first surface；
It is described to form the second plastic packaging layer and include:
Form the second plastic packaging layer that first chip is completely covered.
Preferably, in above-mentioned packaging method, the interconnection circuit includes: the first electrical contact positioned at the first surface
End, positioned at the second electrical contact end of the second surface, and electrical connection first electrical contact end and second electrical contact
The route at end；Second electrical contact end is for being electrically connected the external circuit；
First chip is electrically connected with corresponding first electrical contact end, second chip and corresponding described the
The electrical connection of one electrical contact end.
Preferably, in above-mentioned packaging method, first chip that is arranged in the through-hole includes: by conducting wire by institute
The first chip is stated to be electrically connected with corresponding first electrical contact end；
Wherein, the second plastic packaging layer covers the conducting wire.
Preferably, in above-mentioned packaging method, the first plastic packaging layer of the formation includes: to be formed to expose on the plastic packaging layer
First opening of second electrical contact end.
Preferably, in above-mentioned packaging method, the second plastic packaging layer of the formation includes: to be formed on the second plastic packaging layer
Second opening, second opening is for exposing first electrical contact end of electrical connection corresponding with second chip.
Preferably, in above-mentioned packaging method, second chip has opposite front and the back side, and the back side is fixed
On the surface of the second plastic packaging layer, and its back side has third electrical contact end；
It is described the second plastic packaging layer away from the package substrate a side surface fix the second chip include: will be described
Third electrical contact end and the interconnection circuit weld.
Preferably, in above-mentioned packaging method, second chip has opposite front and the back side, and the back side is fixed
On the surface of the second plastic packaging layer, front has the second weld pad；
It is described the second plastic packaging layer away from the package substrate a side surface fix the second chip include: will be described
Second weld pad is electrically connected with the interconnection circuit by conducting wire.
Preferably, in above-mentioned packaging method, further includes: deviate from the side of the second plastic packaging layer in second chip
Fixed cover board.
Preferably, in above-mentioned packaging method, second chip is sensitive chip, and the cover board is euphotic cover plate.
Preferably, in above-mentioned packaging method, the cover board is fixed by the bracket in the second plastic packaging layer surface, described
Second chip described in support wraps.
Preferably, in above-mentioned packaging method, the interconnection circuit includes the first branch and second branch, and described first
Chip is electrically connected with the first branch, and second chip is electrically connected with the second branch.
In the chip-packaging structure and packaging method that technical solution of the present invention provides, using the package substrate with through-hole
Chip is packaged, the first chip is set in through-hole, the first surface of package substrate is covered by the second plastic packaging layer, and is filled out
Through-hole is filled, so that the first chip is fixed with package substrate, covers the second of the package substrate by the first plastic packaging layer
Surface, and the through-hole is covered, the second chip, and then shape are fixed away from the side of the package substrate in the second plastic packaging layer
At the encapsulating structure, device architecture is simple.And first chip and second chip are mutual with the package substrate
Join circuit electrical connection, be electrically connected by the interconnection circuit with external circuit, is electrically connected convenient for chip with external circuit.Meanwhile
The first chip and the second plastic packaging layer in through-hole are carried by the first plastic packaging layer, in encapsulating structure close to the second chip
When side is under pressure, the pressure can be buffered by the first plastic packaging layer, to avoid the back side of first chip
Periphery and the second plastic packaging layer intersection Problem of Failure as caused by the pressure improve reliability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 3 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 4-Figure 15 is a kind of flow diagram of packaging method provided in an embodiment of the present invention；
Figure 16-Figure 23 is the flow diagram of another packaging method provided in an embodiment of the present invention；
Figure 24-Figure 27 is the flow diagram of another packaging method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
With reference to Fig. 1, Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention, the encapsulating structure
It include: package substrate 12, package substrate 12 includes opposite first surface and second surface, runs through first surface and second
The through-hole T on surface, package substrate 12 further include the interconnection circuit for being electrically connected with external circuit；First plastic packaging layer 14, first
Plastic packaging layer 14 covers second surface, and covers through-hole T；First chip 11, the first chip 11 are at least partially disposed in through-hole T, the
One chip 11 has opposite front and the back side, and the back side and the first plastic packaging layer 14 are fixed, the first chip 11 and interconnection circuit
Electrical connection；Second plastic packaging layer 13, the second plastic packaging layer 13 cover first surface, and between filling between the first chip 11 and through-hole T
Gap；Second chip 16, the second chip 16 are fixed on the side surface that the second plastic packaging layer 13 deviates from package substrate 12, the second chip 16
It is electrically connected with interconnection circuit.
In encapsulating structure of the embodiment of the present invention, chip is packaged using the package substrate 12 with through-hole T, in through-hole
First chip 11 is set in T, the first surface of package substrate 12 is covered by the second plastic packaging layer 13, and fills through-hole T, thus will
First chip 11 is fixed with package substrate 12, and the second surface of package substrate 12 is covered by the first plastic packaging layer 14, and covers
Lid through-hole T fixes the second chip 16 away from the side of package substrate 12 in the second plastic packaging layer 13, and then forms encapsulating structure, device
Part structure is simple.And first chip 11 be electrically connected with the interconnection circuit of package substrate 12 with the second chip 16, pass through interconnection electricity
Road is electrically connected with external circuit, is electrically connected convenient for chip with external circuit.Meanwhile it being carried in through-hole T by the first plastic packaging layer 14
The first chip 111 and the second plastic packaging layer 13 pass through first when encapsulating structure is under pressure close to the side of the second chip
Plastic packaging layer 14 can be with compensator or trimmer pressure, so that the back side periphery and 13 intersection of the second plastic packaging layer that avoid the first chip 11 are due to pressure
Caused Problem of Failure improves reliability, if user's touch operation can apply pressure in the front of encapsulating structure, using the present invention
Technical solution encapsulating structure, can be to avoid Problem of Failure caused by the pressure, to guarantee the reliability of fingerprint detection.Wherein,
The front of encapsulating structure is close to a side surface of the second chip 16.
In mode shown in Fig. 1, the front of the first chip 11 includes boss 111 and the groove for surrounding boss；Boss 111
Expose first surface, boss 111 includes the first functional unit, and groove includes the first weld pad being electrically connected with the first functional unit
112；Second plastic packaging layer 13 is flushed with boss 111, covers groove.The first functional unit is not shown in Fig. 1.Which can use
Thickness is packaged protection to the first chip 1 less than the package substrate 12 of the first chip 11.
First chip 11 can be electrically connected by conducting wire 15 with interconnection circuit.First weld pad 112 of the electrical connection of conducting wire 15 with mutually
Join circuit, the first chip 11 of realization is electrically connected with package substrate 12.In the front setting groove of the first chip 11, boss is formed
111, the height of conducting wire 15 can be reduced, in this way convenient for conducting wire 15 to be encapsulated in the second plastic packaging layer 13.
Interconnection circuit includes: the first electrical contact end 123 positioned at first surface, positioned at the second electrical contact end of second surface
121, and the route 122 of electrical connection the first electrical contact end 123 and the second electrical contact end 121；Second electrical contact end 121 is for electricity
Connect external circuit；First chip 11 is electrically connected with corresponding first electrical contact end 123, and the second chip 16 is electric with corresponding first
Contact jaw 123 is electrically connected.
In encapsulating structure of the embodiment of the present invention, the first chip 11 can pass through conducting wire 15 and corresponding first electrical contact end
123 electrical connections, the second plastic packaging layer 13 cover conducting wire 15.
The thickness of first plastic packaging layer 14 is greater than the height of the first electrical contact end 121, and the first plastic packaging layer 14, which has, exposes second
First opening 141 of electrical contact end 121, in order to which encapsulating structure is electrically connected with external circuit.Laser boring technique can be passed through
Opening is formed on the first plastic packaging layer 14.At this point, the first electrical contact end 121 is pad, in highly smaller other embodiments, the
The height of one electrical contact end 121 can also be greater than the thickness of the first plastic packaging layer 14.At this point, the first electrical contact end 121 can be tin
Ball has biggish height.
First electrical contact end 121 can with the welding circuit board with the external circuit board, to realize and the electricity of external circuit
Connection.It is hot melt adhesive that the first plastic packaging layer 14, which can be set, in this way, when the first electrical contact end 121 is welded with external circuit, welding
High temperature can to melt, and encapsulating structure and circuit board are adhesively fixed by the first plastic packaging layer 14, to improve stability maintenance.
First plastic packaging layer 14 can be prepared using the higher material of thermal coefficient.Leading for the first plastic packaging layer 14 such as can be set
Hot coefficient is greater than the thermal coefficient of the substrate of the first chip 11.In general, chip substrate is silicon substrate, thermal coefficient is lower.It is existing
Have in technology, in the encapsulating structure of chip, when encapsulating structure and fixed welding circuit board, has between encapsulating structure and circuit board
There is gap, heat dissipation can only be directly emitted to the air gap by the back side in through-hole, and rate of heat dispation is poor, lead to dissipating for encapsulating structure
Hot property is poor.When being electrically connected with external circuit, the second plastic packaging layer 14 is abutted with circuit board, which includes external circuit.
In technical solution of the present invention, the first plastic packaging layer 14 is set, the first plastic packaging is prepared using the biggish material of thermal coefficient
Layer 14, can make heat be exported faster by the first chip 11, avoid thermal accumlation in the first chip 11.And first plastic packaging
The area of layer 14 is greater than the back side of the first chip 11, improves heat dissipation region, improves radiating rate.When solid with welding circuit board
Periodically, re-solidified first plastic packaging layer 14 directly the first chip 11 of electrical connection and circuit board can be melted, it can be quick by heat
It is transferred to circuit board, is radiated by circuit board, rate of heat dispation is further increased.Therefore encapsulating structure of the embodiment of the present invention, tool
There is preferable heat dissipation performance.In other modes, the first plastic packaging layer 14 is the dry film that fitting is fixed on second surface, and dry film is plastic packaging
Material.Equally, in order to guarantee heat dissipation effect, when fixed with circuit board, the second plastic packaging layer 14 is abutted with circuit board.
As shown in Figure 1, the second plastic packaging layer 13 have second opening 131, second open 131 for expose it is right with the second chip 16
The first electrical contact end 123 that should be electrically connected.It is also possible to form the second opening 131 by laser boring technique.
In mode shown in Fig. 1, the second chip 16 has opposite front and the back side, and the back side is fixed on the second plastic packaging
The surface of layer 13, and its back side has the third electrical contact end 17 being electrically connected with interconnection circuit.TSV (through silicon via) work can be passed through
Skill forms the back side interconnection architecture including third electrical contact end 17 at 16 back side of the second chip.
First chip 11 is electrically connected by different routes 122 with the first electrical contact end 121 respectively from the second chip 16.Tool
Body, interconnection circuit includes that first branch a and second branch b, the first chip 11 are electrically connected with first branch a, the second chip
16 are electrically connected with second branch b.
In mode shown in Fig. 1,11 part of the first chip is located in through-hole T, and the second plastic packaging layer 13 exposes the first chip 11
Front boss 111, and flushed with boss 111.
With reference to Fig. 2, Fig. 2 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention, which with
Mode difference shown in Fig. 1 is, in mode shown in Fig. 2, the first chip 11 is fully located in through-hole T, i.e., the first chip 11 does not surpass
First surface out；The first chip 11 is completely covered in second plastic packaging layer 13.At this point, the front of the first chip 11 is planar structure.The
The thickness of one chip 11 is less than the thickness of package substrate 12.In which, the second chip 16 again by its back side third
The electrical connection of the interconnection circuit of electrical contact end 17 and package substrate.
With reference to Fig. 3, Fig. 3 be another chip provided in an embodiment of the present invention encapsulating structure schematic diagram, which with
Mode difference shown in Fig. 2 is that the second chip 16 has opposite front and the back side, and the back side is fixed on the second plastic packaging layer 13
Surface, front has the second weld pad 161, and the second weld pad 161 is electrically connected by conducting wire 15 with interconnection circuit.
In mode shown in Fig. 3, the second chip 16 no setting is required back side interconnection architecture, positive second weld pad 161 can be direct
It is electrically connected by corresponding lead 15 with package substrate 12.In mode shown in Fig. 3,11 structure of the first chip and mode phase shown in Fig. 2
Together, in other modes, Fig. 1 embodiment can also be referred to using the first chip 11 shown in Fig. 1, structure, details are not described herein.
In encapsulating structure of the embodiment of the present invention, as shown in Figure 3, further includes: be fixed on the second chip 16 away from the second encapsulation
The cover board 18 of 13 side of layer.Cover board 18 also can be set in structure shown in Fig. 1 and Fig. 2.Cover board 18 is fixed on second by bracket 19
13 surface of plastic packaging layer, bracket 19 surround the second chip 16.Second chip 16 is sensitive chip, and cover board is euphotic cover plate, at this point, can
Antireflection layer is arranged in 19 inner wall of bracket, to reduce reflection of its inner wall to light, photosensitive accurate of the second chip 16 is improved
Property.Such as second chip 16 can be optical finger print chip.First chip 11 can be pressure sense die.
As can be seen from the above description, for encapsulating structure of the embodiment of the present invention, device architecture is simple, convenient for chip and outside
Circuit electrical connection, and it is convenient for chip cooling, it can be avoided the first chip Problem of Failure as caused by pressure, it is reliable to improve it
Property.
Encapsulating structure based on the above embodiment, another embodiment of the present invention additionally provide a kind of packaging method of chip, use
In the encapsulating structure of production such as above-described embodiment, for the packaging method as shown in Fig. 4-Figure 15, Fig. 4-Figure 15 is the embodiment of the present invention
A kind of flow diagram of the packaging method provided, packaging method include:
Step S11: as shown in Figure 4 and Figure 5, a substrate 10 is provided.
Substrate 10 includes multiple package substrates 12, has cutting channel 100, package substrate 12 between adjacent package substrate 12
Including opposite first surface and second surface, also wrapped through first surface and the through-hole T of second surface, package substrate 12
Include the interconnection circuit for being electrically connected with external circuit.Wherein, Fig. 4 is substrate bowing towards each 12 first surface of package substrate
View, Fig. 5 are sectional drawing of the Fig. 4 in P-P '.
Interconnection circuit includes: the first electrical contact end 123 positioned at first surface, positioned at the second electrical contact end of second surface
121, and the route 122 of electrical connection the first electrical contact end 123 and the second electrical contact end 123；Second electrical contact end 121 is for electricity
Connect external circuit.
In subsequent step, the first chip 11 is electrically connected with corresponding first electrical contact end 123, the second chip 16 with it is corresponding
First electrical contact end 123 electrical connection, to realize being electrically connected for each chip and package substrate 12.As above-mentioned, interconnection circuit includes
First branch a and second branch b, the first chip 11 are electrically connected with first branch a, and the second chip 16 is electrically connected with second branch b
It connects.
Step S12: as shown in Figure 6 and Figure 7, the first chip 11 is set in through-hole T.
First chip 11 is at least partially disposed in through-hole T, and the first chip 11 has opposite front and the back side, the back side
Towards second surface, the first chip 11 is electrically connected with interconnection circuit.
It, can be as shown in fig. 6, first substrate 10 be horizontally arranged, the first surface of each package substrate 12 in the step
Towards setting.The back side of substrate 10 is fixed temporarily a loading plate 31.Then, as shown in fig. 7, placing the first chip in through-hole
11。
In the packaging method, the front of the first chip 11 includes boss 111 and the groove for surrounding boss 111；Boss
111 expose first surface, and boss 111 includes the first functional unit, and groove includes the first weldering being electrically connected with the first functional unit
Pad 112.
In the step, it includes: by conducting wire 15 by the first chip 11 and corresponding that the first chip 11 is arranged in through-hole T
The electrical connection of one electrical contact end 123.In the next steps, the second plastic packaging layer 13 covers conducting wire 15.
Step S13: as Figure 8-Figure 10, the second plastic packaging layer 13 is formed, the second plastic packaging layer 13 covers first surface, and fills out
Fill the gap of the first chip 11 and through-hole T.
In the step, forming the second plastic packaging layer 13 includes: as shown in figure 8, forming covering first surface and the first chip
11 positive second plastic packaging layers 13；As shown in fig. 9 again, reduction processing is carried out to the second plastic packaging layer 13, planarizes plastic packaging layer surface,
Boss 111 can also be exposed, so that the second plastic packaging layer 13 is flushed with boss 111, cover groove.The process further include: such as Figure 10
It is shown, the second opening 131 is formed on the second plastic packaging layer 13, the second opening 131 is for exposing be electrically connected corresponding with the second chip 16
The first electrical contact end 123 connect, in order to which the second chip 16 is electrically connected with package substrate 12 in subsequent process.The embodiment of the present invention
In, the second opening 131 can be formed by laser boring technique.In other modes, can also directly it be formed by mold injection
Second encapsulated layer 13 forms the second encapsulated layer 13 and the second opening 131 of setting thickness by mold.
Step S14: as shown in figures 11-13, formed the first plastic packaging layer 14, the first plastic packaging layer 14 cover second surface and
Through-hole T.
In the step, forming the first plastic packaging layer 14 includes: to be formed to expose the first of the second electrical contact end on plastic packaging layer 14
Opening 141.The first opening 141 can be formed by laser boring technique.Specifically, first as shown in figure 11, removing loading plate
31, substrate 10 is inverted, the second film of each package substrate 12 is arranged upward；Then as shown in figure 12, at 10 back side of substrate
The first plastic packaging layer 14 is formed, the second surface and all through-hole T of all package substrates 12 are covered；Finally, as shown in figure 13, shape
At the first opening 141.In other modes, first plastic packaging layer 14 of the thickness less than the second electrical contact end 121 can be formed, is directly revealed
Second electrical contact end, 121 lower end out, the second electrical contact end 121 can be tin ball at this time.
The generation type of first plastic packaging layer 14 is identical as the first plastic packaging layer 13, can place to be formed by no mold injection,
Its surface is planarized by reduction processing, the first opening 141 is being formed by laser boring technique.It, can be in other modes
The first plastic packaging layer that setting thickness planarization is directly formed by mold injection, directly forms the first opening 141, nothing by mold
Drilling technology need to individually be used.
Step S15: as shown in figure 14, the second chip is fixed away from a side surface of package substrate 12 in the second plastic packaging layer 13
16, the second chip 16 is electrically connected with interconnection circuit.
In the step, the second chip 16 has opposite front and the back side, and the back side is fixed on the second plastic packaging layer 13
Surface, and its back side has third electrical contact end 17；The is fixed away from a side surface of package substrate 12 in the second plastic packaging layer 13
Two chips 16 include: to weld third electrical contact end 17 and interconnection circuit.Third electrical contact end 17 is by the second opening 131 and mutually
Join circuit welding.
Step S16: as shown in figure 15, based on cutting channel 100, the second plastic packaging layer 13 of segmentation, substrate 10 and the first modeling
Sealing 14 forms the encapsulating structure of multiple simple grains.
By mode shown in Fig. 4-Figure 15, the encapsulating structure of structure as shown in Figure 1 can be formed, simple process is fabricated to
This is low, and the encapsulating structure of formation has preferable heat dissipation performance, and convenient for being electrically connected with external circuit.
In other modes, encapsulating structure as shown in Figure 2 can also be made, the first chip 11 is without departing from first surface；At this point,
Forming the second plastic packaging layer 13 includes: to form the second plastic packaging layer 13 that the first chip 11 is completely covered.Specific method process such as Figure 16-
Shown in Figure 23, Figure 16-Figure 23 is the flow diagram of another packaging method provided in an embodiment of the present invention, the packaging method with
Aforesaid way difference is that 11 structure of the first chip is different, other processes can refer to above-mentioned packaging method, and details are not described herein.
Above-mentioned packaging method describes the packaging method for making encapsulating structure as depicted in figs. 1 and 2, the second chip of use
16 are directly electrically connected with package substrate 12 by the third electrical contact end 17 at its back side.It makes in mode as shown in Figure 3, the second core
Piece 16 has opposite front and the back side, and the back side is fixed on the surface of the second plastic packaging layer 13, and front has the second weld pad
161；At this point, fixing the second chip 16 away from a side surface of package substrate 12 in the second plastic packaging layer 13 includes: by the second weld pad
161 are electrically connected with interconnection circuit by conducting wire 15.
When making encapsulating structure as shown in Figure 3, packaging method further includes in the second chip 16 away from the second plastic packaging layer 13
Cover board 18 is fixed in side.Optionally, the second chip 16 is sensitive chip, and cover board 18 is euphotic cover plate.Cover board 18 passes through bracket 19
It is fixed on 13 surface of the second plastic packaging layer, bracket 19 surrounds the second chip 16.The method of cover board 18 is set as shown in Figure 24-27, is schemed
24- Figure 27 is the flow diagram of another packaging method provided in an embodiment of the present invention, which includes: first as schemed
Shown in 24, the second chip 16 is fixed on the second plastic packaging layer 13, by conducting wire 15 by the second weld pad 161 and the first electrical contact end
123 electrical connections, then as shown in figure 25, in the fixed bracket 19 of 13 periphery of the second plastic packaging layer, bracket 19 includes the second chip 16, it
Afterwards, as shown in figure 26, cover board 18 is fixed on bracket.Finally, being cut based on cutting channel 100, multiple simple grain envelopes are formed
Assembling structure.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For being encapsulated disclosed in embodiment
For method, since it is corresponding with encapsulating structure disclosed in embodiment, so being described relatively simple, related place is referring to envelope
Assembling structure corresponding part explanation.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (26)
1. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes:
Package substrate, the package substrate include opposite first surface and second surface, through the first surface and
The through-hole of the second surface, the package substrate further include the interconnection circuit for being electrically connected with external circuit；
First plastic packaging layer, the first plastic packaging layer covers the second surface, and covers the through-hole；
First chip, first chip are at least partially disposed in the through-hole, first chip have opposite front with
And the back side, the back side are fixed with the first plastic packaging layer, first chip is electrically connected with the interconnection circuit；
Second plastic packaging layer, the second plastic packaging layer cover the first surface, and fill first chip and the through-hole it
Between gap；
Second chip, second chip is fixed on the side surface that the second plastic packaging layer deviates from the package substrate, described
Second chip is electrically connected with the interconnection circuit.
2. encapsulating structure according to claim 1, which is characterized in that the front of first chip includes boss and packet
Enclose the groove of the boss；The boss exposes the first surface, and the boss includes the first functional unit, the groove packet
Include the first weld pad being electrically connected with first functional unit；
The second plastic packaging layer is flushed with the boss, covers the groove.
3. encapsulating structure according to claim 1, which is characterized in that first chip is without departing from the first surface；
First chip is completely covered in the second plastic packaging layer.
4. encapsulating structure according to claim 1, which is characterized in that the interconnection circuit includes: positioned at first table
First electrical contact end in face, positioned at the second electrical contact end of the second surface, and electrical connection first electrical contact end with
The route of second electrical contact end；Second electrical contact end is for being electrically connected the external circuit；
First chip is electrically connected with corresponding first electrical contact end, second chip and corresponding described first electric
Contact jaw electrical connection.
5. encapsulating structure according to claim 4, which is characterized in that first chip by conducting wire with it is corresponding described
The electrical connection of first electrical contact end, the second plastic packaging layer cover the conducting wire.
6. encapsulating structure according to claim 4, which is characterized in that the first plastic packaging layer, which has, exposes second electricity
First opening of contact jaw.
7. encapsulating structure according to claim 4, which is characterized in that the second plastic packaging layer has the second opening, described
Second opening is for exposing first electrical contact end of electrical connection corresponding with second chip.
8. encapsulating structure according to claim 1, which is characterized in that second chip has opposite front and back
Face, the back side is fixed on the surface of the second plastic packaging layer, and its back side has the third electricity being electrically connected with the interconnection circuit
Contact jaw.
9. encapsulating structure according to claim 1, which is characterized in that second chip has opposite front and back
Face, the back side are fixed on the surface of the second plastic packaging layer, and front has the second weld pad, second weld pad by conducting wire with
The interconnection circuit electrical connection.
10. encapsulating structure according to claim 1, which is characterized in that further include: second chip is fixed on away from institute
State the cover board of the second encapsulated layer side.
11. encapsulating structure according to claim 9, which is characterized in that second chip is sensitive chip, the cover board
For euphotic cover plate.
12. encapsulating structure according to claim 9, which is characterized in that the cover board is fixed by the bracket described second
Plastic packaging layer surface, the second chip described in the support wraps.
13. -12 described in any item encapsulating structures according to claim 1, which is characterized in that the interconnection circuit includes first
Road and second branch, first chip are electrically connected with the first branch, second chip and second branch electricity
Connection.
14. a kind of packaging method of chip, which is characterized in that the packaging method includes:
A substrate is provided, the substrate includes multiple package substrates, has cutting channel between the adjacent package substrate, described
Package substrate includes opposite first surface and second surface, through the logical of the first surface and the second surface
Hole, the package substrate further include the interconnection circuit for being electrically connected with external circuit；
First chip is set in the through-hole, and first chip is at least partially disposed in the through-hole, first chip
With opposite front and the back side, the back side is electrically connected towards the second surface, first chip with the interconnection circuit
It connects；
The second plastic packaging layer is formed, the second plastic packaging layer covers the first surface, and fills first chip and lead to described
The gap in hole；
The first plastic packaging layer is formed, the first plastic packaging layer covers the second surface and the through-hole；
Fix the second chip away from a side surface of the package substrate in the second plastic packaging layer, second chip with it is described
Interconnection circuit electrical connection；
Based on the cutting channel, divides the second plastic packaging layer, the substrate and the first plastic packaging layer, form multiple lists
The encapsulating structure of grain.
15. packaging method according to claim 14, which is characterized in that the front of first chip include boss and
Surround the groove of the boss；The boss exposes the first surface, and the boss includes the first functional unit, the groove
Including the first weld pad being electrically connected with first functional unit；
It is described to form the second plastic packaging layer and include:
Form the second plastic packaging layer for covering the first surface and first chip front side；
Reduction processing is carried out to the second plastic packaging layer, exposes the boss, so that the second plastic packaging layer and the boss are neat
It is flat, cover the groove.
16. packaging method according to claim 14, which is characterized in that first chip is without departing from first table
Face；
It is described to form the second plastic packaging layer and include:
Form the second plastic packaging layer that first chip is completely covered.
17. packaging method according to claim 14, which is characterized in that the interconnection circuit includes: positioned at described first
First electrical contact end on surface, positioned at the second electrical contact end of the second surface, and electrical connection first electrical contact end
With the route of second electrical contact end；Second electrical contact end is for being electrically connected the external circuit；
First chip is electrically connected with corresponding first electrical contact end, second chip and corresponding described first electric
Contact jaw electrical connection.
18. packaging method according to claim 17, which is characterized in that described that the first chip packet is arranged in the through-hole
It includes: being electrically connected first chip with corresponding first electrical contact end by conducting wire；
Wherein, the second plastic packaging layer covers the conducting wire.
19. packaging method according to claim 17, which is characterized in that the first plastic packaging layer of the formation includes: described
The first opening for exposing second electrical contact end is formed on plastic packaging layer.
20. packaging method according to claim 17, which is characterized in that the second plastic packaging layer of the formation includes: described
The second opening is formed on second plastic packaging layer, second opening is for exposing described the be electrically connected corresponding with second chip
One electrical contact end.
21. packaging method according to claim 14, which is characterized in that second chip have opposite front and
The back side, the back side is fixed on the surface of the second plastic packaging layer, and its back side has third electrical contact end；
It is described that in the second plastic packaging layer, away from a side surface of the package substrate, to fix the second chip include: by the third
Electrical contact end and the interconnection circuit weld.
22. packaging method according to claim 14, which is characterized in that second chip have opposite front and
The back side, the back side are fixed on the surface of the second plastic packaging layer, and front has the second weld pad；
It is described that in the second plastic packaging layer, away from a side surface of the package substrate, to fix the second chip include: by described second
Weld pad is electrically connected with the interconnection circuit by conducting wire.
23. packaging method according to claim 14, which is characterized in that further include: in second chip away from described
The fixed cover board in the side of second plastic packaging layer.
24. packaging method according to claim 23, which is characterized in that second chip is sensitive chip, the lid
Plate is euphotic cover plate.
25. packaging method according to claim 23, which is characterized in that the cover board is fixed by the bracket described second
Plastic packaging layer surface, the second chip described in the support wraps.
26. the described in any item packaging methods of 4-25 according to claim 1, which is characterized in that the interconnection circuit includes first
Branch and second branch, first chip are electrically connected with the first branch, second chip and the second branch
Electrical connection.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811382626.8A CN109545757A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
| PCT/CN2019/118165 WO2020103746A1 (en) | 2018-11-20 | 2019-11-13 | Chip packaging structure, and packaging method |
| PCT/CN2019/118164 WO2020103745A1 (en) | 2018-11-20 | 2019-11-13 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811382626.8A CN109545757A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
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|---|---|
| CN109545757A true CN109545757A (en) | 2019-03-29 |
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| CN201811382626.8A Pending CN109545757A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
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| CN (1) | CN109545757A (en) |
| WO (2) | WO2020103745A1 (en) |
Cited By (3)
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| WO2020103745A1 (en) * | 2018-11-20 | 2020-05-28 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure |
| CN112542392A (en) * | 2020-12-04 | 2021-03-23 | 上海易卜半导体有限公司 | Method for forming packaging piece and packaging piece |
| CN112985471A (en) * | 2021-04-30 | 2021-06-18 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
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Also Published As
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| WO2020103745A1 (en) | 2020-05-28 |
| WO2020103746A1 (en) | 2020-05-28 |
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Application publication date: 20190329 |