CN102386106B - Partially patterned lead frame and manufacture and use its method in semiconductor packages - Google Patents

Partially patterned lead frame and manufacture and use its method in semiconductor packages Download PDF

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Publication number
CN102386106B
CN102386106B CN201110257072.0A CN201110257072A CN102386106B CN 102386106 B CN102386106 B CN 102386106B CN 201110257072 A CN201110257072 A CN 201110257072A CN 102386106 B CN102386106 B CN 102386106B
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China
Prior art keywords
chip
lead frame
lead
wire
encapsulation
Prior art date
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Expired - Fee Related
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CN201110257072.0A
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Chinese (zh)
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CN102386106A (en
Inventor
R·S·S·安东尼奥
M·H·麦凯瑞根
A·苏巴吉奥
A·C·托里阿戈
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Advanced Interconnect Technology Ltd
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Advanced Interconnect Technology Ltd
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Priority claimed from US12/875,248 external-priority patent/US20110057298A1/en
Priority claimed from US13/009,362 external-priority patent/US8236612B2/en
Application filed by Advanced Interconnect Technology Ltd filed Critical Advanced Interconnect Technology Ltd
Publication of CN102386106A publication Critical patent/CN102386106A/en
Application granted granted Critical
Publication of CN102386106B publication Critical patent/CN102386106B/en
Expired - Fee Related legal-status Critical Current
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    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Disclose a kind of partially patterned lead frame and manufacture and use its method in semiconductor packages, wherein the method is suitable for better production line automation and therefrom produces the q&r of improvement of encapsulation.The major part of manufacturing technology steps is used in partially patterned bonding jumper side being formed as web shape lead frame and performs, with make the lead frame of web shape be also mechanically rigidity with robust on thermodynamics not have distortion or shifting ground to perform during chip attach and wire bonding technique, in chip-scale and package level.Only after the front side use encapsulant comprising chip and wiring seals hermetically, the bottom side of die-attach area is patterned with isolating chip pad and wire-bonded contact.The gained encapsulation be electrically isolated from each other allows to carry out extension test and reliable singualtion.

Description

Partially patterned lead frame and manufacture and use its method in semiconductor packages
The application is the U.S. Patent application S/N.12/875 submitted on September 3rd, 2010, the part continuation application of 248, U.S. Patent application S/N.12/875, 248 is the U.S. Patent application S/N.11/877 submitted on October 24th, 2007, 732, be now US7, 790, the continuation application of 500, U.S. Patent application S/N.11/877, 732 is the U.S. Patent application S/N.11/553 submitted on October 27th, 2006, 664, be now US7, 799, the part continuation application of 611, U.S. Patent application S/N.11/553, 664 is the U.S. Patent application S/N.11/197 submitted on August 4th, 2005, 944, be now US7, 622, the part continuation application of 322, and U.S. Patent application S/N.11/197, 944 is the U.S. Patent application S/N.10/916 submitted on August 10th, 2004, 093, be now US 7, 129, the continuation application of 116, and U.S. Patent application S/N.10/916, 093 is again the U.S. Patent application S/N.10/134 submitted on April 29th, 2002, 882, be now US 6, 812, the continuation application of 552.All these applications are completely by reference incorporated into this.
Technical field
The present invention relates generally to Electronic Packaging, particularly relate to partially patterned lead frame and for the manufacture of with use its method.It is firmer and more stable that partially patterned lead frame compares conventional lead frame.The robustness of partially patterned lead frame improves the technique and the total reliability strengthening final products that manufacture leadframe package.Lead frame also provides the functional of high degree of flexibility and increase for device is integrated.
Background of invention
Manufacturing in the Electronic Packaging using lead frame, there is some processing steps making lead frame stand machinery and thermal stress.The integrated level of the finer geometry of current leadframe and the further increase of semiconductor core on-chip circuit has caused the process applying even larger stress on lead frame.The lead frame of meticulous configuration usually similar very exquisite needlework or tend to the stencil-like metal structure that easily bends, break, damage or be out of shape.(see Fig. 1 a and 1b).These conventional lead frame are in the industry in order to create the various chip packages comprising wire-bonded and flip-chip (FC) and encapsulate.(see Fig. 2 a-2d and 3a-3b).
Conventional lead frame lacks the rigidity of structure usually.The finger-type part of lead frame can be very fragile and be difficult to remain on original position.This causes process defect, damage and distortion in the wire-bonded situation of integrated technique and complexity.Thus, splice parameters has to be optimized to the lead frame spring of compensation during joint technology.Splice parameters cannot be optimized and can cause poor joint viscosity with the mechanical instability of compensating lead wire frame, and thus poor bond quality and reliability.
The large metal plate sections of usual lead frame is from being called chip housing region, extending also referred to as the center of chip bonding pad.Chip is attached to housing region usually, and dorsal part down and front side be placed with and face up, and terminal be peripherally placed in chip periphery on or be placed in the form of an array on the surface of chip.Housing region has the size of about 5mm x 5mm usually, and has the thick typical sizes of the wide x0.2mm of about 10mm long x 1mm from the outward extending lead-in wire of chip-pad area.Lead frame is compressed by vacuum chuck and mechanical clamp usually.Chuck and fixture must be reequiped for the lead frame of different size and shape.The invention solves this problem.
Prior art not yet illustrates and anyly tolerates the stress run in current semiconductor packaging technology and the lead frame that can manufacture in a cost effective manner.The present invention realizes this object by providing partially patterned lead frame, and this partially patterned lead frame not only improves the manufacturability of lead frame self, and improves integrated level and the reliability of the Electronic Packaging formed from it.The present invention also solves the device complexity demand continued to increase that can not provide for conventional lead frame, the flexibility in such as high I/O number, multi-chip design, system in package and wiring.
The size of computer chip is also continuing to reduce.For the lead frame with specific dimensions, the use of the chip that scales diminishes makes the wire-bonded between chip terminal and electrical connection dish elongated.Shake during can making to be routed in process to the needs of longer wiring, and likely make the wafer-level package of particular type be easy to short-circuit.
The length of arrangement wire increased progressively also affects unit cost.Usually, gold thread is used for computer chip to be connected to terminal pad.In 5 years, in fact price of gold has turned over three times in the past, and along with die size reduction, the amount of gold thread increases, thus causes the remarkable price pressure to chip package manufacturer.Although coating line is the alternative of gold thread, its your 2-3 doubly.
The layout of lead-in wire on lead frame can regulate sometimes, but the ability of the layout of amendment lead-in wire depends on the configuration of lead frame and the production capacity of manufacturer.Fixing wire locations likely needs the technology in special formation loop when bond wire, thus makes engaging process slack-off and do not eliminate the possibility of short-circuit completely.
The encapsulation of some computers needs radio shielding (RF shielding), disturbs it correctly to play function to prevent electromagnetic field when encapsulation work.Lamination device usually has this RF and shields, but this is very expensive feature.There is the electronic device standard (" moisture sensitivity rank ") of the industry acceptance that can expose time quantum in room conditions for moisture sensitivity device.The nominal level of many laminate is MSL 3.At MSL 3, after taking out from damp proof bag, assembly must be installed and reflux in 168 hours.
Sawing is usually used in making lead frame singualtion, thus forms each wafer-level package, and partly cuts lead frame to expose expectation metal level, thus is connected to special characteristic, such as EMI (electromagnetic interference) curtain coating.But carrying out many wheels with a saw can affect productivity and product recovery rate.When exposed metal surface be generally 5-18 μm thick time, the high level of Sawing Process controls guaranteeing that correct saw blade height is important.
Summary of the invention
Lead frame is made up of the film with end face and bottom surface.But the first area of film is partially patterned from end face arrives bottom surface not entirely through film.The second area (not from top plane view patterning) of film forms the lead contact for the chip housing region and multiple electrical connection for being provided to IC chip supporting integrated circuit (IC) chip.First area forms groove in film, and produces interconnection not from the web shape structure of the second area of summit portion patterning.The invention still further relates to a kind of method of lead frame of fabrication portion patterning and adopt the Electronic Packaging of these lead frames.Lead frame of the present invention is because its web shape or the web shape architecture advances rigidity of structure.
According to the present invention, first use end face that the photoetching technique of standard or similar techniques patterning form the metal film of lead frame by it to draw the profile with chip housing region and the corresponding region that goes between.At next step, be etched in the first area of drawing outside contour area of film and perform, from the end face of film through the thickness of lower membrane to produce leadframe pattern film.After partially patterned, do not form second area from the remaining area of top plane view patterning, it will be used as chip housing region and the lead-in wire along end face.First area forms the recessed web shape region under the end face of film.The web shape structure of first area makes lead portion be interconnected and is connected to chip housing region.Thus, partially patterned film looks similar with webfoot (webbed foot) and keeps its rigidity and intensity, so it can tolerate the stress of subsequent manufacturing procedures step.Especially, partially patterned lead frame can tolerate the stress met with during wire-bonded and packaging technology.In certain embodiments, chip housing region and electrical lead can be formed from the same section of second area (such as, when electrical lead supports integrated chip and provides the electrical connection with it).
The present invention also provides a kind of unique method using partially patterned lead frame to manufacture multiple Electronic Packaging.The method relates to the film with end face and bottom surface.In the first region, film from summit portion patterning but be not pass completely through arrive bottom.Film do not form multiple partially patterned lead frame from the residue second area of summit portion patterning.So lead frame has one separately for supporting the chip housing region of integrated circuit (IC) chip and multiple for providing the electrical lead with the electrical connection of IC chip.
The first area of film forms the web shape structure that the electrical lead of chip housing region and each lead frame is interconnected.First area also makes multiple lead frame be interconnected in the street of film (street) part.
Be provided with multiple chip, each chip has the multiple electric terminals for being attached to respective leadframe.Each chip is attached to the chip housing region in respective leadframe and is connected electrically between one of at least one terminal of each chip and the electrical lead of lead frame and formed.In addition, encapsulant be applied to lead frame and film street portions on the top of complete coverlay.Once encapsulant is dried up, back-patterning technique just performs with the street portions removing web shape structure and film from the bottom surface of film in first area.Then the encapsulant be arranged on the street portions of film is encapsulated to form each by singualtion.
In a preferred embodiment, the method comprises the film in the matrix be formed as by lead frame in frame/pattern of windows, and relates to the production of wafer-level package.
Some advantages produce from partially patterned lead frame of the present invention.Smooth and the solid non-etched bottom surface of lead frame is used as outstanding heat sink during wire bonding technique.This provides uniform Heat transmission for better with more consistent bond quality.In addition, solid construction provides continuous print surface for universal vacuum chuck compresses lead frame, thus makes chip attach technique during subsequent process steps more stable and go between safer.The clumsiness clamping of the outer rim of lead frame is eliminated to allow array matrix leadframe design and processing and without the need to conversion.Because the bottom side of partially patterned lead frame is smooth continuous surface, so universal vacuum chuck can be used to the frame compressing many different sizes.This removes the complexity adopting in packaging technology at every turn and have to reequip vacuum chuck during the lead frame of different size.In addition, not to the further demand of clamp.The use of universal vacuum chuck and the elimination of clamping allow the staggered leads constructing two row or three row on the second region to obtain the lead-in wire of higher number.
The present invention relates to and will not only hold wire-bonded chips but also hold the partially patterned lead frame welding convex flip-chip.In addition, teaching of the present invention is a kind of for manufacturing etched lead frame encapsulation (ELP) using wire-bonded, the ELP (ELPF) with flip-chip and having bank grid array (LGA) pad to form the method that etching bank grid array (ELGA) ELP or ELPF that encapsulate uses partially patterned lead frame, as described in further in various embodiments of the present invention.
Flip-chip (FC) technology is to another step being completely automatically attached to next stage encapsulation by the electric terminal on chip, and the encapsulation of this next stage is pottery or plastic base or is attached to the chip microcarrier (microcarrier) of substrate after a while.Microcarrier (it is only a bit larger tham chip itself) is called wafer-level package (CSP) now.FC technology engages (TAB) from band automation and develops, and TAB develops from wire-bonded (WB).Although be placed on the back side in WB and TAB chips and be electrically connected the terminal around the periphery be positioned on its end face, but be inverted in the orientation of FC technology chips.Chip quilt cover down place and the dorsal part of chip upward.This flip chip orientation has remarkable advantage, because it concentrates Electricity Functional in the downside of chip, leaves top side and freely uses when developing the design of efficient Heat transmission.
In FC technique, the dissimilar projection sealing on the surface of chip terminal or bond pad chip, wherein pattern can be arranged to area array, peripheral pattern or other pattern.Chip can be attached to next stage in the following manner: a) FC is attached to lead frame; B) FC of layer/substrate attached (being called insert), connects space for re-routing on lead frame; C) FC is attached to the pre-attached insert on lead frame; Or d) use the routine techniques FC comprising chip remelting method to be attached to printed circuit board (PCB).
Especially difficulty is become when using the chip attach of routine techniques to be applied to QFN (quad flat no-lead (QFN) encapsulation) lead frame in the process of growth manufacturing QFN encapsulation and such as VFQPF-N and so on thereof.This is because conventional lead frame lacks the rigidity of structure usually.The finger-type part of lead frame can be quite fragile and be difficult to remain on an exact position.This causes process defect, damage and distortion in the chip join situation of packaging technology and complexity.PC combined process needs protruding solder heads to aim at the suspension of lead frame and the accurate of lead end of fragility.In addition, the solder end got wet must remain on their position after by solder reflow technique.Therefore, the lead frame spring during remelting parameter must be optimised and combine with compensation chips, this (if untreated proper) can cause the binding site of difference, and thus causes the poor quality of final products and poor reliability.
General custom is by the photoresist on pattern metal bar or metal film and etching is worn pattern to be formed and formed conventional mould type lead frame from chip housing region outward extending finger-type lead-in wire.Also " shunt bar " (tie-bar) between finger accustomed to using, to make finger be kept separately during each processing step, as best shown in figures 3 a and 3b.The present invention is by the problem forming web shape, partially patterned lead frame but not the rigidity of structure that stencil-type lead frame solves lead frame lack.
A method according to the present present invention, all main technological steps forming semiconductor packages perform from the side that will become lead frame of film.Opposite side (i.e. bottom side) keeps smooth and does not touch on the surface on the surface of such as vacuum chuck and so on.This comprises encapsulation and the step of part hermetically sealed hermetically formation front side.Once encapsulate, bottom surface has just been etched with optionally to remove by back and lead-in wire has been interconnected and the web shape part being connected to chip housing region.Wherein chip by flip-chip bonded to the chip bonding pad on chip housing region and under carrying out with the electrical connection of chip terminal ELP situation by wire-bonded, all middle web shape parts are mutually isolated by the moulding material around the front of chip, lead-in wire and wire-bonded contact region by the cut-off lead contact of chip bonding pad and wire-bonded end that makes of etching.But, when ELFP encapsulates, only make lead-in wire interconnective web shape part be cut off, because the lead-in wire itself being connected to chip soldering stub bar projection provides the electrical connection encapsulated with next stage by etching.
The removal embedding the metal of the thick or street of saw in web shape part has some advantages, comprises the sawing force eliminated and propagate in whole lead frame structure, and therefore, prevents the layering on metal-plastic interfaces.In addition, the electric insulation etched by back make extension test can before any sawing or singualtion extension test or carried out before any further processing step.After back-patterning, the reservation on bottom surface and exposing metal part can use the weldable material of any number to carry out burr finishing (flash finish) by wicking immersion plating or chemical nickel plating.But ELGA encapsulation uses the PC of ELPF encapsulation, and LGA pad is used for being connected to next stage encapsulation.
Be separated in order to prevent during manufacture between moulding material and other assembly of encapsulation any, the present invention also teaching how on the exposure vertical wall of the recessed web shape part of partial etch lead frame (such as on the sidewall of lead-in wire) form Lock Part, these parts are by the molding material contacts with such as resin and so on.As replacement, also teaching forms " antelabium " on the edge of chip bonding pad and lead contact, so that catch the moulding material under each antelabium, thus makes moulding material be difficult to be separated with match surface.
From obviously above, partially-etched lead frame provides the consistency of structure and adjoint rigidity and intensity to tolerate the stress and strain of various manufacturing process well when manufacturing Electronic Packaging.This is because the mechanical property of these uniquenesses causes, make partial etch lead frame encapsulate the tight ultrasonic joint routing to package bottom that also resistance toly can be exposed for and to be connected to next stage encapsulation, this is impossible for conventional plastic package up to now.
One aspect of the present invention provides a kind of method for the formation of Electronic Packaging.The method comprises the one piece of partial etch lead frame being formed and have selectivity pre-galvanized end face and bottom surface.This lead frame is comprised web shape part and is separated from each other by street portions.
First core assembly sheet is attached to the chip-pad area on lead frame.For simplicity, the region of supporting integrated chip (IC) or the IC die attach lead frame on it will be called as chip-pad area or chip housing region, no matter this region is for wire-bonded chips, flip-chip or other type any known in the art.These chips of first group can use adhesive, resin or other material flip-chip bonded compatible with these two assemblies to chip housing region.Such as, flip-chip bonded can use epoxy resin, non-conductive epoxy resin, band or soldering paste to complete.Other suitable material is well known in the art.
Second core assembly sheet then tube core is stacked on the top of corresponding first core assembly sheet.After on the second core assembly sheet to be stacked in the first core assembly sheet top by tube core, other chipset one or more can be stacked on the top of the second core assembly sheet by tube core, thus provide comprise be stacked in top of each other two, three, or more the encapsulation of a chip.In certain embodiments of the present invention, not that all chips in the first core assembly sheet can have the chip that tube core is stacked in their tops.In these embodiments, lead frame will have one or more single (non-closed assembly) chip and one or more groups tube core closed assembly chip.
The electrical lead portion of the terminal and respective leadframe that are connected electrically in each of the first chip is formed between dividing.Electrical lead part and chip-pad area electric insulation.Also the electrical connection with second or additional chips group is formed.Multiple electrical connection can be formed after chip is stacked on lead frame by tube core simultaneously.Alternatively, the first core assembly sheet is attachable and be electrically connected to lead frame, and subsequently second or additional core assembly sheet can be stacked to the top of the first core assembly sheet by tube core and be electrically connected to lead frame.
To be stacked on lead frame by tube core and after being electrically connected to lead frame at chip, lead frame then by lead frame and separate lead frame street portions on apply encapsulant to encapsulate.After encapsulation, the bottom rear of lead frame by back-patterning to remove web shape part and street portions.Back-patterningly to perform by any facilitated method, such as by etching.
If the bottom that pre-galvanized material is applied to lead frame is such as used as photoresist, then this pre-galvanized material can be removed after back-patterning.
Isolation pattern can be formed in the bottom of lead frame after back-patterning.These isolation patterns can be plated or apply to protect its surface with material.The example of suitable material comprise Electroless Plating Ni/leaching Au, leaching Sn, organic surface-protective agent (OSP) and other weldable material.This polishing or plating step are convenient to provide additional stability to the back side of chip package, and the connectivity through improving of other position that tolerable and computer plate, socket or chip package are placed.
The encapsulant be placed on street portions is encapsulated for the various application for semicon industry to form one single chip level by singualtion.Singualtion can use any any convenient means that can be used for being separated each chip package to complete.In one embodiment, singualtion is undertaken by using saw or abrasion water spray cutting sealing material.
Another aspect of the present invention provides the lead frame comprising chip-pad area and lead-in wire and have alterations (alternation).Alterations can be regarded as the element be positioned on the structure member of lead frame, and it provides the surface area of increase compared with not having the lead frame of alterations time.These alterations are coated on the encapsulant on lead frame before being convenient to be retained in singualtion.These alterations can be any type of, the recess on the electrical lead of such as lead frame.
Each of second core assembly sheet can be identical or different with corresponding first die size.In addition, the first core assembly sheet being attached to lead frame needs not be all identical, and thus these the first core assembly sheets can comprise greater or lesser chip.Usually, maximum chip will be attached to chip-pad area and more and more less chip will be stacked in the top of this chip by tube core.In an alternate embodiment, maximum chip will not be attached to chip-pad area, but by the centre of tube core closed assembly chip or top.The large I of tube core closed assembly chip is all identical.
Second group can use any convenient means closed assembly known in the art with the chip of additional group and join corresponding first chip to.Such as, chip can use the insulating material closed assembly of non-conductive epoxy resin or such as band and so on to prevent between chip or within interference or electric moveable.In another embodiment, the second core assembly sheet can use band, electroconductive binder or conductive epoxy resin to be attached to corresponding first chip.
First core assembly sheet uses known technology to be electrically connected to lead frame.Such as, chip can use wire bond technology or use flip chip technology (fct) to be connected to lead frame.
First core assembly sheet can be electrically connected to lead frame before second group of chip-die is stacked in the first chip.Alternatively, the first core assembly sheet can be connected to lead frame after second group or additional group chip-die is stacked on corresponding first core assembly sheet.The step forming electrical connection realizes by the end of each connecting terminals on chip being received the electrical lead extending to chip area.Electrical connection can use any facility or proper technology to be formed.Such as, if fruit chip is wire-bonded chips, then connect the wire bond technology that such as hot sound can be used to engage (thermasonic bonding) and so on and formed.Flip-chip is electrically connected to lead frame by usually using flip chip technology (fct).The combination of wire-bonded and flip chip technology (fct) also within the scope of the invention.When flip-chip is attached directly to lead frame, corresponding lead-in wire can be plated or not electroplate.
Second core assembly sheet received power is to perform calculating or other function.This second core assembly sheet can be electrically connected to corresponding first chip, lead frame or they both.The concrete condition of the join dependency set up between each chip and lead frame in vicinity and the particular electronic package of formation.
Chip type used in this invention also will depend on specific environment.Such as, chip can be the chip of wire-bonded chips, flip-chip or other type any being applicable to electronic chip packaging.In one embodiment, the first core assembly sheet comprise flip-chip or wire-bonded chips or they both, and second group and any sheet of core assembly subsequently comprise wire-bonded chips.What one in chip also can comprise semiconductor device.
Certain height will be had after encapsulation and singualtion according to the Electronic Packaging that the present invention is formed by tube core closed assembly chip.In order to reduce the height of Electronic Packaging, chip-pad area can be recessed into the height reducing obtained encapsulation.That is, the chip bonding pad on lead frame can be formed as having reduce inner so that make chip can load this region in and therefore provide to have to reduce chip highly.
The Electronic Packaging formed according to disclosed method is firm and stable.Be encapsulated in stress state and the further reliability during manufacturing to provide, alterations can be used to the reservation increasing encapsulant.Alterations can be arranged along chip bonding pad, lead-in wire or the periphery both them.
The selectivity pre-galvanized of bottom lead frame can be used to the bottom part limiting lead frame.This selectivity pre-galvanized can provide similar pattern at the end face of lead frame and lower surface.Selectivity pre-galvanized can use any convenient material to complete.In one embodiment, NiPdAu or silver alloy are used to pre-galvanized lead frame.
After encapsulation, tube core closed assembly chip by by solid sealing material around to prevent moving or weakening of the electrical connection between chip and lead frame.The closed assembly chip of whole group can be covered by encapsulant.Alternatively, a part for the most top layer chip at the such as back side or end face and so on can keep exposing after encapsulation.Such as, the remainder that the surface of most top layer chip can penetrate the chip in encapsulant and embedding sealing material exposes.In this way, the amount of encapsulant can be reduced and can not the stability that finally encapsulates of dramatic impact.In addition, if the end face of most top layer chip or the back side comprise identification information, then encapsulation can be formed as making this information do not covered by encapsulant and can check with being suitable for a user to easily.
As discussed previously, chip and tube core closed assembly chip electricity are attached to lead frame so that provide electric power to chip.Except the chip of such as flip-chip or wire-bonded chips, other element also can be connected to lead frame.These additional elements can be provide the supporting of increase or the structural detail of stability to encapsulation.Additional element can also be the electric device of the function of supporting chip or chip package.The example of these add ons is passive block, isolation pad, power ring, ground loop and selected wiring.These and other structure in chip package or any combination of electric device are within the scope of the present invention.
Encapsulating material can be the material of any type, and it can be coated to tube core closed assembly chip or solidify to form curable solid.In one embodiment, encapsulant can be around chip and harden with the liquid resin obtaining chip.The example of encapsulant is epoxy resin.Normally non-conductive material is jumped to another to prevent the signal of telecommunication in encapsulant from a chip by encapsulant.
When additional element comprises electric device, these elements can be that directly electrical connection or Indirect Electro are connected to lead frame.These additional elements also can be electrically connected to the one or more chips in encapsulation, and these embodiments can be dependent on formed concrete wafer-level package.
Lead frame also can use production technology known in the art to be formed.Such as, lead frame can use chemical etching, punching press or stamping technique to be formed.
Lead frame can apply with the film coating of the material of such as electric conducting material and so on or part.This film can provide lead frame and provide the electric throughput of increase (compared with not having the lead frame of such film) between the chip being attached to lead frame.In one embodiment, film is formed by copper or copper alloy.The thickness of film is not crucial usually, although film will be had to enough thick in have mechanical stability.In one embodiment, the thickness of film is more than or equal to about 0.05mm.
Another aspect of the present invention provides the lead frame comprising chip-pad area and lead-in wire.Lead frame has the alterations providing the increase of the encapsulant covering lead frame to retain.Chip will usually be attached to chip-pad area and be electrically connected to lead-in wire.
Alterations can be configured to be provided for by structural design the increase surface area retaining encapsulant.Alterations can adopt the form of any type providing the increase of encapsulant to retain.Such as, alterations can be the shape of hole, depression or recess, its be positioned on lead frame or lead frame a part on.Alterations also can appear at and be formed with on the lead-in wire of the electrical connection of chip.
Alterations can in any part of lead frame.Such as, alterations can on both the periphery of chip-pad area or lead-in wire or they.Alterations can also be the form of roughening chip-pad area, lead-in wire or the periphery both them.
Except providing except alterations for the improvement of encapsulant retains, the surface of lead frame can be roughened the surface area providing increase.To encapsulant will be convenient to be adhered to the surface of lead frame through the surface of roughening.
Wire clamp can preferably be used for replacing wire-bonded thus to improve the performance of chip to increase electric power to the flowing of chip.
In another embodiment of the invention, a kind of method of Electronic Packaging for the formation of having ultrasonic bond wire is provided.Form one piece of partially-etched lead frame, by the lead frame that street portions is separated from each other, there is continuous print bottom surface comprising web shape part.Chip is attached to the chip housing region on lead frame.Be electrically connected between the terminal of each chip divides with the electrical lead portion of respective leadframe.Wiring is joined to the bottom surface of lead frame ultrasonically.Lead frame by lead frame, the street portions comprising isolation lead frame applies encapsulant to encapsulate.Then perform the back-patterning of bottom surface and remove web shape part and street portions.Through encapsulation lead frame then on street portions by singualtion to form wafer-level package bottom surface with ultrasonic bond wire.
One embodiment of the invention provide a kind of method forming wafer-level package.The method comprises formation one piece of partial etch lead frame, and this lead frame comprises web shape part, chip mounting area, multiple electrical lead part and street portions.Integrated circuit (IC) chip is attached to the chip mounting area of the first area of film.The one or more terminal of electrical connection then on chip and the one or more electrical lead portion on lead frame are formed between dividing.Lead frame then by applying encapsulant encapsulation on lead frame and street portions.Then the bottom surface of lead frame is etched with by back and removes web shape part, street portions and chip mounting part, thus the lead frame of whole or considerable part below integrated circuit (IC) chip is removed.Be placed in encapsulant on the street portions of film then by singualtion to form each wafer-level package.The chip of any number of any type is attached to partially patterned lead frame.
Lead frame can carry out optionally pre-galvanized with pre-galvanized material, or they can before encapsulation with mask material they top side, bottom side or both on shelter.If lead frame is masked, then regulation can be there is to the opening on the solder mask of the expectation terminal pad for being connected to printed circuit board (PCB) (PCB).
Lead frame can carry out optionally pre-galvanized by any facility or conventional substances.The example of these materials comprise Ni/Pd/Au-strike, Sn/Pb, lead-free solder, wicking chemical nickel plating, silver (Ag) and Au (gold) strike.
Lead frame also can be sheltered with any facility or conventional masking substance, such as can printer's ink, tusche, epoxy resin ink or organic substance.
Pre-galvanized material or mask material at any appropriate time, such as can be removed from the bottom of lead frame after back-patterning.
Lead frame can be formed by any suitable material known in the art.Such as, lead frame can comprise the film of copper or copper alloy or the film of another metal or metal alloy.
As discussed previously, integrated circuit (IC) chip is attached to the chip mounting area of lead frame.Chip useful binders or other known in the art can stereognosis or fixed substance attachment.Such as, adhesive can be resin, epoxy resin, soldering paste or band.
Lead frame can be used and such as be formed by the common process of chemical etching, impression or pressure-sizing and so on.
Chip can use and such as be connected to lead frame by the suitable electrical connection means of wire-bonded and so on.
In a further embodiment, method of the present invention allows at the multiple chip of chip mounting area tube core closed assembly.Such as, the method can comprise and one or more second chip-die being stacked on the top of the integrated circuit (IC) chip being attached to lead frame.These second chips can be electrically connected to lead frame, or are attached to the integrated circuit (IC) chip of lead frame, or both them.The combination of these methods of attachment is possible.Second chip can also be electrically connected to each other.
Another aspect of the present invention provides partially patterned lead frame for manufacture Electronic Packaging.
Partially patterned lead frame can be made up of the film with end face and bottom surface.This film can have end face, and it has (a) from summit portion patterning but not exclusively through the first area of bottom surface, and (b) be not from the second area of summit portion patterning.Second area can form chip-pad area for supporting integrated circuit (IC) chip and the multiple electrical leads for the electrical connection that is provided to IC chip.Chip-pad area can be connected via first area with multiple electrical lead, but does not connect via end face.End face also from bottom surface portions patterning, but not exclusively can be passed through in the bottom surface of film.
The end face of lead frame and bottom surface can any ad hoc fashion patternings.Such as, end face and bottom surface can supplement pattern, have basically identical feature to make two surfaces on the both sides of lead frame.
The bottom surface of lead frame can be patterned as opening, passage or they both.These openings or passage advantageously allow lateral ventilation hole and lateral ventilation, so do not have entrapped air during remelting.
The further embodiment of another aspect of the present invention provides a kind of method for the formation of wafer-level package.The method comprise provide have (a) from summit portion patterning but not exclusively through the first area of bottom surface and (b) not from the second area of summit portion patterning.Second area forms (a) for supporting the chip-pad area of integrated circuit (IC) chip and (b) for being provided to multiple electrical leads of the electrical connection of IC chip.Chip-pad area can be connected via first area with multiple electrical lead, but is not connected by end face.
Then integrated circuit (IC) chip is attached to the chip-pad area of the first area of lead frame.The one or more terminal of electrical connection then on chip and the one or more electrical lead portion on lead frame are formed between dividing.Lead frame then by applying encapsulant to encapsulate on lead frame and street portions.The bottom surface of lead frame then by back-patterning to remove web shape part and street portions.The fraction of the bottom surface of chip-pad area is also removed to form the one or more passages by chip-pad area.These passages advantageously allow lateral ventilation hole and lateral ventilation, so do not have entrapped air during remelting.Be placed in encapsulant on the street portions of lead frame then by singualtion to form each wafer-level package, it is got ready for follow-up use.
The passage of chip-pad area extends in the length of whole chip-pad area, or they can extend in a part for chip-pad area.These passages can be the forms of opening (hatching) or other similar structures.
Another aspect of the present invention is provided in the manufacture of Electronic Packaging the partially patterned lead frame used.Lead frame is made up of the film with end face and bottom surface.This film from summit portion patterning, but imperfectly through bottom.Film is also from bottom surface portions patterning but be not completely through end face.Patterning on end face is darker than the patterning on bottom surface.Gained lead frame has at its top compares patterning darker bottom it.Two-sided etching allows each several part of lead frame to have reduction thickness, and these parts will finally be removed and the thus process of streaming gained Electronic Packaging and manufacture.
Another aspect of the present invention provides a kind of wafer-level package with bottom surface with passage.Wafer-level package comprises one or more computer chip through encapsulation and is used as pore to reduce or eliminate the passage of entrapped air during remelting.
Feature of the present invention provides the remarkable advantage being better than prior art.The invention provides the feature of system in such as encapsulation, and increase along with package dimension reduces electricity, heat and I/O.Flexibility of the present invention makes the ELP type of novelty encapsulate the requirement that can adapt to become increasingly complex.
Although above-mentioned all embodiments of the present invention provide the wafer-level package of the improvement having remarkable practicality and be better than prior art, in instantiation, supplementary features can provide advantage.
Such as, an embodiment of another aspect of the present invention provides a kind of use to introduce the method that lead-in wire (pull-in lead) forms Electronic Packaging.These are introduced lead-in wire and electrical connection dish can closer to chip attach region or side's placement even under the die, and be allowed to be electrically connected more easily.
Introduce lead-in wire usually to have and coils large surface area than conventional electrical connection, therefore allow wire-bonded or upside-down mounting attached time have greater flexibility.Introduce lead-in wire also to allow to use less wiring in wire-bonded.Because the gold thread that wiring is normally expensive, so suitable cost has been saved in the minimizing of the amount of these lines, the amount being namely used in the metal of lead-in wire or trace has slightly increased.
The method comprises: formed and have the end face of selectivity pre-galvanized and the partial etch lead frame block of bottom surface, and these lead frames comprise web shape part, chip attach region and introduce the electrical connection disc portion of lead-in wire form.Electrical lead part and chip attach region electrical separation, and lead frame is separated from each other by compartment.Introduce lead-in wire and in conjunction with solder resist, ink or or desirable any other materials'use required to the correct function of lead frame or gained wafer-level package can be considered as.
Chip is attached to the respective chip attachment levels of lead frame, and forms one or more electrical connection between one or more terminal of chip divides with one or more electrical lead portion of respective leadframe.Then package leadframe is carried out by applying encapsulation agent material on the compartment of lead frame and separate leadframes.The step of chip attach to chip attach region is optionally comprised: chip is placed in active lead-in wire (or contrary, lead-in wire by active in final wafer-level package) on, active lead-in wire will when lacking chip bonding pad supporting chip, and use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to carry out adhering chip.In this embodiment, electrical connection will be formed between active lead-in wire and integrated circuit (IC) chip.
The bottom surface of lead frame then by back view patterning to remove web shape part and compartment; And lead frame carrys out singualtion, to form each wafer-level package by the cutting encapsulation agent material be placed on compartment.
The chip attach region (holding district or chip installation area also referred to as chip) of lead frame can have any ad hoc structure for holding computer chip.Such as, chip attach region can be the landless part of chip soldering panel or lead frame.
In all embodiments of the present invention introducing lead-in wire can around corresponding chip attach region or near arrange in any convenient manner.Such as, introduce lead-in wire and can be arranged in single file at chip circumference, or they can be arranged in multirow around the respective chip attachment levels of lead frame.
Electrical lead can also be the combination in any of dissimilar lead-in wire.Such as, lead-in wire can be introduce lead-in wire arbitrarily, or lead-in wire can be the combination introducing lead-in wire and electrical connection dish.
Back-patterning step can use the method for any convenience or practicality to perform.Such as, back-patterningly partially-etched or overflow etching is used to carry out.Similarly, encapsulation step can use any means easily to carry out, and such as or individual unit molded by block material is molded.
The chip attach region of lead frame can have any structure easily.Such as, chip attach region (or any portion of lead frame) can comprise one or more heat through-hole (the vertical electrical connection in PCB design between different conductor layer).
After singualtion, such as the solderable material of soldered ball or weldering paint can be adhered to one or more electrical connection dishes of wafer-level package before or after singualtion.Solderable material is convenient to the connection of the electronic hardware of wafer-level package and circuit board or other type.Solderable material can have the formation of any novelty or routine, such as tin, copper, silver, bismuth, indium, zinc and/or antimony.
The IC chip being attached to lead frame can have any suitable or conventional structure.Dissimilar chip also can be engaged to the different chip attach regions on identical lead frame.Such as, wire-bonded chips and flip-chip can be used, and particular leadframe instance can support polytype chip and die stacks.Chip can use any suitable means to be attached to chip attach region.The example of proper technology comprises use conductive epoxy resin, non-conductive epoxy resin or attached die film adhesive.
Equally, the technology of any suitable type can be used to realize electrical connection.Such as, electrical connection can use wire bond technology, flip chip technology (fct) or its combination to be formed.The step forming electrical connection has been come by the end connecting terminals on chip being connected to the electrical lead part extended from lead frame, and lead portion can be electroplated or do not electroplated.The particular technology being used for chip electrical to be connected to lead frame will depend on the present invention's concrete configuration during fabrication and embodiment.
The bottom surface that the inventive method can be included in back-patterning backward lead frame further applies non-conductive coating.This non-conductive coating can be used to protection lead frame not by mechanical wear or consume, therefore can strengthen the durability of gained wafer-level package.The intention of coating is between PCB installation period, make active introducing lead-in wire avoid short circuit.Desired location open or exposure by maintenance of electrical connection dish or pad, so that provide necessary electrical connection.
In other embodiments of the invention, the inventive method applies electromagnetic interference (EMI) shielding to wafer-level package before or after can being included in singualtion further.This electromagnetic interference shield is eliminated or is significantly reduced the coupling of the undesired radiation electromagnetic energy that may occur in electric device at least in part.The preparation of prior art wafer-level package generally needs the part of leadframe substrate or lamination to cut to expose expectation metal level, is connected to ground connection for by EMI shielding.Because the thickness of the metal trace of RF magnetron sputtering normally 5-18 μm, so technology controlling and process is crucial.On the contrary, ELP platform of the present invention is specially adapted to apply EMI shielding, because it has the technology controlling and process more wide in range than other types of leads frame owing to employing thicker lead frame.In addition, ELP platform of the present invention also can be selected to use bag mould to be molded during encapsulating and avoids partly cutting lead frame.In this embodiment, bag mould molding process does not encapsulate whole lead frame, but makes the metal exposed of a part of lead frame and can be used for being connected to EMI shielding so that ground connection.
Electromagnetic interference shield can use any common process to apply, such as chemical plating, metallide, injection, dipping, sputtering sedimentation or silk-screen printing technique.
One single chip with reference to the chip attach region pasting lead frame discusses the present invention.In other embodiment in this respect of the present invention, method can be included in package leadframe before the multiple chip of tube core closed assembly.Such as, a chip can be adhered to chip attach region, and the second chip can be adhered to the top of the first chip.The chip of overlappable any amount is to form wafer-level package of the present invention.Each chip by another chip of being electrically connected in lead frame, lamination or both.These chips can use other technology any in wire bond technology, flip chip technology (fct) or both and this area to connect, and this arrangement is by the specific embodiment during depending on manufacture and configuration, and any this embodiment can be incorporated on single lead frame.
Accompanying drawing is sketched
Fig. 1 a is the diagram with the conventional lead frame of lead-in wire and chip-pad area according to prior art.
Fig. 1 b is the diagram of the conventional lead frame of Fig. 1 a according to prior art, shows the wire-bonded of terminal on the attached and chip of chip and chip bonding pad and lead-in wire.
Fig. 2 a is the sectional view of the encapsulation of the near chip level through wire-bonded and leaded (having lead-in wire) (CSP) according to prior art, shows the connection encapsulated by lead-in wire and next stage.
Fig. 2 b be according to prior art through wire-bonded and the sectional view of approximate CSP without lead-in wire (not there is lead-in wire), show the connection encapsulated by solder projection or soldered ball and next stage.
Fig. 2 c is the sectional view through flip-chip and leaded approximate CSP according to prior art, and the connection encapsulated by lead-in wire and next stage is shown.
Fig. 2 d be according to prior art through flip-chip and the sectional view of approximate CSP without lead-in wire, show the connection encapsulated by soldered ball and next stage.
Fig. 3 a is the vertical view of the stencil-type lead frame according to prior art, shows flip-chip bonded chip and is connected with the wire-bonded that lead frame goes between.
Fig. 3 b is the vertical view of the stencil-type lead frame according to prior art, shows the connection gone between by flip-chip bonded chip and the lead frame of solder reflow technique.
Fig. 4 is can the sectional view of grafting material metal film of uniform thickness pre-galvanized on both sides according to use of the present invention.
Fig. 5 is the sectional view of the metal film according to Fig. 4 of the present invention, and the pre-galvanized layer wherein only on end face has corresponded to two chip positions and has been patterned, and each position comprises chip bonding pad and the lead contact around each chip bonding pad.
Fig. 6 is the sectional view of the electroplating metal film according to Fig. 4 be partially patterned of the present invention.
Fig. 6 a is the vertical view of the matrix illustrated according to partially patterned lead frame of the present invention.
Fig. 6 b and 6c illustrates the progressively amplification plan view of the lead frame in the matrix shown in 6a.
Fig. 7 a is the sectional view of the partially patterned metal film according to Fig. 6 of the present invention, its chips be attached to two chip positions each on chip bonding pad.
Fig. 7 b is according to the enlarged drawing that the junction between the chip of the attached thing comprising epoxy resin or solder and chip bonding pad is shown of the present invention.
Fig. 8 is the sectional view of the chip attach metal film according to Fig. 7 a or 7b of the present invention, the terminal wherein on each chip by wire-bonded on each chip position the lead portion of lead frame that formed.
Fig. 9 is the sectional view of the wire-bonded lead frame according to Fig. 8 of the present invention, has been hermetically sealed in encapsulant comprising the end face of the metal film of chip and wire-bonded.
Figure 10 is the sectional view of the encapsulation of hermetic seal according to Fig. 9 of the present invention, this encapsulation from back side etch to remove the street regions the first area of each lead frame and film.
Figure 11 is the sectional view of the partially patterned encapsulation of two near chip sizes according to formation of the present invention two individual packages, wherein encapsulant in street regions by singualtion.These encapsulation can use aluminum steel, copper cash soldered ball joining technique or use any other easily joining technique come ultrasonic joint.
Figure 12 a is the vertical view one of encapsulated according to the singualtion of Figure 11 of the present invention, and it illustrates the amplification cross section of chip, contact chip terminal being connected to lead contact and one of wiring and the contact with wire-bonded.
Figure 12 b is the sectional view according to the region between one of chip bonding pad of the present invention and contact, and it illustrates and uses with " antelabium " in the vertical surface of molding material contacts so that provide grappling and prevent layering.
Figure 12 c is the sectional view according to the region between one of chip bonding pad of the present invention and contact, and it illustrates and uses with the difformity hole in the vertical surface of molding material contacts so that provide grappling and prevent layering.
Figure 13 a-13f is according to the diagram that can be used to the various holes providing grappling means for the moulding material in the vertical surface shown in Figure 12 b and 12c of the present invention.
Figure 14 is the flow chart of the various processing steps according to conclusion forming section patterning encapsulation of the present invention.
Figure 15 a is according to the diagram that vertical view, end view and the upward view with the encapsulation that peripheral I/O configures is shown of the present invention.
Figure 15 b is the diagram according to vertical view, end view and upward view that the encapsulation of the array configurations with I/O pad is shown of the present invention.
Figure 16 is the sectional view of the metal film according to Fig. 4 of the present invention, and the pre-galvanized layer wherein only on end face has corresponded to two chip positions and has been patterned, and each position comprises chip attach region and the lead-in wire around each chip attach region.
Figure 17 is according to the sectional view being partially patterned the electroplating metal film of the Figure 16 forming web shape lead frame (i.e. web shape structure) of the present invention.
Figure 18 is according to the sectional view that the chip-joined lead frame (FCL) that flip-chip (FC) combines is shown of the present invention.
Figure 19 is the sectional view of the FCL according to Figure 18 of the present invention, and the end face comprising the metal film of chip has been hermetically sealed in encapsulant.
Figure 20 is the sectional view of the encapsulation of hermetic seal according to Figure 19 of the present invention, this encapsulation from back side etch optionally to remove the web shape part between each lead-in wire and between each recessed chip attach region.
Figure 21 is from the sectional view of the partially patterned encapsulation of two near chip sizes of the encapsulation singualtion of Figure 20 according to of the present invention.
Figure 22 a is the vertical view one of encapsulated according to the singualtion of Figure 21 of the present invention, and chip and lead-in wire are shown for it and chip terminal is connected to the end of lead-in wire, and the end of lead-in wire is connected to again the encapsulation of next stage.
Figure 22 b be according to flip-chip of the present invention and and the connection that encapsulates of next stage between the amplification sectional view in region, show two ends of lead-in wire.
Figure 23 is according to flow chart of concluding each processing step of the partially patterned encapsulation forming supporting flip-chip of the present invention.
Figure 24 a and 24b illustrates sectional view according to the partially patterned encapsulation of two near chip sizes of the present invention and upward view, and then this encapsulation is provided with by singualtion the bank grid array connector encapsulated to form ELGA type for being connected to next stage encapsulation.
Figure 25 a and 25b illustrates further optional embodiment of the present invention, and it comprises the wire-bonded that leadframe package of the present invention and next stage encapsulate.These accompanying drawings illustrate that the encapsulation of Figure 24 a and 24b uses aluminum steel (shown in Figure 25 a) or uses copper cash soldered ball joining technique (shown in Figure 25 b) ultrasonic joint.Copper cash soldered ball joining technique can be used to Flip-Chip Using to be connected to lead frame.
Figure 26 a and 26b is stereogram and the sectional view of the embodiment of the present invention, and wherein multiple chip-die closed assembly is to form semiconductor packages.
Figure 27 a-27c is stereogram and the sectional view of the embodiment of the present invention, and wherein chip bonding pad is recessed into allow the reduction of tube core closed assembly through improving and packaging height.
Figure 28 a and 28b illustrates the stereogram with the lead frame of recessed chip-pad area and tube core closed assembly chip according to the embodiment of the present invention.
Figure 29 a-29c illustrates the stereogram of the lead frame of the alterations of the chip bonding pad Lock Part form had according to an aspect of the present invention.
Figure 30 a-30d illustrates the vertical view with some class electrical leads of alterations and the end view of some embodiments according to an aspect of the present invention.Figure 31 a and 31b illustrates vertical view and the end view of electrical lead according to another embodiment of the present invention, and wherein the surface of lead frame or lead-in wire is roughened.
Figure 32 a-32e illustrates the stereogram being arranged on the some class alterations on electrical lead according to a further aspect in the invention.Figure 32 f illustrates vertical view and the end view of electrical lead according to a further aspect in the invention, wherein the surface of lead frame be roughened to provide encapsulant through improving adhesiveness.This surface roughening can combine with the alterations given by the present invention and carry out.
Figure 33 a-33b illustrates the one side of embodiments of the invention, and wherein wire clamp is used to replace wire-bonded to improve the power capability of chip.
Figure 34 a-34f illustrates the embodiment of partially patterned lead frame, do not exist, and chip is placed directly on lead frame at this lead frame chips housing region.After, wire-bonded attached in subsequent die, encapsulation and back-patterning and pre-shaping step, the part in lead frame face is under the die removed.Exposure is used for the non-conductive adhesive (such as epoxide resin material or band) of die attach in lead frame by this pre-shaping step.
Figure 35 illustrates the upward view of the wafer-level package prepared via the operation shown in Figure 34 a-34f.
Figure 36 a provides the sectional view of the wafer-level package shown in Figure 34 f.Figure 36 b provides the sectional view of another embodiment of the present invention, and wherein wafer-level package comprises the wire-bonded chips of multiple tube core closed assembly.
Figure 37 a illustrates the lead frame that wherein end face and bottom surface have been partially patterned before any chip is attached to lead frame.Figure 37 b illustrates the lead frame of Figure 37 a that chip is electrically connected with it, and this lead frame is packed before back-patterning and singualtion.
Figure 38 illustrates the wafer-level package of the wire-bonded chips comprising multiple tube core closed assembly, wherein the bottom of pipe core welding disc by opening to provide ventilation.
Figure 39 a illustrates the vertical view of an embodiment of wafer-level package according to an aspect of the present invention, and wherein electrical connection dish is all square, and is arranged in two concentric row at chip circumference, and chip is connected to electrical connection dish by wiring.To describe as following, in alternative embodiments, terminal pad can have any shape, such as, but not limited to ellipse, rectangle or circle.
Figure 39 b illustrates the vertical view of a variant of Figure 39 a embodiment, and wherein electrical connection dish is the form introducing lead-in wire, and is arranged in two row at chip circumference.Chip is connected to the end of the close chip introducing lead-in wire by wiring.
Figure 40 a illustrates the sectional view of an embodiment of wafer-level package according to a further aspect of the invention, and its chips is the flip-chip that solder joint is arranged in its periphery, and chip is electrically connected to the introducing extended the under the die lead-in wire on lead frame.
Figure 40 b illustrates the sectional view of a variant of Figure 40 a embodiment, and its chips is the flip-chip that solder joint is arranged in array pattern, and chip is connected to the electricity introducing terminal pad extended under the die.
Figure 41 illustrates for using linerless lead frame to select preparation according to the step of wafer-level package of the present invention, and the electrical connection dish wherein on lead frame is the form introducing lead-in wire.
Figure 42 illustrates the step for the preparation of the wafer-level package with electromagnetic interference (EMI) shielding material, and the electrical connection dish wherein on lead frame is the form introducing lead-in wire.
Figure 43 a-43c illustrates that using block material to be molded selects preparation EMI to shield the sectional view of wafer-level package, and wherein cell array is encapsulated in single piece.
Figure 43 d-43e illustrates that using single bag mould to be molded selects preparation EMI to shield the sectional view of wafer-level package, and wherein each unit is molded in its oneself die cavity.
Figure 44 a-44c illustrates that preparation EMI shields the sectional view of the step of wafer-level package, wherein unit first singualtion before applying shielding material.
Figure 45 a-45b illustrates partial etch lead frame bottom and by solder resist and the follow-up sectional view be applied to bottom lead frame of electrical feature.
Figure 45 c-45d illustrates and to flood bottom etched lead frame and by solder resist and the follow-up sectional view be applied to bottom lead frame of electrical feature.
Figure 46 a-46e illustrates perspective bottom view and the X ray picture of each embodiment of wafer-level package constructed in accordance, and wherein electrical connection dish is the form of introducing lead-in wire and uses wire-bonded to be connected to chip.
Figure 47 a-47d illustrates the perspective bottom view used according to the wafer-level package having liner and linerless embodiment to manufacture of the present invention, and wherein electrical connection dish is the form introducing lead-in wire.
Figure 48 a-48b illustrates the sectional view of each embodiment according to wafer-level package of the present invention, and wherein die pad is solid or comprises part metals through hole.
Figure 49 a and 49b illustrates according to the vertical view and the sectional view that encapsulate ELP lead frame of the present invention respectively, and the connection electrical ground of the EMI shielding for gained shielding EMI package is shown.
Describe in detail
Describe the present invention referring now to accompanying drawing, wherein identical Reference numeral indicates identical element.Fig. 4-15b and Figure 16-24b illustrates and forms number of leads encapsulates (CSP) suitable partially patterned leadframe package different embodiments near chip level.The automation that method of the present invention improves production line and the q&r of encapsulation therefrom manufactured.This is by performing major part of manufacturing technology steps and partially patterned metal film realizes at the webbed lead frame of side shape.Contrast with the stencil-like lead frame of conventional break-through, lead frame used in this invention is partially patterned in side and is solid and smooth on another side.This structure is improved by machinery and thermodynamics means, and during chip attach, wire-bonded and packaging technology, do not have distortion or shifting ground to carry out.Lower surface can by addition mask or the profile otherwise marking to draw the region of being removed by back etching the most at last.To complete and chip and wire-bonded are attached and after being encapsulated in moulding material hermetically in chip attach and wire bonding technique step, in the region of not sheltered by the selectivity pre-galvanized layer of lower surface, lower surface is partially etched and wears film, isolates and mutually isolated to make lead contact and chip bonding pad.Subsequently, gained through encapsulation encapsulation by singualtion without the need to cutting any additional metal.
More specifically, Fig. 4-15b illustrate for the partially patterned lead frame of wire-bonded chips formation and use it to form the method for ELP type Electronic Packaging.On the other hand, Figure 16-22 illustrates with the formation of the partially patterned lead frame of flip-chip and uses it to form the method for ELPF type Electronic Packaging.The method that the partially patterned lead frame of a kind of the present invention of use forms ELGA type Electronic Packaging also composition graphs 24a and 24b is described.
Fig. 4 is the sectional view of the film being preferably metal (being preferably copper) sheet, and this film is not only formed as lead frame, and is used as stable carrier during the processing step guaranteeing formation lead frame.The thickness of bonding jumper is equal to or greater than about 0.05mm.In another embodiment, this thickness can in about 0.05 scope to 0.5mm.
Formation lead frame is usually directed to cut wears bonding jumper, similar cutting board, and then works to very very thin finger-type lead-in wire.Put in place in order to structure very thin is like this compressed, can vacuum chuck be used.But conventional vacuum chuck is unsuitable for providing suction and lead frame must clamp in periphery usually for device very thin so usually.Any rigging for this object must be reequiped from a kind of lead frame of type and size to another kind.But, this invention removes this repacking step.Because the lower surface of partially patterned lead frame is solid and continuous print, so this lead frame can easily keep putting in place by conventional vacuum chuck between processing period.In addition, the bonding jumper that can adapt to a kind of size of various industrial lead frame can be commonly used in the manufacture of lead frame.The subsequent process steps of chip attach and wire-bonded completes when much smaller stress and strain can be had on lead frame to be formed.The lead frame with much very thin geometry can easily manufacture, because lead-in wire is combined together and be not mutually separated until final step by web shape structure.
Lead frame is formed various pattern can complete in every way.One method can be on metal by imprint patterns/pressure-sizing.Other method can comprise chemistry or electrochemical milling and electric discharge and process (EDM).On the other hand, preferred lithographic patterning, it is the pillar of semiconductor manufacturing.In the present invention, the bonding jumper (100) shown in Fig. 4 before lithographic patterning in front (or on) side and the back of the body (or under) side pre-galvanized.One of front and back or both the material engaging and can weld can be used respectively to carry out pre-galvanized.In one embodiment, front with such as Ni/Pd/Au strike or silver and so on can carry out pre-galvanized by grafting material.In another embodiment, the back side uses such as Sn/Pb, lead-free solder, wicking chemical nickel plating or au base plate coating to carry out pre-galvanized.In another embodiment, the back side uses the material identical with top side to carry out pre-galvanized, and then it can play etchant resist effect in back-patterning period.This etchant resist class electrodeposited coating can be peelled off after a while before final finishing.Pre-galvanized can perform in step after a while (if needing like this).
At next step, the front side (110) of pre-galvanized is corresponded to the region of chip bonding pad (115) and the electric contact (113) around chip-pad area with formation by lithographic patterning.Electric contact (113) can be characterized by the end of lead-in wire, goes between to be connected to chip-pad area (115) by the first area of the middle recessed portion forming web shape structure.At metal film (100), from back, the etched time is after a while removed web shape parts recessed in the middle of these, with make end and chip-pad portions mutually isolated.The region comprising chip bonding pad (115) and surrounding contact (113) is sometimes referred to as chip position (chip site).Multiple chip position can formed around on one on bobbin continuously volume copper sheet, to make the formation easily automation of the lead frame comprising one or more chip position.Fig. 5 illustrates two chip positions, and it will be formed as two corresponding lead frames, and these lead frames will be by a part for two encapsulation formed by it again.
For the pattern shown in the chip position of two shown in Fig. 5 then by etch transfer to film bar (100).As shown in Figure 6, principal character of the present invention is that the thickness only etching partly penetrating metal performs, and this is referred to here as partially patterned.Partially patternedly in the first area of film, perform to be formed the web shape structure (130) that the chip bonding pad of the lead contact of each lead frame (113) (115) is connected.This first area also makes lead frame be interconnected at the street portions (street portion) (136) of film.
As shown in Fig. 6 a-c, matrix or these lead frames (such as, 16x 16) can be formed in frame/window film (138).Fig. 6 b with 6c illustrates that first area comprises the web shape structure (139) that the chip bonding pad of each lead frame is connected with lead contact.First area also makes multiple lead frame be interconnected at the street portions of film (136).
In one embodiment, partially patternedly 90% can be changed to from 25% of film thickness.But, in fact partially patterned can be the film thickness of any percentage, and partially-etched amount can by considering that the various factors affecting manufacturability parameters is determined, these factors comprise flexibility, rigidity and hot thickness (or thermal conductivity).The lateral dimension of lead contact region (113) and chip-pad area (115) can determine based on the degree of the miniaturization needed for given die size and wire-bonded or other connecting media, connects in the inter-stage between the encapsulation that wire-bonded or other connecting media can be used in given encapsulation or next stage encapsulates or level.Especially it should be noted that the web shape structure to the very thin parts of lead frame and the manufacturability factor of dimensional stability rely on finger-type to go between now becomes less important.
As shown in Figure 7, chip (140) then uses any convenient means of such as epoxy resin (150) and so on to be attached to chip-pad area.Chip and illustrate that junction between attached chip bonding pad is according to the present invention includes epoxy resin or solder.Epoxy resin (150) can be filled with conductive particle to strengthen the cooling of chip.As replacement, the soldering paste (150 ') of epoxy resin (150) is replaced also to can be used to provide the firmer joint between chip and chip bonding pad and the more effective cooling path to surrounding environment.Epoxy resin is cured and as shown in Figure 8, after chip attach, line (160) uses known wire bond technology to join terminal (145) and corresponding lead contact (113) to, as shown in Figure 8.Because lead frame formed according to the present invention has firm fixing and such as compress solid, continuous print dorsal part in the plane, so the web shape structure of lead-in wire does not swing or spring during wire-bonded by vacuum chuck (not shown).This causes outstanding joint, and this improves the reliability of final products.Although dorsal part is solid and continuous print, it still can have the designator will where carried out about back etching.Such as, dorsal part can have other designator of the part on the surface that can be maybe film of breaking, or dorsal part can be sheltered to draw the profile by the presumptive area etched by back with pre-galvanized material (120).Such as, pre-galvanized material (120) can be masked to indicate the appropriate section of lead frame will to be retained at etching after a while and region under region (130) and (136) will be removed under region (113).
In fig .9, making after chip is connected with corresponding contacts, then all component on the front side of metal film is such as hermetically sealed in moulding material by resin.Encapsulant (170) film with comprise lead frame and they be associated line (160), chip (140) and contact (113) and web shape structure (130) and street portions (136) all exposed surfaces on formed.When gained molded package is picked up, clean dorsal part now can for processing further.Usually molded burr (mold flashing) problem to the overlay area on encapsulation downside run into uses method disclosed in this to eliminate.Clean dorsal part can in advance with being convenient to the material plating of following process or etching.
As shown in Figure 10, lead contact (113) and chip bonding pad (115) can penetrate encapsulation dorsal part with the easily mutually isolated island forming them by the web shape structure (135) of etching first area now.Now, street portions (136) is also etched by back.Use and such as the pre-galvanized layer (120) of material of printer's ink or organic material and so on can be used as mask or etchant resist to form required bottom part (123,125).In other embodiments, organic material can be used to replace metal or weldable material as etching mask.Organic material can be printed in any convenient step or be coated on lead frame before the etching of back.
Back etching continues until arrive moulding material.Engraving method for back etching metal can different from for front side.According to the partially-etched degree performed from front side, the etching period for dorsal part can different from for front side.Thus, the initial formation of partial etch lead frame can be customization to be applicable to the automation of final encapsulation, quality, reliability and functional manufacture demand.The pre-galvanized layer (120) playing the bottom of Chemical resistance membrane interaction can be peelled off with exposing metal bar (100).
Be convenient to be installed to printed circuit board (PCB) for protective material, weldable material or other such material of such as Electroless Plating Ni/leaching Au, leaching Sn and so on can be electroplated onto bonding jumper (100).Think applicable specific environment time, any pre-galvanized layer can retain or peel off.
As final step, the encapsulant (170) on the street portions (136) between lead frame is encapsulated separately with two of being formed as shown in figure 11 by singualtion.This presses various ways and realizes, and comprises sawing sheet, water spray cutting, laser cutting or its combination or is specially adapted to cut other technology of plastics.In other words, layering or other problem that metal and so there is no is associated with the combination of cutting plastics and metal is no longer cut.The routine that this and the bridge joint metal wherein between street must be cut while encapsulating by singualtion encapsulates makes comparisons.In multiple times, when cutting both metal and plastic at the same time, the part in metal chip can be short circuit line and contact, thus causes unexpected on saw blade and unpredictable loss.As shown in Figure 6 a, the method also can be applicable to by a large amount of encapsulation of leadframe matrix manufacture.
The sectional top view of overlooking through the encapsulant of singualtion ELP is shown in Figure 12 a.Figure 12 b shows the enlarged drawing in the corner between one of chip and contact of encapsulation, described corner comprise the parts of original metal bar (100), pre-galvanized with formed can the end face of knitting layer (113) and pre-galvanized can the bottom surface of layer (123) to be formed.In Figure 12 b, " antelabium " illustrates on the corner of contact and chip.Contact (113) and chip (140) show for mutually isolated on their island, but are interconnected by means of only the line (160) of wire-bonded.
Welded pre-galvanized surface (120) on the downside of encapsulation, as unstripped, may be used for some purposes now.The first, the direct external path to the back (125) of chip bonding pad (140) provides additional hot path for cooling.The second, the contact (123) in the area coverage of near chip level encapsulation (CSP) makes the encapsulation may installing tight spacing in next stage encapsulation, and therefore promotes the performance of the same area.
Another aspect of the present invention provides a kind of method reducing the possibility of layering between moulding material and its attached surface.This has been come with the flange or " antelabium " that form Reference numeral (105) indication in such as Figure 12 b by the edge around half-etching chip bonding pad and contact region.Also may form the erose hole (107) shown in Figure 12 to strengthen the interlocking mechanism with the surface of molding material contacts.The enlarged drawing in other hole various also illustrates at Figure 13 a-13f, and the formation of these surface enhanced can be readily incorporated from front side partially-etched.This is for dispensable from back side etch, because moulding material only encapsulates from the surface that formed, front part ground.
Method of the present invention is summarized as with lead frame from front part is etched into (200) bonding jumper and to use the back-patterning etching of mode (250) the same bonding jumper forming required chip bonding pad and surrounding contact to terminate by Figure 14.The intermediate steps of chip attach (210), epoxy resin cure (220), wire-bonded (230) and encapsulation (240) all mechanically with on stable lead frame on thermodynamics realizes, because lead-in wire is still connected by the first area of the partially-etched web shape in metal film or the structural middle recessed portion of web shape.Also importantly should be noted that; only after all component of encapsulation has been protected in encapsulant, the first area of middle recessed portion is removed by back pattern etching (250) and peripheral contacts and chip bonding pad is separated from each other for suitable isolation.Before final step, can perform and peel off pre-galvanized layer (120) and coating weldable material.Therefore, do not need to cut any metal during singualtion (260) becomes single near chip level to encapsulate.
Method of the present invention can be used for forming various encapsulation, such as the array type lead frame of Electronic Packaging.It is adjacent that the vertical view of array style package (400) is regarded as encapsulating (300) with the standard peripheral type shown in Figure 15 a in Figure 15 b.Although Reference numeral (305) refers to the chip terminal of peripheral arrangement, Reference numeral (405) refers to the terminal of array type arrangement that can be coaxial or interconnected.The disclosed partially patterned invention as indicated by Reference numeral (310) and (410) is used to form these two kinds encapsulation.In array type ELP, lead (440) and outer lead (445) are illustrated.These two kinds of encapsulation are encapsulated in moulding material (320) or (420).Back-patterningly be etched with spacing contact and chip is indicated by (330) and (430).Reference numeral (450) describes ground loop parts, and it is etched to the level identical with mould.Reference numeral (460) refers to the array type I/O configuration on the vertical view of ELP.
The second embodiment shown in accompanying drawing 16-24b discloses a kind of method of VFQFP-N type lead frame of forming section patterning, and the method is particularly useful for the FC Electronic Packaging of large-scale production.Being made the lead frame holding flip-chip will hereinafter referred to as FCL to differentiate it and conventional lead frame.This is because different from conventional lead frame, FCL is firmer and be more suitable for automatic production line, as described below.
FCL is also web shape structure, and the break-through general with routine, stencil-type lead frame are contrary.The front side of web shape FCL has the recessed portion comprising partially patterned lead-in wire, and dorsal part is solid and smooth.This provides mechanical stiffness to perform not have distortion or shifting ground during manufacturing process.After the chip attach completing encapsulation and hermetic seal, dorsal part is etched with makes lead contact mutually isolated.Remove pre-galvanized layer or use other weldable material again to electroplate and complete by chemical plating or immersion technique.Subsequently, gained through encapsulation encapsulation by singualtion without the need to cutting any additional metal.Thus, it is evident that the FCL with more very thin geometry such as with VFQFP-N encapsulation can easily manufacture, because lead-in wire to be held togather by web shape or web shape structure and be mutually not exclusively separated until final singulation step.
The similar partially patterned lead frame disclosing the first embodiment, the FCL of the second embodiment is also formed by sheet metal, preferably copper film as shown in Figure 4, and wherein front and back is by pre-galvanized, or plating as discussed previously can be put off to step after a while.(note, the processing step due to these two embodiments is similar, so Reference numeral remains identical as required, except indicating those marks of the second embodiment with prime number.Identical Reference numeral (100) has been used for the metal film of these two embodiments for holding consistency.Then, on front side of pre-galvanized (110 ') by lithographic patterning to form chip housing region (115 '), around the lead portion (113 ') of chip housing region and other zone line (117 ').In the subsequent process steps of following discloses, an end of lead-in wire will be connected to the terminal of PC, and another end will be connected to next stage encapsulation.Similar with the chip position with wire-bonded chips, the region comprising chip housing region and surrounding lead-in wire is sometimes referred to as chip position.The multiple lead frames comprising multiple chip position can formed around rolling up continuously on copper sheet to one of bobbin, easily to make the formation automation of the lead frame comprising one or more chip position.Figure 16 illustrates two chip positions, and it will be formed as two corresponding lead frames, and these lead frames will be by a part for two encapsulation formed by it again.
The pattern of the chip position of two shown in Figure 16 is then by transferring to metal film (100) via the partially patterned of etching.Partially patterned shown in Figure 17 can the most nearly 1/2nd, 1/4th, or any ratio of the thickness of bonding jumper can be up to, and partially-etched amount can by considering that the various factors affecting manufacturability parameters is determined, execution factor comprises flexibility, rigidity and hot thickness (or thermal conductivity).The lateral dimension of lead contact region (113 ') and chip area (115 ') can be determined based on the degree of miniaturization needed for given chip position, the lead-in wire comprising die size and connect in the inter-stage that is used in given encapsulation or between the encapsulation of next stage encapsulation or level.Especially it should be noted that and rely on now the web shape structure of finger-type lead-in wire to become less important to the very thin parts of lead frame and the manufacturability factor of dimensional stability.
Flip-chip (FC) (130 '), then by upside-down mounting, rests on an end of lead-in wire as shown in figure 18 to make the terminal (135 ') on front side of chip.In step after a while, the electric contact of next stage encapsulation that the end opposite of lead-in wire will be formed for being connected to such as card or plate and so on.But, first, as shown in figure 18 be assembled in chip in web shape lead frame structure by the chip as put into practice in the art in conjunction with stove transmission.Soldered ball remelting limits by BLM to make remelting, thus forms welding column.Because lead frame formed according to the present invention has robust sealed and compress solid, continuous print dorsal part in the plane, thus the web shape structure of lead-in wire not at chip in conjunction with swinging around stove or spring, thus obtain outstanding chip and combine.As a result, disclosed method improves the reliability of final products, i.e. the reliability of VFQFP-N type encapsulation.
After chip joining, then chip is such as hermetically sealed in moulding material by resin together with the partially patterned lead-in wire on the front side at original metal film, as shown in figure 19.Encapsulant (140 ') is formed in around all exposed surfaces, all exposed surfaces comprise lead-in wire (113 '), soldered ball (135 ') around, below chip, along the exposed surface of the vertical wall of recessed chip housing region (115 '), and the exposed surface of the vertical wall of recessed region (117 '), except not the etching of firm compression bonding jumper in the plane (100), solid and smooth dorsal part.When gained molded package is picked up, clean dorsal part now can for processing further.Usually the molded Burr Problem to the overlay area on the downside of encapsulation run into also is eliminated in this embodiment.
Lead-in wire (113 ') now can easily by alignedly patterning is mutually isolated through the dorsal part encapsulated with pattern etch from front part when technique starts.Back etching continues until arrive moulding material.This is shown in Figure 20, wherein the web shape part of lead frame, and namely region (111 ') and (119 ') are removed chip area (115 ') is disconnected mutually, and go between (113 ') disconnects mutually.For back-patterning metal engraving method can or can not be used for from front part etching method identical.In addition, according to the partially-etched degree performed from front side, can different from for front side from time of back side etch.Thus, the initial formation of partial etch lead frame can be customization to be applicable to the automation of final encapsulation, quality, reliability and functional manufacture demand.The pre-galvanized layer (120) playing the bottom of Chemical resistance membrane interaction can be peelled off with exposing metal bar (100).Be convenient to be installed to printed circuit board (PCB) for protective material, weldable material or other material of such as Electroless Plating Ni/leaching Au, leaching Sn and so on can be electroplated onto bonding jumper (100).
As final step, in order to the present invention is described, the encapsulation with Figure 20 of two packaged chip positions is then changed into single near chip level encapsulation (CSP) by monolithic, and they are mostly is the encapsulation of VFQFP-N type, as shown in figure 21.The vertical view of singualtion patterned lead frame encapsulation is shown in Figure 22 a, and wherein go between (113 ') is illustrated as soldered ball (135 ') that is mutually isolated and that be connected on the downside of chip (130 ').Figure 22 b illustrates the enlarged drawing in the corner between one of chip and the lead-in wire being connected to the external contact (145 ') that can be arranged on card or plate (150 ') of encapsulation.Pre-galvanized surface (120 ') has been prepared into the contact be attached to as same next stage shown in the drawings.When being applicable to as thought at this moment or catering to the need, pre-galvanized or mask can be kept or remove.Pre-galvanized or mask also can be removed when in process other, thus are suitable for various environment.In addition, the downside (114 ') of lead-in wire (113 ') is exposed to surrounding environment, thus provides the cooling of enhancing.In some cases, coating can be applied to downside (114) to reduce the possibility of potential short circuit between plate installation period, especially for fine pitch applications.
As previously disclosed constructed can be used to, by the erose hole of composition graphs 13a-13f on the recessed region (115 ') of web shape lead frame and the vertical wall of (117 '), prevents encapsulant from the skin lamination of FCL.It is partially-etched that the formation of these surface enhanced can be readily incorporated from front side.This is for will being unnecessary from back side etch, because moulding material only encapsulates the surface from the fractal one-tenth of front side portion.
The method of the present embodiment is summarized as with lead frame from front part is etched into (200 ') bonding jumper and to use the same bonding jumper of mode back-patterning (240 ') forming required chip housing region and surrounding lead-in wire to terminate by Figure 23.The intermediate steps that FC places (210 '), FC chip combines (220 ') and encapsulation (230 ') is all mechanically upper with stable FCL on thermodynamics to be realized, because lead-in wire still passes through the partially-etched web shape anatomical connectivity in metal film.Also importantly should be noted that; only after all component of encapsulation has been protected in encapsulant, the web shape part of lead-in wire is optionally removed by back-patterning etching (240 ') and lead-in wire is separated from each other for suitable isolation.Therefore, do not need to cut any metal during singualtion (250 ') becomes single near chip level to encapsulate.
Be similar to the disclosed method using the peripheral group of solder projection in this article, method of the present invention can be used to form various encapsulation, the multiple partially patterned lead frame of such as array type, wherein the area array of solder projection can be attached to the lead frame of flip-chip by chip simultaneously.In addition, the array of partially patterned lead frame itself can be formed simultaneously, and then FC combination simultaneously, array is encapsulated by the VFQFP-N type that monolithic changes into multiple separation subsequently.In addition, then each gained CSP can be provided with and be attached to the solder projection of next stage encapsulation for array type under encapsulation, pad or other electricity connects to form the etched lead frame encapsulation with bank grid array as shown in Figure 24 a and 24b or the encapsulation of ELGA type.At Figure 24 a, illustrate that chip bonding pad (135 ') is at the upper viewgraph of cross-section formed of lead-in wire (145 ').After back-patterning, lead-in wire (145 ') mutually electric isolution encapsulates to be attached to next stage.The bottom surface (145 ') exposed uses the weldable material of any number to carry out burr finishing by wicking dipping or chemical nickel plating plating.There is the bottom surface (111 ') of the ELGA encapsulation of the array pattern (145 ') for being electrically connected shown in Figure 24 b.
Solder projection can be the form of the metal column projection of such as copper post projection and so on, and wherein each projection is high by about 75 microns, and has solder (or unleaded) cap and cause the Cu shaft of about 100 microns of total heights to form.When using copper post projection, " solder projection " can be " solder caps ".The use of copper post gives the gap being greater than 50 microns between chip surface UBM and plate contact, and plastic encapsulating material can be made freely to flow and cover the crack below flip-chip.
Because formed ELP, ELPF or ELGA encapsulation in any one partial etching method during each manufacturing step, provide robustness, Electronic Packaging in other forms be also possible.A kind of such form comprises the wire-bonded that leadframe package of the present invention encapsulates to next stage.Because the ultrasonic joining technique of the fragility of lead-in wire itself can not be used for conventional lead frame, unless they are attached to solid substrate to provide stability and intensity.On the contrary, partial etch lead frame relies on their web shape structure to be stable.Not etching of partially patterned lead frame provides solid engaging zones or post with pre-galvanized bottom surface (120 '), effectively to be closed by the aluminum steel wedge joint of ultrasonic energy on the block or bar of ELP or ELPF.Therefore, according to a further aspect in the invention, aluminum steel (121) ultrasonic bottom surface being attached to a piece or bar partial etch lead frame as shown in Figure 25 a.Linear diameter scope about 0.001 inch to 0.020 inch between, and a rear diameter representing ribbons (ribbon) and non-thread.Then packed, the back-patterning and singualtion of bar is to form each approximate CSP.Ultrasonic joint is desirable, because it avoids being exposed to the ball bonding junction temperature being encapsulated experience by solder ball grid array type, therefore has the reliability of improvement.As shown in figure 25b, also can apply copper cash ball bonding to engage.To understand, the CSP shown in Figure 25 a and 25b can be any one in ELP and ELPF.
The present invention facilitates the multiple attendant advantages in Electronic Packaging manufacturing process.Such as, after the etching of back and before singualtion, package blocks will be inherently extension test and gets ready and encapsulate and be still arranged in block.This with encapsulation process is become compared with unit to provide remarkable advantage.The reliability of their retrofit testings of extension test when encapsulation is arranged in block.
The present invention can also make manufacturer's production have the encapsulation of two or three line interlacings lead-in wires of the I/O capacity of given encapsulation of can doubling.The smooth continuous bottom surface of lead frame makes general mounting equipment use, and it does not need each application repacking, and it is completely flexibly to automation.Such as, the process between 2x2 to 12x12 package blocks is without any need for change mechanically.In addition, the present invention easily promotes the structure (being such as, 2 mils between the bottom of the surperficial molding of pin) each pin to the encapsulation in " gap ".When chip package is connected to the next stage encapsulation of such as plate and so on, this gap provides additional advantage.
Figure 26 a and 26b illustrates the embodiment of an aspect of of the present present invention, and wherein two chip (505,510) tube cores are stacked on the chip bonding pad (515) of lead frame (500).Lower chip (505) (being namely attached to the chip of chip bonding pad housing region (515)) is electrically connected to interior group of (520) electrical lead around chip-pad area (515).The outermost group (525) that upper chip (510) (being namely attached to the chip at the top of lower chip (505)) is electrically connected to around chip bonding pad area (515) goes between.Chip encapsulant (530) encapsulation, its protect IC and line are with antisitic defect.Although the chip (505,510) in Figure 26 a and 26b is wire-bonded chips, consistent with the present invention, one or more in chip can also be flip-chips.Lower tube core closed assembly chip (505) is greater than chip (510) dimensionally.Although lower chip and upper chip are not electrically connected in the example shown mutually, in certain embodiments, these chips can such as by being electrically connected from a chip to another line.The step forming electrical connection can be realized by the end of the connecting terminals of various chip being received the electrical lead extended from lead frame.
Figure 27 a-27c illustrates embodiments of the invention, and wherein chip-pad area (550) is recessed to allow the reduction of tube core closed assembly and the packaging height improved.In Figure 27 a-27c, three chip (555,560,565) tube core closed assemblies are to form chip package.As can from Figure 27 a finding, the inside of chip-pad area (550) be removed and have made to only have foursquare outer shroud.Chip (555) is placed into and is attached to this chip-pad area.Although illustrated three tube core closed assembly chips (555,560,565) in Figure 27 a-27c, consistent with the present invention, the tube core closed assembly chip of any number can be had.In Figure 27 a, the inside of recessed chip-pad area (550) is illustrated as the end face of lead frame.That is, only the outer square loop (575) of chip-pad area has been deposited over the top of lead frame, and the whole inside (550) of chip-pad area is not deposited or removes from lead frame.In an alternate embodiment of the invention, a part for the thin-material layers inside or chip bonding pad interior zone that are deposited over chip-pad area is removed.In these embodiments, the inside of chip-pad area will higher than leadframe pad, but still lower than the outside of chip-pad area, thus provides recessed chip-pad area for the attached of chip.
Although in Figure 27 a-27c, maximum chip (555) is positioned at the bottom of die stacks, and minimum chip (565) is positioned at top, chip can be placed to make maximum minimum in bottom at top.The chip (565) of most top layer is illustrated as being connected to intermediate chip (560), and is connected to the electrical lead (580,585) on lead frame (570).Intermediate chip (560) is illustrated as the chip (565) being connected to most top layer, and is connected to the electrical lead on lead frame.The encapsulant (590) covering tube core closed assembly chip (555,560,565) prevents the line of chip package damaged between operation or installation period.Various chip uses the adhesive of such as conduction or non-conductive epoxy resin and so on or uses insulating material to be attached to lead frame (550) or mutually attached.
Figure 28 a and 28b is the stereogram of the lead frame of specific some aspects of the present invention.Figure 28 a illustrates the lead frame (600) with four chip-pad area (605,610,615,620) before chip is attached to lead frame.Figure 28 b illustrates the same lead frame (600) after chip (625,630,635,640) has been attached to chip-pad area (605,610,615,620) and has been electrically connected to lead frame.
Lead frame (600) shows for having three chip-pad area (610,615,620) for wire-bonded chips and a chip-pad area (605) for flip-chip by Figure 28 a.Recessed for two (615,620) not recessed and remaining chip-pad area (610) in three chip-pad area of wire-bonded chips.These chip-pad area (610,615,620) comprise the alterations (645) of the ' locked ' zone form that shape is " T " on the neighboring of chip-pad area.These Lock Parts are that encapsulant (650) adheres to and provides additional surface area, and provide a kind of and do not make for keeping encapsulant the method that encapsulant is displaced sideways.
In Figure 28 b, each supporting of recessed chip-pad area (615,620) is not had to be connected to the one single chip (635,640) of lead frame via electrical lead.Chip-pad area (605) for flip-chip (625) is formed by electrical lead bed, and flip-chip (625) is placed on the top of these lead-in wires to form electrical connection.As compared to wire-bonded chips (630,635,640), flip-chip (625) thus save space on lead frame (600).Although for clarity sake, only one single chip is illustrated as two of being attached on lead frame does not have recessed chip-pad area (615,620), but in other embodiments of the invention, one or more chip can be had to be placed on the top of these wire-bonded chips or flip-chip.
In Figure 28 b, the recessed chip-pad area (610) on lead frame supports the wire-bonded chips (being generically and collectively referred to as 630) of multiple tube core closed assembly.These chips use the adhesive of such as conduction or non-conductive adhesive (such as epoxy resin) and so on or use insulating barrier to be attached to chip-pad area (610).The periphery of recessed chip-pad area (610) comprises the alterations (645) of shape for the ' locked ' zone form of " T ".
Lead frame (600) in Figure 28 a and 28b also has the electrical lead (usual 655) be positioned between flip-chip welding disking area (605) and recessed chip-pad area (610), and it also can be used for other element except computer chip.Such as, these electrical leads can be the elements of such as semiconductor element, passive block, resistor and capacitor and so on, or other is used for the non-chip assembly (generally showing for (660)) of supplementary chip package chips function.In Figure 28 b, capacitor or resistor are attached to these electrical leads.
Chip can one by one be stacked in chip-pad area and to be then electrically connected to lead frame by tube core closed assembly before electrical connection at next chip by tube core.By tube core closed assembly and then alternatively, all chips can be electrically connected to lead frame by the chip of whole tube core closed assembly group.In another embodiment, chip can with chip-pad area tube core closed assembly discretely, and then the chip of whole tube core closed assembly group can be attached and be electrically connected to lead frame.Tube core closed assembly and electrical connection can be formed by any order, although it is easily that chip and passive block are attached to lead frame, then carry out wire-bonded (or forming other method of electrical connection).
Figure 29 a-29c illustrates each embodiment of the various types of alterations that can be applicable to chip-pad area.In Figure 29 a, alterations (705) adopts the form of "T"-shaped recess on the outer ledge of chip-pad area (720).In Figure 29 b, alterations (710) is positioned at the hole of neighboring along chip-pad area (725) or the form of perforation.Figure 29 c illustrates the alterations (715) of the form of the recess of the neighboring along chip-pad area (730).These alterations for encapsulation chip package the intensity of increase and the stability of improvement are provided.
Although the alterations in Figure 29 a-29c or Lock Part are positioned at the periphery of respective chip welding disking area (720,725,730), alterations also can be placed in the other parts of chip-pad area.Such as, alterations can in the inside of chip-pad area, and the inside of this chip-pad area will not covered by chip and therefore can fill with encapsulant.
In Figure 29 a-29c, alterations has been illustrated as being positioned in chip-pad area.In additional embodiment of the present invention, those such as shown in Figure 30 a-32f, alterations can be positioned on the electrical lead that on lead frame and chip can be connected electrically.Alterations also can be placed on chip-pad area and lead-in wire simultaneously.
Figure 30 a-31b illustrates top view and the end view of some embodiments of the electrical lead with alterations.Figure 30 a-30d illustrates the cross section of the part in various types of lead-in wire (735,740,745,750) and these lead-in wires.What Figure 30 b illustrated that alterations can have an inner surface (755) being arranged in lead-in wire (740) can grafting material.Figure 31 a and 31b illustrates that the improvement that the surface (770,775) of lead-in wire (760,765) can be roughened for encapsulant retains.
Figure 32 a-32f illustrates the stereogram of each embodiment of Figure 30 a-31b, and these stereograms illustrate some embodiments with the electrical lead of alterations.Figure 32 a illustrates the lead frame (800) with chip-pad area (805).The encircled portion (810) of accompanying drawing illustrates the electrical lead (815) with alterations.Figure 32 b-32f illustrates the lead-in wire of these types.Figure 32 b-32d illustrates the embodiment to those the roughly similar lead-in wires (820,825,830) shown in Figure 30 a, 30c and 30d.Figure 32 e illustrates and the roughly similar lead-in wire (835) shown in Figure 30 b.Figure 32 f illustrates the lead-in wire (840) of the surface roughening had along the peripheral horizontal recess form of lead-in wire, thus gives the outward appearance of lead-in wire step.The technique of chemistry or other type can be used to obtain the surface roughening shown in Figure 32 f.This surface roughening can with lead-in wire with chip and pad alterations Combination application.
Figure 33 a-33b illustrates the sectional view of the one side of further embodiment of the present invention, and wherein wire clamp (925) is used to replace wire-bonded to power to wafer-level package (935) and thus to improve its power capability.Figure 33 a illustrates the embodiment using wire-bonded chips (905 and 910), and Figure 33 b illustrates the embodiment for flip-chip (showing for one single chip 907).The electric power that wire-bonded provides significantly a large amount of compared by wire clamp, and result makes gained chip package (935) can have the reliability of improvement.Wire clamp also helps from chip cooling.When using wire clamp, the chip of most top layer will comprise for by the lead-in wire of electric signal transmission to printed circuit board (PCB).
In Figure 33 a, wire-bonded chips (905 and 910) is placed on chip-pad area (900) and goes up and be electrically connected to lead-in wire (915) via line (920).Multiple line (920) is used to chip (910) to be connected to multirow electrical lead (915), although the number of electrical connection and type will depend on specific embodiment.In Figure 33 b, flip-chip (907) is placed on from the electrical lead (such as 915) of lead frame protrusion.For ease of illustrating, only single flip-chip (907) is shown in Figure 33 b, although in fact can have the flip-chip of formation wafer-level package (935) and any combination of wire-bonded chips.
The end face of the highest chip (907 and 910) is electrically connected to the one or more electrical leads (917) on lead frame (900) by wire clamp (925).After chip is attached to lead frame, wire clamp (925) joins the top of chip to.Any means easily can be used to join wire clamp to chip.In the example shown in Figure 33 a-33b, conducting resinl or solder (930) are used to wire clamp (925) to be attached to chip (907 and 910).Wire clamp (925) can by the conductive materials manufacture of such as metal or metal alloy and so on.The example of suitable conductive materials comprises copper and silver.According to specific embodiment, each wire clamp can be attached to certain chip, or whole bus or plate can use combined method to be attached to multiple chip.In a rear embodiment, the action incision bus of singualtion or plate are effectively to obtain each chip package.
According to the present invention, closed assembly chip is covered by encapsulant subsequently and after singualtion, obtains wafer-level package (935).
The pipe core welding disc exposed is commonly used to provide the electric isolution between wafer-level package and printed circuit board (PCB) (PCB).But in some examples, the pipe core welding disc of exposure or chip-pad area are unfavorable for the suitable function of chip or wafer-level package.Such as, some PCB designs have the active circuit below wafer-level package, and if encapsulation there is exposure chip bonding pad then these circuit can break down.Although the use that QFN (quad flat no-lead (QFN) encapsulation) encapsulates in such cases can provide possible solution, be designed so that, with the lead frame of QFN encapsulation, there is multiple assembling difficult point be associated.Such as, the QFN be difficult to or prior art can not be used to produce for landless lead frame encapsulates, and namely these methods are that (a) uses band, wherein lead frame normally map (mode array technique) form, or (b) need not be with, wherein lead frame is matrix form.
In order to overcome these difficulties, user (a) has and can be embedded into or (b) has upset at pipe core welding disc in molded period to make pad from the lead frame of bottom half-etching.But, for there being band map lead frame, there is the problem performing wire-bonded, because band will prevent heater block (for preheating lead frame before joining semiconductor leads to lead frame) and contact pads.After wire-bonded, perform adhesive tape, to the rate of manufacturing a finished product, there is negative effect.For matrix lead frame, heater block can be designed to have pedestal with supports chip welding disking area during wire-bonded.But this leadframe design has low capacity, and therefore will affect specific yield per hour and increase production cost.
In these cases, landless ELP can provide the possibility of the fault of the functional of improvement and reduction.Landless ELP can maintain high density designs and provide the packaging technology of more robust.Landless ELP embodiment has the structure roughly similar with ELP chip bonding pad embodiment, but without the need to protecting the etching of bottom.Therefore, landless ELP embodiment does not need acutely to change production line.
Landless lead frame have half-etching tube core housing region and without the need to bottom etching mask or electrodeposited coating.Tube core housing region compares other lead frame can hold larger die size, and can provide the device needing tube core completely isolated.Because tube core housing region is recessed, so gained wafer-level package can have low-down profile, thus minimize its install needed for height.Die-attach material (or adhesive) therefore will be nonconducting to prevent short circuit, and will be that same color is to provide consistent outward appearance with mold compound usually.In addition, die-attach material or adhesive should be stable at back etching, so that prevent the damage to wafer-level package.Die-attach material can be any material known in the art, such as the band of curable epoxy or such as polyimide binder band and so on.
Figure 34 a-34f illustrates the embodiment of partially patterned lead frame, and wherein chip-pad area or chip housing region do not exist and chip is directly attached to forming lead frame the bottom of etching-film.Attached die, encapsulation and back-patterning after, the bottom of chip is exposed in wafer-level package.As shown in Figure 34 a, partially-etched film does not have protruding chip-pad area with holding semiconductor chip.
Figure 34 a illustrates the metal film (1000) be partially etched in front side.This film (1000) can use and the material processed after a while being convenient to such as wire-bonded and so on is come pre-galvanized one or both sides.Such as, pre-galvanized can be carried out by mating substance with the lead-in wire of such as NiPdAu or the silver (Ag) such as soaking Ag and so on and so in the top of film, and the bottom of film can be exposed and use identical or another lead-in wire can carry out pre-galvanized by mating substance.In other embodiments, organic material can be used as etching mask.
Film (1000) is etched with preparation integrated circuit (IC) chip by electrical lead part (1005) attached with it after a while in its front.Film has the street regions (1035) of each several part of isolation lead frame, and will by these street regions (1035) singualtion to obtain each wafer-level package through the lead frame of encapsulation.Chip mounting area (1010) is etched to the front of film.These chip mounting area (1010) are in height low than lead-in wire.In other words, film (1000) is etched minimum in the region (1005) of lead-in wire, and is etched at most by the other parts at lead frame.
To have prepared and suitably after etching at film (1000), semiconductor or integrated circuit (IC) chip (1020) will by attached die to films, as shown in Figure 34 b.Any convenient material of chip (1020) available die-attach material or adhesive (1015) and so on is attached, these materials by normally nonconducting to avoid the propagation of the signal of telecommunication.
In one embodiment, the available nonconducting epoxy resin of chip (1020) (1015) is attached.This adhesive is applicable as fluid or viscous liquid, and then it will harden or form internal crosslinking to form firm, durable joint.Adhesive or die-attach material (1015) will be visible and be exposed to the bottom of gained wafer-level package (1040), and therefore have long-term thermodynamics and mechanical stability by needing.In other embodiments, adhesive can be the form of the band of such as polyimide binder band and so on.Band is made up of the base band film of the adhesion substance being coated with such as thermoplastic polymer and so on both sides usually, and band can be viscosity or tack-free.In a further embodiment, adhesive is solid plastics material, and it solidifies in position or to solidify to provide between chip and lead frame firm attached.Various types of adhesive, band and other die-attach material are known and commercially available.
In one embodiment, adhesive (1015) and around encapsulant (1030) be all black, therefore whole wafer-level package (1040) is presented consistent painted.In other embodiments, adhesive and encapsulant are different colours.In a further embodiment, manufacturer such as can wish the color for adhesive and encapsulant selection particular complementary or contrast, thus provides special trade dress.
The thickness of adhesive (1015) is not crucial, although it by have to enough thick with there is mechanical stability and tolerate lead frame back etching.Adhesive (1015) will cover the whole bottom surface of integrated circuit (IC) chip (1020) usually to avoid during back etching subsequently or back-patterning process the chemistry of chip or mechanical damage.
Once chip (1020) by attached die to film (1000), chip just such as uses lead-in wire (1025) to be connected to electrical lead (1005), as shown in Figure 34 c.Chip (1020) and lead-in wire (1025) use encapsulant (1030) hermetic seal (Figure 34 d).As discussed above, encapsulant (1030) can be any material known in the art.The unrestricted list of the usual encapsulant used in industry comprises silica particles filling epoxy resin and liquid epoxies.Encapsulant is coated to the various elements being arranged on or being attached to lead frame usually used as liquid or viscous liquid.Solidification encapsulant obtains hard, curable coating, and the lower panel element in its protective core chip size package is not damaged.
After encapsulant (1030) has solidified, lead frame (1000) has then been etched with isolation electrical lead (1005), as shown in Figure 34 e by back.The each several part (i.e. original chip installation region) below chip (1020) of lead frame (1000) at back etching by basic or complete removal, until die attach adhesives (1015).
Then lead frame is suitable for wafer-level package (1040) of each encapsulation of subsequent applications with acquisition by singualtion along street portions (1035), such as being attached to computer circuit board.Manufacturer can select the mark of printing or silk screen printing mark, lot number or other type in the wafer-level package completed for recognition purpose.
Figure 35 and 36a illustrates vertical view and the cross sectional view of the wafer-level package (1040) prepared via the operation shown in Figure 34 a-34f respectively.Figure 35 person, cure adhesive (1015) shows for the irregular square compared with light colour at the center of wafer-level package (1040).Around solidification adhesion substance (1015) be encapsulant (1030), as shown in comparatively dark colour.Encapsulant (1030) covers and encapsulated integrated circuit chip (1020), wiring (1025), lead-in wire (1005) and other assembly any that can be attached to or be installed on lead frame.
Figure 36 b illustrates another embodiment of the present invention, and wherein multiple integrated circuit (IC) chip (1020,1050) is stacked in the wafer-level package of the landless of finishing (1070) by tube core.Although Figure 26 b and 36b illustrates the various embodiments of the present invention with tube core closed assembly chip, the embodiment in Figure 26 b has chip bonding pad (515) and embodiment in Figure 36 b adopts landless technology.The height that there is not reduction gained wafer-level package of the comparison display chip pad of Figure 26 b and 36b, thus make to prepare the wafer-level package with lower profile.
Embodiment shown in Figure 36 b can use method disclosed by the invention to prepare.In brief, the first, lower chip (1020) is placed on and does not have (not shown in this figure) on the partially patterned lead frame of chip bonding pad, and this chip (1020) uses the die-attach material of such as adhesive or epoxy resin and so on (1015) to be attached to lead frame.Upper chip (1050) then uses the adhesion substance of such as conduction or nonconducting epoxy resin or insulating material and so on be placed on the top of lower chip (1020) and be attached to this lower chip.Chip (1020,1050) uses wire-bonded to be electrically connected to lead frame.
Electrical connection (1025) sequentially can be carried out after each chip is placed on lead frame.That is, the first chip (1020) can be placed on lead frame and to be electrically connected to this lead frame, and then the second chip (1050) can be placed on the first chip (1020) upper and be electrically connected to lead frame.In other embodiments, then chip (1020,1050) first in position by tube core closed assembly, and carries out being electrically connected (1025).The various combinations of these closed assemblies and electrical connecting step are possible and within the scope of the present invention.
At chip (1020,1050) by tube core closed assembly and after being electrically connected (1025) to lead frame, then lead frame uses encapsulant (1030) to encapsulate for good and all chip and electric wire to be arranged on lead frame.Back-patterning, etching and finishing are carried out as required to isolate electrical lead (1005) in the back of lead frame then.During this back-patterning technique, the part of lead frame below tube core closed assembly chip by complete removal, and only goes between (1005) from the wafer-level package through finishing " protrusion ".Generally speaking, the original lead frame retained after back-patterning only have part to be electrical lead (1005).Finally, wafer-level package in street regions by singualtion to obtain each wafer-level package (1070) for subsequent applications.
According to a further aspect in the invention, the end face of lead frame and bottom surface can be partially patterned or partially-etched before attached die.As shown in Figure 37 a, lead frame (1100) can be etched before the encapsulation of assembling chip level on both sides.Etching on the both sides of lead frame can be the consistent degree of depth.Alternatively, etching can be uneven, and side is compared opposite side and can be patterned darker.Such as, top (such as, region 1160) compare bottom (such as, region 1165) can be patterned darker.
Bilateral etching allows the thickness each several part of the film of final removed lead frame with reduction.Thus etching will be carried out faster, and thus increase speed of production and reduce costs.The partially patterned thickness that can reduce the etching part of film reaches any convenient quantity.Such as, the partially patterned segmentation of lead frame can remove the original membrane thickness of 25-90% in the etched region.
Lead frame material can carry out prepatterned with etchant resist material.Etchant resist can be the metal or nonmetal of such as organic etchant resist and so on, and can baking-curing or UV solidification.These prepatterned techniques are well known in the art.
Replace using metal pre-galvanized lead frame, lead frame can with such as epoxy resin ink or tusche and so on can the organic material of printer's ink printing or such as polyimide resin and so on as the etching mask printing before the etching of back.This technology advantageously makes into instinct and reduces and can streamlinedly manufacture.From material angle, printer's ink or organic substance can be used as etching mask and make manufacturer can obtain lead frame from many manufacturers there because not every supplier can on both sides pre-galvanized lead frame.In the example present, lead frame supplier will only etch and electroplate lead wire frame at top, and it is undressed to leave bottom.Such as, the bottom of lead frame can be the naked metal of such as copper and so on.Use printer's ink or organic substance can be carried out sheltering and usually compares use and carried out sheltering for the noble metal of the such as palladium of pre-galvanized lead frame, gold, platinum, rhodium, silver or ruthenium or its alloy and so on more cheap.In addition, ink is removed after the etching usually easier than removal noble metal.
Lead frame can also before etching by pre-galvanized.Pre-galvanized material can be identical or different on the end face and bottom surface of lead frame.What the example of suitable pre-galvanized material comprised such as Ni/Pd/Au strike and silver (Ag) and so on can the weldable material of wire-bonded material and such as Sn/Pb, lead-free solder, wicking chemical nickel plating or Au (gold) strike and so on.In an embodiment of the present invention, front uses can grafting material pre-galvanized, and the back side uses weldable material pre-galvanized.In another embodiment, front can use can carry out pre-galvanized by wire-bonded material, and the back side can pre-galvanized and covering with etchant resist.In a further embodiment, organic material can be printed or be coated on lead frame with for use as photoresist.
Figure 36 a illustrates and is etched with the film (1100) forming chip bonding pad (1110) and multiple electrical lead (1105).The bottom that film is compared at the top of film has been etched to larger degree.Figure 36 b illustrates the chip (1120) being electrically connected to the lead frame shown in Figure 36 a via wire-bonded (1125).In Figure 36 b, integrated circuit (IC) chip (1120) has used adhesive (1115) to be attached to lead frame (1100), and chip package has used epoxy sealing material (1130) to cover.Street regions (1135) makes to be electrically connected and the isolation of packed chip (1120).
Chip (1120) be attached to lead frame chip bonding pad (1110) and packed after, the back side of lead frame can by back-patterning and be etched with isolation electrical lead (1105) and chip bonding pad (1110), or each several part of electric isolution lead frame is to produce expectation parts.Because the back side is partially etched, so this back etch process will carry out more quickly and thus advantageously improve unit per hour (UPH) capacity and reduce costs.
The bottom die pad of previous lead frame normally plane.There is the example of the lead frame of the bottom die pad of plane shown in Figure 37 b.But in some examples, the pipe core welding disc of these planes tends to cause solder void problem when wafer-level package being installed to printed circuit board (PCB).Not bound by theory, the phenomenon that solder void is mainly caused by the degasification of encapsulation solvent should be believed.Although solder void reduces the efficiency of electrical contact and thus can cause secondary integrity problem, solder void only can cut detection by X-ray microscope method or destructive differential usually.
According to a further aspect in the invention, lead frame can have the bottom die pad of opening.The embodiment of such pipe core welding disc is shown in Figure 38.Opening (1255) can form passage on pipe core welding disc (1210), and reduces the surface area of the contact between pipe core welding disc and print surface plate, thus advantageously reduces the amount of solder void.Opening or passage (1255) play pore, to make not having entrapped air during remelting.
The bottom land (1210) of opening is obtained by the electroplating mask making little array below the pad on the bottom side of lead frame.At etching, the array of this electroplating mask will produce half-etching passage on bottom die pad.Mask will play etchant resist effect during etch process.
Etching mask can be nickel/palladium/golden synthetic (NiPdAu), silver (Ag), antimony (Sn), nickel (Ni) or its mixture, or anyly applies or be printed onto nonmetal or organic material on lead frame or ink.Etching mask can be baked or UV solidification as required.Other suitable mask and photoresist material are known to those skilled in the art.The technique sheltered and etch can perform as discussed previously.
Figure 38 illustrates to have the wafer-level package (1240) that multiple integrated circuit (IC) chip (1220,1250) is installed to the open bottom pipe core welding disc (1210) on it.Lower chip (1220) is attached to opening pipe core welding disc via adhesive (1215), and upper chip (1250) is attached to lower chip (1220) via adhesive (1245).Chip (1220,1250) is electrically connected to electrical lead (1205) via wire-bonded (1225), although chip (1220,1250) also can be electrically connected to each other in other embodiments.Using can be encapsulant (1230) packaged chip of epoxy resin or another material.
Although Figure 38 illustrates the wafer-level package of the integrated circuit (IC) chip comprising two tube core closed assemblies, only can there is one single chip in other embodiments of the invention, and three or more tube core closed assembly chips can be had in a further embodiment.All these embodiments all within the scope of the present invention.The different number chip of the different chip bonding pads be attached on lead frame can also be had.Such as, a chip bonding pad of lead frame can have singulated dies chip, but another chip bonding pad on same lead frame can be three tube core chip.Therefore, the present invention can be used on single lead frame, prepare multiple difference and different chip.
Figure 39 a and 39b illustrates two embodiments of wafer-level package (1340) according to a further aspect of the invention, and wherein electrical connection dish has different structure.Figure 39 a illustrates that wherein all electrical connection dishes (1305) are for square and be arranged in two concentric row with the wafer-level package (1340) making each terminal pad keep separating enough distances around chip (1320).Figure 39 b illustrates that wherein electrical connection dish (1305) is the wafer-level package (1340) introducing lead-in wire (1309) form.Chip (1320) in wiring (1325) formation Figure 39 a and 39b and the electrical connection be electrically connected between dish (1305).Introduce lead-in wire to prepare in etch device, or they can use the routine techniques of such as silk screen printing to be applied on lead frame.In alternative embodiments, the arbitrary terminal pad on lead frame can have any shape of such as ellipse, rectangle or circle.On lead frame, this optional terminal pad shape Anywhere within the scope of the invention.
The wiring (1325) in Figure 39 a, chip (1320) being connected to electrical connection dish is longer than chip (1320) being connected in Figure 39 b the wiring (1325) introducing lead-in wire.Although the embodiment in Figure 39 a provides the difference being better than prior art lead frame to improve and is efficient, sometimes carefully must avoid wiring contact, otherwise just become too close.Once in a while, the technology in special formation loop is used to keep being separated to make wiring.This technology is useful, although they can make wire bonding technique slack-off sometimes.On the contrary, in Figure 39 b, introduce the end of lead-in wire (1309) quite close to the electric terminal on IC chip (1320) periphery, therefore form the amount much shorter of the necessary wiring of electrical connection.Is formed because these wirings (1325) are customized by gold, the length shorter permission institute therefore for the wiring of wire-bonded uses golden amount minimizing, and because this reducing production cost.
Although the electrical connection dish (1309) in Figure 39 a is all illustrated as the introducing lead-in wire consistent with the present invention, some terminal pads can be the forms introducing lead-in wire, and other terminal pad has another form, such as convention square lead-in wire.Such as, the electrical connection dish closest to chip can be form that is square, circular or oval terminal pad, and can have introducing lead-in wire away from the electrical connection dish of chip.This combination within the scope of the invention.
Figure 40 a illustrates the sectional view of an embodiment of wafer-level package (1340) according to a further aspect of the invention, wherein IC chip is the flip-chip with the solder joint (1380) be arranged near chip perimeter, and chip electrical receives introducing lead-in wire (1309) extended under the die.Figure 40 b illustrates another embodiment of wafer-level package (1340), and its chips (1320) has the flip-chip being arranged in the solder joint (1380) of array in chip bottom.Solder joint is electrically connected to introducing lead-in wire (1309) extended under the die.As shown in figures 39 and 40, wire-bonded with introduce lead-in wire in flip chip embodiment and can effectively use together with the present invention.
Figure 41 illustrates the preparation of the embodiment using the ELP lead frame introducing lead-in wire and landless selection.Technology for the preparation of lead frame is general suitable with the above-mentioned technology for conventional terminal pad.In step 1, metal frame (1300) will be conversion raw material.In step 2, metal frame is partially etched to produce the partial etch lead frame block with web shape part (1305) and chip attach region (1310).Metal frame (1300) can be made by facilitating arbitrarily material, such as copper or copper alloy.Partial etching step illustrates that material is removed from lead frame (1300) center, so that provide landless lead frame around region (1310).That is, in gained wafer-level package, the center of chip or tube core (1320) will not remain on pipe core welding disc.
In step 3, after partially-etched, lead frame (1300) can carry out selective electroplating to form electrical connection dish (1307) by wire-bonded material with such as Ag, Ni/Au or NiPdAu's, and these electrical connection dishes are the form introducing lead-in wire in the embodiment shown.Electrical lead part (1307) is electrically separated to prevent unexpected electrical contact with chip attach region, and lead frame is separated from each other by compartment (not shown).
Although in Figure 41, unanimously with the present invention to complete partially-etched (step 2) before the selective electroplating (step 3), but these steps can any order easily be carried out, and selective electroplating (step 3) can carry out (step 2) before partially-etched.The order of step will depend on specific embodiment at hand.The surface of the normally selective coating in top (1360) of lead frame, and bottom coating is optional.If the bottom surface of lead frame (1365) are electroplated, then coating can be used as underseal or assembles for plug-in unit.
In step 4, after plating, adhesive (1315) is used chip or tube core (1320) to be attached to the chip attach region (1310) of lead frame.Then use wire bond technology to be formed between the terminal and the electrical lead part (1307) of corresponding lead frame of chip (1320) and be electrically connected (step 5).As previously mentioned, lead portion (1307) introduces the form of lead-in wire.Chip or the attached die step to chip attach district is optionally comprised: chip is placed in active lead-in wire (or contrary, lead-in wire by active in final wafer-level package) on, active lead-in wire will when there is no chip bonding pad supporting chip (as shown in Figure 47 b further).In such an embodiment, chip can use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to paste chip attach region.In this embodiment, electrical connection will be formed between active lead-in wire and integrated circuit (IC) chip.
In Figure 41, chip (1320) is wire-bonded chips, but this chip also can be flip-chip.In such example, as known in the art, wire-bonding step can soldered step substitute.
In step 6, after the electrical lead portion using wire-bonded (1325) chip (1320) to be electrically connected to lead frame is divided, on the compartment being coated in lead frame and separate leadframes by encapsulating agent (1330), lead frame is packed.Then the bottom surface (1365) of lead frame is etched with by back-patterning or back removes web shape part and compartment.In this etching step, organic underseal (1361) or another suitable resist can be applied to the selectivity part bottom lead frame before the etch, thus etch process can remove remaining unwanted part (shown in step 7) in metal frame.
In step 8, then use saw or other proper technology by lead frame singualtion, to form one single chip level encapsulation (1340) (step 8).The bottom of lead frame or wafer-level package optionally scribbles the conductive coating (1375) of such as ink or solder resist material, to prevent the bottom short circuit of wafer-level package when being mounted to printed circuit board (PCB) or miscellaneous equipment.Soldered ball (1380) also optionally affixes to electrical connection dish so that follow-up for wafer-level package (1340) affixing to is expected use location.In addition, solderable material can optionally be applied to electrical connection dish so that follow-up electrical connection.Although these can any one of optional feature can apply before or after singualtion, generally speaking, before singualtion, apply this feature is more convenient.
Figure 42 illustrates the set-up procedure for EMI (electromagnetic interference) shielding being put on ELP lead frame of the present invention.In Figure 42, electrical connection dish (1309) is the form introducing lead-in wire, and lead frame scribbled electromagnetic interference (EMI) shielding material (1385) before singualtion.Figure 41 is identical in two processes with the step 1-6 in 42, prepares package leadframe, therefore will not be further described from metal frame (1300) in step 6.
In the step 7 of Figure 42, cut package leadframe with exposing metal lead frame (1300) at interval region (1335) partial cut, shield (1385) ground connection for EMI.EMI shielding (1385) is then applied on package leadframe and interval region.EMI screening energy applies with any convenient manner known in the art.Such as, shield (1385) to apply by chemical plating, metallide, dipping, splatter, silk screen printing or other proper technology any as known in the art.Before the etch process of follow-up back, resist coating is optionally applied to EMI shielding (shown in step 9).Resist coating will prevent etching material likely attach EMI shield.
In step 9, the bottom (1365) of lead frame is etched with by back-patterning or back removes web shape part and compartment.Organic resist (1361) or another suitable resist can be used to the selectivity part preventing from removing metal frame (1300) at etching.This resist generally will be removed before the final encapsulation of preparation.Electrical connection dish forms the electrical connection being provided to chip during etch process.If resist coating is applied to EMI shielding, then it is removed together with any remaining resist used when etching.
In step 10, then use saw or other proper technology (not shown) singualtion lead frame in interval region, to form one single chip level encapsulation (1340) with EMI shielding (1385).With the embodiment of Figure 41 similarly, the bottom (1365) of lead frame or wafer-level package optionally can scribble the non-conductive coating (1375) of such as ink or solder resist material and so on, to prevent the bottom short circuit of wafer-level package when being mounted to printed circuit board (PCB) or miscellaneous equipment.Soldered ball (1380) or other jockey also optionally affix to electrical connection dish (optionally using solderable material) so that follow-up for wafer-level package affixing to is expected use location.Lead frame can have pipe core welding disc, or can use landless part as shown in figure 42.
EMI shielding (1385) in wafer-level package decreases the amount of the seen environmental interference of packaged chip (1320) or noise, hence improves the performance of chip.The wafer-level package of gained is suitable for the many purposes in circuit and electronic equipment.
Figure 43 a-43c illustrates the step when using the block material of lead frame to be molded selection preparation EMI shielding wafer-level package.In this embodiment, (Figure 43 a) to use the encapsulation agent (1330) of large mould monolithic to cover the lead frame of whole array.After cure package agent, remove mould, leave cell array (1340), then singualtion.Then metal frame (1300) is switched to will encapsulate agent (1330) in interval region (1335) in Figure 43 b under.Must carefully avoid cutting off metal frame and weakening lead frame.Carry out part cutting in lead frame after, as shown in Figure 43 c, apply EMI shielding (1385), and subsequently lead frame singualtion is encapsulated (1340) to obtain one single chip level.
Figure 43 d-43e illustrates the step when using single bag mould to be molded selection preparation EMI shielding wafer-level package.In the embodiment of Figure 43 d, each unit (1340) of lead frame has its encapsulation die cavity, generates the independent moulding unit being coated with encapsulation agent (1330) thus.As shown in Figure 43 e, then EMI shielding (1385) is applied to lead frame, gained lead frame is singualtion in interval region (1335) afterwards.The electrical lead part (1307) of this frame can use plating or other technology to apply.
Auxiliary being molded of band the conventional lead frame mould with bag mould can be used, although can contribute to preventing mold flashing (being pasted to the excessive encapsulation agent of lead frame).Advantageously, the lead-in wire being expected to be useful in shielding connection is exposed, because single mould bag does not cover interval region (1335), therefore not needing to expose by cutting, discussing further as following about Figure 49.Use bag mould to be molded and also eliminate partial saw lead frame with the needs of exposing metal film (1300), shorten cycle time thus and make this technique have higher cost efficiency.The molded separately of lamination is also possible.
Discuss Figure 43 a-43e with reference to EMI shielding being applied in package leadframe before singualtion.Figure 44 a-44c shows the multiple steps in alternate embodiment, wherein first singualtion unit (1340) before applying shielding (1385).Unit (1340) through encapsulation and singualtion (but not EMI shielding) first can be placed on saw cramp (1390) as shown in Figure 44 a, or be placed on saw band or band conveyor (1391) as shown in fig. 44b, or be placed in other to facilitate on device, so that lead frame is to the movement of saw (1392).After singualtion, EMI shielding material (1385) still can be applied to these unit at clip or when bringing by splash, silk screen printing or other means at the unit (1340) through singualtion.After applying shielding material, the wafer-level package completed can be picked up respectively and be inserted transfer dish, pipe, bag, tank or other packing container for being finally delivered to client.
Figure 45 a-45b illustrates partially-etched step when having bottom (1365) of lead frame of EMI shielding (1385).In Figure 45 a, previously used pre-galvanized mask or resist (1361) to cover the bottom (1365) of lead frame, then optionally etched bottom this to form required surface characteristics.Then solder resist (1375) is applied to the bottom of lead frame, then applies solderable material (1362) to form electrical connection dish (Figure 45 b).Solder resist (1375) can depend on that particular requirement is at hand particular leadframe instance convenience or prepares particularly.Solderable material (1362) can comprise silver (Ag), tin (Sn), tin-billon (SnAu), chemical nickel plating palladium leaching gold (ENEPIG) or any other can affix to the electric conducting material of lead frame.Solderable material is by dipping, chemical plating, silk screen printing or other technology applying easily.Soldering paste or soldered ball drip (not shown) and can be used to increase the size of terminal pad so that electricity is afterwards attached.After having prepared EMI shielded lead frame completely, can at this lead frame of interval region (1335) singualtion to form single wafer-level package.
In alternative embodiments, as shown in Figure 45 c, not the adding of EMI shielded lead frame (1365) bottom mask, can be submerged the feature being etched with and exposing bottom surface.Flooding in etching step, do not applying selective electroplating or mask.Flood the terminal pad that etching does not produce protrusion, although etched away net-like character to isolate lead-in wire and pad.After etched bottom, solder resist can be applied to bottom the relatively flat of molded block, and electrical feature (1362) can use solderable material to apply (Figure 45 d).Any required pad and solderable material generally will be oriented to be convenient to PCB and install.The lead frame of gained can in singualtion in interval region (1335) to generate the ELP wafer-level package with EMI shielding (1385).
Figure 46 a-46e illustrates bottom view and the X ray picture of the exemplary embodiment of wafer-level package (1340) constructed in accordance, and wherein electrical connection dish (1305) has introducing lead-in wire (1309) and uses wire-bonded to be connected to chip (1320).X ray picture illustrates the Circuits System of the wafer-level package (1340) through encapsulation agent (1330).
In Figure 46 a, outside lead (1305) is integrated into chip bonding pad (1310) route around, and in Figure 46 b, inside and outside lead-in wire (1305) is all introducing lead-in wire (1309) route.The bottom of wafer-level package will cover with solder resist or protection ink to prevent lead-in wire itself from exposing usually.Therefore, in the wafer-level package of reality, only terminal pad (1305) but not route lines will be visible.
Figure 46 c illustrates that wherein small-size chips (1320) is placed in the wafer-level package (1340) on pad by use conductive epoxy resin.Outside lead (1305) row is routed, and inner lead (1305) is capable is not routed and for square.Due to the route of outside lead, use wiring amount than do not have a lead by time necessary few.
Figure 46 d illustrates and wherein uses conductive epoxy resin to be placed in by small-size chips (1320) on pad and the wafer-level package of the chip drawing inside and outside lead-in wire (1305) of route.Fewer than the amount used in Figure 46 c for the amount of the gold thread of wire-bonded in Figure 46 d.
Figure 46 e illustrates that wherein large size chip (1320) is placed on route lead-in wire (1309) itself, and uses non-conductive epoxy resin or attached die film by the wafer-level package under chip attach to pipe core welding disc.The amount of required gold thread is than necessary few when not having electrical connection dish (1305) route.
Figure 47 a-47d illustrates the upward view used according to the wafer-level package (1340) having pad and landless embodiment to manufacture of the present invention, and wherein electrical bonding pads (1305) is the form introducing lead-in wire (1309).
Figure 47 a illustrates the wafer-level package (1340) of one way traffic by go between (1309) with surrounding pipe core welding disc (1310).Conductive epoxy resin can be used to chip attach to the hot property of pipe core welding disc for electric purposes and Geng Jia.
Figure 47 b illustrate according to landless select with the wafer-level package (1340) of one way traffic by go between (1309).Lead frame will still have chip attach region in region (1310) around.IC chip can be placed on active lead-in wire, these active lead-in wires will when there is no chip bonding pad supporting chip.Chip can use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to be pasted to lead frame, and electrical connection can be formed between lead-in wire and chip.
Figure 47 c illustrates that wherein pipe core welding disc (1310) is for part metals through-hole form and lead-in wire (1305/1309) point two row surround the wafer-level package (1340) of pads.Inner lead capable (1309) is routed, and outer row (1305) is not routed and do not have introduce lead-in wire.In Figure 47 d, solid pipe core welding disc (1310) and terminal pad (1305-1309) point two row are arranged in around pipe core welding disc.Outside lead (1305) is capable not to be routed, and inner lead is exercised with introducing lead-in wire (1309) route.
Figure 48 a-48b illustrates the sectional view of each embodiment according to wafer-level package of the present invention (1340), and wherein pipe core welding disc is solid or comprises part metals through hole, such as heat through-hole.
Figure 49 a and 49b illustrates according to the vertical view and the sectional view that encapsulate ELP lead frame of the present invention respectively, and the connection electrical ground for EMI shielding is shown.
Figure 49 a illustrates the X ray vertical view of four packaged chips (1320) of lead frame, and chip is electrically connected to introducing lead-in wire (1309).Although four chips (1320) illustrate for the ease of illustration, lead frame can have any size easily and can have any amount of unit.Lead frame packed (in Figure 49 b 1330) and with EMI shielding (in Figure 49 b 1385) cover, but not yet singualtion to form each wafer-level package.EMI curtain coating (1385) is electrically connected dish (1308) electrical contact with each corner.In order to form each encapsulation, lead frame is by dotted line (1335) singualtion of the interval region along expression lead frame.
Figure 49 b singualtion is shown after the sectional view of one of unit of Figure 49 a.Chip (1320) packed (1330) and covering with EMI screen (1385).Arrow between Figure 49 a and 49b illustrates that being used as shielding connects correspondence with the electrical lead (1308) of ground connection, and lead-in wire for introduce lead-in wire (1309) form and at chip (1320) downward-extension.Other lead-in wire is by extending to make these lead-in wires can be connected to EMI shielding (1385) in interval region across packaging line by lead-in wire, and next being used as connects to the electro-magnetic screen layer of ground connection.The solderable material (1362) that encapsulation also has on lead-in wire is so that be connected to circuit board or miscellaneous equipment, and the non-conductive coating (1365) in package bottom.
Various described embodiment of the present invention is not mutually repel, and at random can combine the variant preparing disclosed lead frame.Such as, the bottom of the pipe core welding disc of the lead frame of the uneven etching shown in Figure 37 a can the wafer-level package with foot passage prepared shown in Figure 38 of Cross Hatch and being used for.Equally, the EMI shielding shown in Figure 42 can be applied to the wafer-level package of Figure 27 b to obtain the multi-chip package with EMI shielding.Other variant is also possible and within the scope of the present invention.
Although illustrate especially and describe the present invention with reference to each specific embodiment, it should be appreciated by those skilled in the art that the various change that can do in form or details and do not deviate from the spirit and scope of the present invention.

Claims (16)

1. form a method for Electronic Packaging, said method comprising the steps of:
Form the block with the partial etch lead frame of selectivity pre-galvanized end face and bottom surface, described lead frame comprises the electrical lead part of web shape part, chip attach region, introducing lead-in wire form, wherein said electrical lead part and chip attach region electrically separated, and described lead frame is separated from each other by street portions;
By chip attach to the corresponding chip attach region on lead frame;
One or more electrical connection is formed between one or more terminal of described chip divides with one or more electrical lead portion of corresponding lead frame;
Described lead frame is encapsulated by applying encapsulant on described lead frame with the described street portions being separated described lead frame;
The bottom surface of back-patterning described lead frame is to remove described web shape part and described street portions; And
Singualtion is placed in described encapsulant on described street portions to form each wafer-level package.
2. the method for claim 1, is characterized in that, described chip attach region is chip-pad area or the landless part of described lead frame.
3. the method for claim 1, it is characterized in that, chip attach to the step in chip attach region being comprised is placed on active lead-in wire by described chip, and using non-conductive adhesive or attached die film adhesive to attach described chip, described chip supported by wherein said active lead-in wire when there is no chip bonding pad.
4. the method for claim 1, is characterized in that, described introducing lead-in wire point single file or plurality of rows are around the respective chip attachment levels of lead frame.
5. the method for claim 1, is characterized in that, comprising further is not the electrical lead introducing lead-in wire form.
6. the method for claim 1, is characterized in that, described back-patterning step uses partially-etched or floods etching to carry out.
7. the method for claim 1, is characterized in that, by block material, molded or individual unit is molded and carries out described encapsulation step.
8. the method for claim 1, is characterized in that, described chip attach region is solid or comprises one or more heat through-hole.
9. the method for claim 1, is characterized in that, also comprises one or more electrical connection dishes soldered ball, weldering paint or solderable material being affixed to before or after singualtion described wafer-level package.
10. the method for claim 1, is characterized in that, the step forming electrical connection uses wire bond technology, flip chip technology (fct) or the combination both them.
11. the method for claim 1, is characterized in that, the step forming electrical connection has been come by the end of the connecting terminals on described chip being received the electrical lead part of stretching out from described lead frame.
12. the method for claim 1, is characterized in that, the bottom of the block of lead portion, lead frame or both soldered masks cover.
13. the method for claim 1, is characterized in that, before or after being also included in singualtion, electromagnetic interference shield are applied to described wafer-level package.
14. methods as claimed in claim 13, it is characterized in that, described electromagnetic interference shield is applied by chemical plating, metallide, injection, dipping, sputtering sedimentation or silk-screen printing technique.
15. the method for claim 1, is characterized in that, described chip uses conductive epoxy resin, non-conductive epoxy resin or attached die film adhesive to be attached to described chip attach region.
16. the method for claim 1, is characterized in that, also comprise:
One or more second chip-die is stacked to the top of one or more chip before the described lead frame of encapsulation.
CN201110257072.0A 2010-09-03 2011-08-24 Partially patterned lead frame and manufacture and use its method in semiconductor packages Expired - Fee Related CN102386106B (en)

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US12/875,248 US20110057298A1 (en) 2002-04-29 2010-09-03 Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US12/875,248 2010-09-03
US13/009,362 2011-01-19
US13/009,362 US8236612B2 (en) 2002-04-29 2011-01-19 Partially patterned lead frames and methods of making and using the same in semiconductor packaging

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