TWI382501B - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- TWI382501B TWI382501B TW096143567A TW96143567A TWI382501B TW I382501 B TWI382501 B TW I382501B TW 096143567 A TW096143567 A TW 096143567A TW 96143567 A TW96143567 A TW 96143567A TW I382501 B TWI382501 B TW I382501B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- substrates
- semiconductor device
- sealing resin
- semiconductor wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係關於一種基板上安裝有半導體晶片之半導體裝置之製造方法。The present invention relates to a method of fabricating a semiconductor device in which a semiconductor wafer is mounted on a substrate.
伴隨著近年來電腦、手機、PDA(個人數位助理(Personal Digital Assistance))等電子機器之小型化、高性能化及高速化，人們亦越要求裝載有此種電子機器的IC(積體電路)、LSI(大型積體電路)等半導體晶片之半導體裝置進一步小型化、高速化及高密度化。With the recent miniaturization, high performance, and high speed of electronic devices such as computers, mobile phones, and PDAs (Personal Digital Assistance), there is a growing demand for ICs (integrated circuits) equipped with such electronic devices. The semiconductor device of a semiconductor wafer such as an LSI (large integrated circuit) is further reduced in size, speed, and density.
隨著半導體裝置之小型化，多層配線基板變得薄型化。作為薄型化進展之多層配線基板，已知有譬如將以絕緣樹脂層與配線層交錯形成之增層(bulid up)為主體，且未具備芯基板之無芯基板(參照專利文獻1)。As the size of the semiconductor device is reduced, the multilayer wiring substrate is made thinner. For example, a coreless substrate in which a bulk layer formed by interleaving an insulating resin layer and a wiring layer is formed and a core substrate is not provided (see Patent Document 1) is known.
[專利文獻1]日本專利公開公報特開2004－186265號[Patent Document 1] Japanese Patent Laid-Open Publication No. 2004-186265
如無芯基板，當多層配線基板薄型化進展時，於半導體裝置之製造或檢查過程中受到來自外部之衝擊時，多層配線基板易於受到損傷。即便係於多層配線基板上成形有密封樹脂之封裝構造，與多層配線基板之外形相比，密封樹脂之外形較小，且若為多層配線基板之端部延伸超出密封樹脂之構造時，多層配線基板之端部受損便成為一個問題。故而，需要一種可讓密封樹脂之外形與多層配線基板 之外形相對合之構造。然而，在基板單體進行之密封，由於模具偏移，故不易讓密封樹脂之外形與多層配線基板之外形對合。In the case of a coreless substrate, when the thickness of the multilayer wiring substrate progresses, the multilayer wiring substrate is easily damaged when subjected to an impact from the outside during the manufacture or inspection of the semiconductor device. Even if it is a package structure in which a sealing resin is formed on a multilayer wiring board, the sealing resin is smaller in shape than the outer shape of the multilayer wiring substrate, and if the end portion of the multilayer wiring substrate extends beyond the structure of the sealing resin, the multilayer wiring Damage to the end of the substrate becomes a problem. Therefore, there is a need for a sealing resin to be externally shaped and a multilayer wiring substrate. The outer shape is opposite to the structure. However, the sealing by the substrate alone is difficult to form a shape in which the sealing resin is shaped outside the multilayer wiring substrate due to the mold offset.
本發明係有鑑於前述課題而創作完成者，其目的在於提供一種可減輕薄型化基板其端部之損傷的半導體裝置之製造方法。The present invention has been made in view of the above problems, and an object of the invention is to provide a method of manufacturing a semiconductor device capable of reducing damage of an end portion of a thinned substrate.
本發明之一樣態，係半導體裝置之製造方法。該半導體裝置之製造方法之特徵係包含有以下步驟，即：安裝步驟，係於複數個基板上分別安裝半導體晶片；配設步驟，係配設複數個基板，以使安裝有半導體晶片之各基板的至少一邊與其他基板的邊相接觸；密封步驟，係讓密封樹脂成形在較可形成於複數個基板上之密封樹脂層其外形更大的區域，並連結相鄰之基板群；及單片化步驟，係將各基板及各基板上的密封樹脂按預定尺寸進行切割，使各基板單片化。上述配設步驟中，亦可讓將前述複數個基板朝一方向並置。The same state of the present invention is a method of manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of: mounting a semiconductor wafer on a plurality of substrates; and disposing a plurality of substrates to support each substrate on which the semiconductor wafer is mounted. At least one side is in contact with the sides of the other substrate; the sealing step is such that the sealing resin is formed in a region having a larger outer shape than the sealing resin layer which can be formed on the plurality of substrates, and is connected to the adjacent substrate group; and the single piece In the step of dicing, the sealing resin on each of the substrates and the respective substrates is cut to a predetermined size, and each of the substrates is singulated. In the above arrangement step, the plurality of substrates may be juxtaposed in one direction.
依據此樣態，可讓薄型化之基板外形與密封樹脂之外形一致，因此可大幅度降低外力作用於基板端部之可能性。藉此，在半導體裝置之製造過程與檢查步驟中，可減低傷及基板端部之可能性，提高半導體裝置之製造成品率。According to this aspect, the shape of the thinned substrate can be made to conform to the shape of the sealing resin, so that the possibility of external force acting on the end portion of the substrate can be greatly reduced. Thereby, in the manufacturing process and the inspection step of the semiconductor device, the possibility of injuring the end portion of the substrate can be reduced, and the manufacturing yield of the semiconductor device can be improved.
以下將本發明係依較佳態樣加以說明。當然此係說明本發明之較佳形態，並無法據此限縮本發明之範圍。The invention will now be described in terms of preferred aspects. It is a matter of course that this is a preferred form of the invention and is not intended to limit the scope of the invention.
參照圖式說明實施形態之半導體裝置之製造方法。A method of manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings.
圖1係顯示實施形態之半導體裝置製造方法所使用之基板的構造圖。基板20具有層間絕緣膜與配線膜交錯層積且不含芯基板之多層配線構造。更詳細言之，複數個配線層22係挾層間絕緣膜24而加以層積。配線層22係譬如採用銅。為不同層的配線層22之間，係藉由設置於增間絕緣膜24上之導通孔插塞26而電性連接。基板20背面之配線層22a周圍，係形成有由耐熱性良好的樹脂材料組成之焊料掩膜28，且熔焊至基板20時，為避免焊料附著於必要區域以外的其他區域，係對最下層之層間絕緣膜24a進行塗層。又，接合有BGA球50之球區部29係呈陣列狀地多數配設於基板20之背面。各球區部29之表面上係覆蓋有有機表面保護塗覆材料(OSP)21。另一方面，藉由電解鍍敷而形成之鎳(Ni)、鉛(Pd)、金(Au)或其等之合金所組成的電極墊25，係呈陣列狀地多數配設於安裝有半導體晶片側之基板20表面上，且各電極墊25之上，設有由錫、鉛、或其等之合金所組成之C4(控制崩潰接片接合(Controlled Collapse Chip Connection))凸塊27。Fig. 1 is a structural view showing a substrate used in a method of manufacturing a semiconductor device of an embodiment. The substrate 20 has a multilayer wiring structure in which an interlayer insulating film and a wiring film are alternately laminated and does not include a core substrate. More specifically, a plurality of wiring layers 22 are laminated by laminating the interlayer insulating film 24. The wiring layer 22 is made of, for example, copper. The wiring layers 22 of different layers are electrically connected by via plugs 26 provided on the interlayer insulating film 24. A solder mask 28 made of a resin material having good heat resistance is formed around the wiring layer 22a on the back surface of the substrate 20, and when soldering to the substrate 20, the solder layer is prevented from adhering to other regions than necessary regions, and the lowermost layer is formed. The interlayer insulating film 24a is coated. Further, the ball portion 29 to which the BGA balls 50 are bonded is arranged in an array and is disposed on the back surface of the substrate 20. The surface of each ball portion 29 is covered with an organic surface protective coating material (OSP) 21. On the other hand, the electrode pads 25 composed of nickel (Ni), lead (Pd), gold (Au) or the like formed by electrolytic plating are mostly arranged in an array and mounted with a semiconductor. On the surface of the substrate 20 on the wafer side, and on each of the electrode pads 25, a C4 (Controlled Collapse Chip Connection) bump 27 composed of an alloy of tin, lead, or the like is provided.
基板20之製造方法並無特別限定，可藉由組合眾所周知的微影製程、蝕刻、鍍敷、積層等技術而獲致。作為獲得無芯基板之方法，可例舉在銅等金屬板上形成由層間絕緣膜與配線層電解所構成之增層後，對金屬板進行蝕刻或剝離等手法。The method of manufacturing the substrate 20 is not particularly limited, and can be obtained by a combination of well-known techniques such as photolithography, etching, plating, and lamination. As a method of obtaining a coreless substrate, a method of forming a layer formed by electrolysis of an interlayer insulating film and a wiring layer on a metal plate such as copper, and then etching or peeling the metal plate may be mentioned.
且基板20之外形宜使用大於半導體裝置預先設定好的尺 寸。譬如半導體裝置所使用之基板的尺寸為45 mm角時，將基板20各邊之長度較45 mm再多取1 mm程度。And the shape of the substrate 20 is preferably larger than the predetermined size of the semiconductor device. Inch. For example, when the size of the substrate used in the semiconductor device is 45 mm, the length of each side of the substrate 20 is more than 1 mm from 45 mm.
準備多數個基板20，如圖2(A)所示，將LSI(大型積體電路)等半導體晶片30安裝至基板20。具體言之，在將設有半導體晶片30之外部電極端子的表面朝下狀態，藉由熔焊各焊接凸塊32及與其相對應的C4凸塊27，進行半導體晶片30之覆晶安裝。A plurality of substrates 20 are prepared, and as shown in FIG. 2(A), a semiconductor wafer 30 such as an LSI (large integrated circuit) is mounted on the substrate 20. Specifically, the flip chip mounting of the semiconductor wafer 30 is performed by welding the respective solder bumps 32 and the C4 bumps 27 corresponding thereto with the surface of the external electrode terminals on which the semiconductor wafer 30 is provided facing downward.
其次，如圖2(B)所示，將填充料70填充至半導體晶片30與基板20之間。由此，焊料結合部分所產生的壓力加以分散，故可改善半導體裝置10之耐溫度變化特性，並可抑制半導體裝置10的彎曲。Next, as shown in FIG. 2(B), the filler 70 is filled between the semiconductor wafer 30 and the substrate 20. Thereby, the pressure generated by the solder joint portion is dispersed, so that the temperature change resistance characteristic of the semiconductor device 10 can be improved, and the bending of the semiconductor device 10 can be suppressed.
對多數個基板分別進行如上述之半導體晶片安裝程序後，如圖3(A)及圖3(B)所示，配設多數個基板20，以使各基板20的至少一邊與其他基板20的邊相接觸。本實施形態中，係將4個基板20朝同一方向排列放置。此時，在相鄰接之基板20間，宜使基板20的上方面高度保持一致。After performing the semiconductor wafer mounting procedure as described above on each of the plurality of substrates, as shown in FIGS. 3(A) and 3(B), a plurality of substrates 20 are disposed so that at least one side of each substrate 20 and the other substrate 20 are provided. Side contact. In the present embodiment, four substrates 20 are arranged in the same direction. At this time, it is preferable that the height of the upper surface of the substrate 20 be kept uniform between the adjacent substrates 20.
其次，如圖4(A)及圖4(B)所示，藉由傳遞模塑法於並置的各基板20上成形密封樹脂40。此時，傳遞模塑裝置所使用之上模，並非與各半導體裝置之密封樹脂的設計形狀相吻合的模，而是使用較該模大者。本實施形態中，為使各半導體晶片30之背面露出，係使用與半導體晶片30周邊相分離，且相鄰接之基板20上的密封樹脂40為相連的上模，並於多數個基板20上進行密封樹脂注塑。藉由讓經模塑後之密封樹脂形狀大於設計形狀，可避免設計區域內產 生渣料毛邊等之毛刺。又，藉由密封樹脂40硬化而讓各基板20加以連接，故可作為多數個基板20的集合體而進行處理。再者，由於可在產品區域外的基板上設置注入密封樹脂之閘口，故無需開發特別的模具，可降低模具所需的費用。Next, as shown in FIGS. 4(A) and 4(B), the sealing resin 40 is formed on each of the substrates 20 which are juxtaposed by transfer molding. At this time, the upper mold used in the transfer molding apparatus is not a mold that matches the design shape of the sealing resin of each semiconductor device, but is used to be larger than the mold. In the present embodiment, in order to expose the back surface of each semiconductor wafer 30, it is separated from the periphery of the semiconductor wafer 30, and the sealing resin 40 on the adjacent substrate 20 is a continuous upper mold, and is applied to a plurality of substrates 20. Sealing resin injection molding. By allowing the molded resin to be shaped larger than the design shape, it is possible to avoid production in the design area. Raw burrs and other burrs. Further, since the sealing resin 40 is cured and the substrates 20 are connected, it can be handled as an aggregate of a plurality of substrates 20. Furthermore, since the gate into which the sealing resin is injected can be provided on the substrate outside the product area, it is not necessary to develop a special mold, and the cost required for the mold can be reduced.
其次，如圖5(A)及圖5(B)所示，使用切割裝置等的切削器械，並依預定之製品尺寸將基板20單片化。藉由切割加工，對各基板20及其上的密封樹脂40將超出製品尺寸的部分R切除。Next, as shown in FIGS. 5(A) and 5(B), a cutting instrument such as a cutting device is used, and the substrate 20 is singulated according to a predetermined product size. By the cutting process, the portion R of the substrate 20 and the sealing resin 40 thereon is removed beyond the size of the article.
各基板20單片化後，如圖6所示，將BGA球50安裝至設於各基板20上之球區部29(參照圖1)。藉由以上步驟，獲致將半導體晶片30覆晶安裝於基板20上，且密封樹脂40成形於與半導體晶片30周邊相分離的位置上之半導體裝置10。更具體言之，熔焊設置於半導體晶片30上之凸塊32，以及與該等凸塊32相對應而設於基板20上的C4凸塊27，並將填充料70填充至半導體晶片30與基板20之間。After the respective substrates 20 are singulated, as shown in FIG. 6, the BGA balls 50 are attached to the ball portion 29 provided on each of the substrates 20 (see FIG. 1). Through the above steps, the semiconductor wafer 30 is flip-chip mounted on the substrate 20, and the sealing resin 40 is formed on the semiconductor device 10 at a position separated from the periphery of the semiconductor wafer 30. More specifically, the bumps 32 disposed on the semiconductor wafer 30, and the C4 bumps 27 disposed on the substrate 20 corresponding to the bumps 32 are soldered, and the filler 70 is filled to the semiconductor wafer 30 and Between the substrates 20.
依以上說明之半導體裝置之製造方法，可讓薄型化之基板外形與密封樹脂之外形一致，故可大幅度降低外力作用於基板端部之可能性。由此，可降低半導體裝置之製造過程以及檢查過程中，基板端部受損之可能性，提高半導體裝置之產品成品率。According to the method for manufacturing a semiconductor device as described above, the shape of the thinned substrate can be made to conform to the shape of the sealing resin, so that the possibility of external force acting on the end portion of the substrate can be greatly reduced. Thereby, the possibility of damage to the end portion of the substrate during the manufacturing process of the semiconductor device and the inspection process can be reduced, and the product yield of the semiconductor device can be improved.
又，由於模塑時係在基板上形成大於設計形狀之密封樹脂，故在基板上可能因模塑而產生殘渣毛刺之處係在製品區域之外側。製品區域之外側因可藉由切割等而加以切 除，故進行成品所得之半導體裝置上不會殘留有殘渣毛刺等。由此，可提高半導體裝置之產品品質。Further, since the sealing resin having a larger shape than the design shape is formed on the substrate during molding, the residue on the substrate due to molding may be on the outer side of the product region. The outer side of the product area can be cut by cutting or the like Except for this, no residue burrs or the like remain on the semiconductor device obtained by the finished product. Thereby, the product quality of the semiconductor device can be improved.
再者，使用密封樹脂而讓半導體裝置封裝化的方法，並不限於使用模塑裝置來讓導入孔內之密封樹脂熱硬化之手法。亦可採用如下述方法，即，並非於最後才進行模塑裝置之熱硬化，而可自中途開始，如圖7所示，使用簡易構造的熱硬化裝置完成熱硬化處理。Further, the method of encapsulating the semiconductor device using the sealing resin is not limited to the method of using the molding device to thermally harden the sealing resin in the introduction hole. It is also possible to adopt a method in which the heat hardening of the molding apparatus is not performed at the end, but the heat hardening treatment can be completed using a heat-curing device of a simple structure as shown in Fig. 7 .
熱硬化裝置100係包含有下側板110、上側板120、加壓設備(圖式未標注)以及加熱設備(圖式未標注)。下側板110包含有與半導體裝置之基板20之底面相連接之平面。另一方面，上側板120包含有與半導體裝置之密封樹脂40之頂面相連接之平面。下側板110與上側板120上分別設有加熱器等加熱設備，下側板110與上側板120係藉由加熱設備而將半導體裝置所用的密封樹脂40加熱至其硬化溫度。又，下側板110與上側板120之間所挾有之複數個基板20之集合體，係藉由加壓設備而以預定之壓力進行押壓。藉由使用如上述之熱硬化裝置100，可將複數個基板20之集合體保持於加熱至預定溫度的下側板110與上側板120之間，故可於抑制彎曲的同時，完成密封樹脂40之硬化。The heat curing device 100 includes a lower side plate 110, an upper side plate 120, a pressurizing device (not shown), and a heating device (not shown). The lower side plate 110 includes a plane that is connected to the bottom surface of the substrate 20 of the semiconductor device. On the other hand, the upper side plate 120 includes a plane that is connected to the top surface of the sealing resin 40 of the semiconductor device. The lower side plate 110 and the upper side plate 120 are respectively provided with heating means such as a heater, and the lower side plate 110 and the upper side plate 120 heat the sealing resin 40 used for the semiconductor device to a curing temperature thereof by a heating device. Further, an aggregate of a plurality of substrates 20 interposed between the lower side plate 110 and the upper side plate 120 is pressed by a predetermined pressure by a pressurizing device. By using the thermal curing device 100 as described above, the assembly of the plurality of substrates 20 can be held between the lower side plate 110 and the upper side plate 120 heated to a predetermined temperature, so that the sealing resin 40 can be completed while suppressing the bending. hardening.
參照圖8(A)說明使用上述熱硬化裝置而讓半導體裝置封裝化之程序。將欲封裝化之複數個基板之集合體(以下稱為基板集合體)依次以P1，P2，P3…表示。將預定溫度下至硬化所需時間表示為標準硬化時間T1。首先，對於基板集合體P1，令模塑裝置所進行的熱硬化以T1的一半時間 (1/2×T1)進行。其後，將基板集合體P1設置於熱硬化裝置，並將其後可進行封裝化之基板集合體P2設置於模塑裝置。接著，令熱硬化裝置對基板集合體P1所進行之熱硬化以T1的一半時間(1/2×T1)進行，與之同時，對於基板集合體P2，令模塑裝置所進行之熱硬化以T1的一半時間(1/2×T1)進行。即，對於不同的基板集合體，係並行藉由模塑裝置所進行之熱硬化，以及藉由熱硬化裝置所進行之熱硬化。依此，如圖8(B)所示，與僅採用模塑裝置並依次讓基板集合體封裝化的情況下所需時間相比，封裝化所需時間可減半，可提高半導體裝置之生產性能。再者，與模塑裝置相比，熱硬化裝置係構造簡單，故價格較為低廉，與保有兩台模塑裝置的情況相比，可抑制投資所需費用。A procedure for packaging a semiconductor device using the above-described thermal curing device will be described with reference to Fig. 8(A). An aggregate of a plurality of substrates to be encapsulated (hereinafter referred to as a substrate assembly) is sequentially represented by P1, P2, P3, . The time required to cure at a predetermined temperature is expressed as a standard hardening time T1. First, for the substrate assembly P1, the heat hardening performed by the molding apparatus is half the time of T1. (1/2 × T1). Thereafter, the substrate assembly P1 is placed in a thermosetting device, and the substrate assembly P2 which can be packaged thereafter is placed in the molding apparatus. Next, the thermal curing of the substrate assembly P1 by the thermosetting apparatus is performed at half the time T1 (1/2 × T1), and at the same time, the thermal assembly of the substrate assembly P2 is performed by the molding apparatus. Half of T1 (1/2 × T1) is performed. That is, for different substrate assemblies, thermal hardening by a molding apparatus in parallel and thermal hardening by a heat hardening apparatus are performed. Accordingly, as shown in FIG. 8(B), the time required for encapsulation can be halved, and the production of the semiconductor device can be improved, compared with the time required in the case where only the molding apparatus is used and the substrate assembly is sequentially packaged. performance. Further, compared with the molding apparatus, the thermosetting apparatus has a simple structure and is relatively inexpensive, and the cost of investment can be suppressed as compared with the case of holding two molding apparatuses.
更具體言之，密封樹脂係採用T1為60秒的習知態樣之環氧樹脂時，每一個基板集合體所需之熱硬化處理的工作時間可約為30秒。又，即便與先前態樣相比而需較長之T1時，熱硬化處理之工作時間亦可減半。如，T1為120秒時，每一個基板集合體所需的熱硬化處理之工作時間可約為60秒。More specifically, when the sealing resin is a conventional epoxy resin having a T1 of 60 seconds, the working time of the heat hardening treatment required for each of the substrate assemblies may be about 30 seconds. Moreover, even if a longer T1 is required than in the previous aspect, the working time of the heat hardening treatment can be halved. For example, when T1 is 120 seconds, the working time of the heat hardening treatment required for each substrate assembly may be about 60 seconds.
再者，熱硬化裝置100之下側板110或/及上側板120，亦可配合基板集合體之彎曲特性，而為可將與基板集合體連接的面做成矯正彎曲之形狀。據此，可更進一步抑制基板集合體之彎曲。Further, the lower side plate 110 or/and the upper side plate 120 of the heat curing device 100 may have a curved shape in which the substrate assembly is connected, and the surface to be connected to the substrate assembly may be curved in a corrected shape. According to this, the bending of the substrate assembly can be further suppressed.
又，上述之封裝化程序中，係將T1二等分，惟，亦可藉由使用2台以上的熱硬化裝置而將T1三等分，於包含模塑 裝置與多數個熱硬化裝置的3處以上並行地進行熱硬化處理。Further, in the above-described encapsulation program, T1 is halved, but T1 may be equally divided by using two or more thermal curing devices to include molding. The apparatus is thermally hardened in parallel with three or more of a plurality of thermal curing apparatuses.
本發明並不限於上述實施方式，亦可依當業者之學識而施加各種設計變更等之變形，且如此種施加變形後之實施方式仍包括在本發明內。The present invention is not limited to the above-described embodiments, and various modifications such as design changes may be applied depending on the knowledge of the practitioner, and such an embodiment after the application of the deformation is still included in the present invention.
如圖2(A)中，半導體晶片30係覆晶安裝於基板20上，惟半導體晶片30亦可藉由打線接而合與基板20進行電性連接。As shown in FIG. 2(A), the semiconductor wafer 30 is flip-chip mounted on the substrate 20. However, the semiconductor wafer 30 can be electrically connected to the substrate 20 by wire bonding.
又，圖3(A)及圖3(B)中，複數個基板20為同一方向並置，惟亦可讓複數個基板20縱橫二次元並列。Further, in FIGS. 3(A) and 3(B), a plurality of substrates 20 are juxtaposed in the same direction, but a plurality of substrates 20 may be arranged in parallel with each other.
再者，圖4(A)及圖4(B)中，密封樹脂40係設置於各半導體晶片30之周邊，且各半導體晶片30的背面露出，惟密封樹脂40之形狀亦可為任意，可藉由密封樹脂40而整個披覆住各半導體晶片30。Further, in FIGS. 4(A) and 4(B), the sealing resin 40 is provided around the respective semiconductor wafers 30, and the back surface of each of the semiconductor wafers 30 is exposed, but the shape of the sealing resin 40 may be arbitrary. Each of the semiconductor wafers 30 is entirely covered by the sealing resin 40.
20‧‧‧基板20‧‧‧Substrate
21‧‧‧脂塗層材料21‧‧‧Lipid coating materials
22‧‧‧配線層22‧‧‧Wiring layer
22a‧‧‧背面配線層22a‧‧‧Back wiring layer
24‧‧‧層間絕緣膜24‧‧‧Interlayer insulating film
24a‧‧‧最下層層間絕緣膜24a‧‧‧The lowest interlayer insulating film
25‧‧‧電極墊25‧‧‧electrode pads
26‧‧‧導通孔插塞26‧‧‧Through hole plug
27‧‧‧凸塊27‧‧‧Bumps
28‧‧‧焊料掩膜28‧‧‧ solder mask
29‧‧‧球區部29‧‧‧Ball Division
30‧‧‧半導體晶片30‧‧‧Semiconductor wafer
32‧‧‧焊接凸塊32‧‧‧welding bumps
40‧‧‧密封樹脂40‧‧‧ sealing resin
50‧‧‧BGA球50‧‧‧BGA ball
70‧‧‧填充材料70‧‧‧Filling materials
100‧‧‧熱硬化裝置100‧‧‧Heat hardening device
110‧‧‧上側板110‧‧‧Upper side panel
120‧‧‧下側板120‧‧‧ lower side panel
P1,P2‧‧‧基板集合體P1, P2‧‧‧ substrate assembly
圖1係表示用於半導體裝置製造上之基板的構造圖。Fig. 1 is a structural view showing a substrate used in the manufacture of a semiconductor device.
圖2(A)、(B)係表示半導體晶片之安裝步驟的剖面圖。2(A) and 2(B) are cross-sectional views showing a mounting step of a semiconductor wafer.
圖3：圖3(A)係表示載置基板之步驟的平面圖。圖3(B)係表示圖3(A)之A-A'線上的剖面圖。Fig. 3: Fig. 3(A) is a plan view showing a step of placing a substrate. Fig. 3(B) is a cross-sectional view taken along line A-A' of Fig. 3(A).
圖4：圖4(A)係表示模塑步驟之平面圖。圖4(B)係表示圖4(A)之A-A'線上的剖面圖。Figure 4: Figure 4 (A) shows a plan view of the molding step. Fig. 4(B) is a cross-sectional view taken along line A-A' of Fig. 4(A).
圖5：圖5(A)係表示基板單片化步驟之平面圖。圖5(B)係表示圖5(A)之A-A'線上的剖面圖。Figure 5: Figure 5 (A) is a plan view showing the substrate singulation step. Fig. 5(B) is a cross-sectional view taken along line A-A' of Fig. 5(A).
圖6係表示焊球安裝步驟圖。Fig. 6 is a view showing a step of mounting a solder ball.
圖7係表示以簡易構造的熱硬化裝置進行之成形樹脂層的形成方法圖。Fig. 7 is a view showing a method of forming a molding resin layer by a thermosetting apparatus having a simple structure.
圖8：圖8(A)係表示使用熱硬化裝置而硬化半導體裝置之成形樹脂層的流程圖。圖8(B)係表示僅使用模塑裝置而硬化半導體裝置之成形樹脂層的流程圖。Fig. 8: Fig. 8(A) is a flow chart showing the curing of the molding resin layer of the semiconductor device using a heat curing device. Fig. 8(B) is a flow chart showing the curing of the molding resin layer of the semiconductor device using only a molding device.
20‧‧‧基板20‧‧‧Substrate
21‧‧‧塗覆材料21‧‧‧Coating materials
22‧‧‧配線層22‧‧‧Wiring layer
22a‧‧‧背面配線層22a‧‧‧Back wiring layer
24‧‧‧層間絕緣膜24‧‧‧Interlayer insulating film
24a‧‧‧最下層之層間絕緣膜24a‧‧‧The lowermost interlayer insulating film
25‧‧‧電極墊25‧‧‧electrode pads
26‧‧‧導通孔插塞26‧‧‧Through hole plug
27‧‧‧凸塊27‧‧‧Bumps
28‧‧‧焊料掩膜28‧‧‧ solder mask
29‧‧‧球區部29‧‧‧Ball Division
30‧‧‧半導體晶片30‧‧‧Semiconductor wafer
32‧‧‧焊接凸塊32‧‧‧welding bumps
40‧‧‧密封樹脂40‧‧‧ sealing resin
50‧‧‧BGA球50‧‧‧BGA ball
70‧‧‧填充材料70‧‧‧Filling materials
100‧‧‧熱硬化裝置100‧‧‧Heat hardening device
110‧‧‧上側板110‧‧‧Upper side panel
120‧‧‧下側板120‧‧‧ lower side panel
P1,P2‧‧‧基板集合體P1, P2‧‧‧ substrate assembly
Claims (3)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007015093A JP4344752B2 (en) | 2007-01-25 | 2007-01-25 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200841431A TW200841431A (en) | 2008-10-16 |
| TWI382501B true TWI382501B (en) | 2013-01-11 |
Family
ID=39725758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096143567A TWI382501B (en) | 2007-01-25 | 2007-11-16 | Semiconductor device manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4344752B2 (en) |
| TW (1) | TWI382501B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9972593B2 (en) * | 2014-11-07 | 2018-05-15 | Mediatek Inc. | Semiconductor package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001267470A (en) * | 2000-03-16 | 2001-09-28 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| TW498519B (en) * | 2000-07-13 | 2002-08-11 | Nippon Electric Co | Semiconductor device having heat spreader attached thereto and method of manufacturing the same |
| JP2005158873A (en) * | 2003-11-21 | 2005-06-16 | Fdk Corp | Method of manufacturing semiconductor device |
-
2007
- 2007-01-25 JP JP2007015093A patent/JP4344752B2/en active Active
- 2007-11-16 TW TW096143567A patent/TWI382501B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001267470A (en) * | 2000-03-16 | 2001-09-28 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| TW498519B (en) * | 2000-07-13 | 2002-08-11 | Nippon Electric Co | Semiconductor device having heat spreader attached thereto and method of manufacturing the same |
| JP2005158873A (en) * | 2003-11-21 | 2005-06-16 | Fdk Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200841431A (en) | 2008-10-16 |
| JP2008182100A (en) | 2008-08-07 |
| JP4344752B2 (en) | 2009-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI576927B (en) | Semiconductor device and manufacturing method thereof | |
| US8796561B1 (en) | Fan out build up substrate stackable package and method | |
| US9040361B2 (en) | Chip scale package with electronic component received in encapsulant, and fabrication method thereof | |
| US7138706B2 (en) | Semiconductor device and method for manufacturing the same | |
| JP5598787B2 (en) | Manufacturing method of stacked semiconductor device | |
| US20110115085A1 (en) | Semiconductor device and method of fabricating the same | |
| US20100261311A1 (en) | Method of manufacturing a semiconductor device | |
| TWI423355B (en) | Chip-sized package and fabrication method thereof | |
| JP5980566B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6841884B2 (en) | Semiconductor device | |
| US20130234330A1 (en) | Semiconductor Packages and Methods of Formation Thereof | |
| JP5543084B2 (en) | Manufacturing method of semiconductor device | |
| US7663254B2 (en) | Semiconductor apparatus and method of manufacturing the same | |
| US20080174005A1 (en) | Electronic device and method for manufacturing electronic device | |
| JP5404513B2 (en) | Manufacturing method of semiconductor device | |
| US20100219522A1 (en) | Semiconductor device and method of manufacturing the same, and electronic apparatus | |
| US8198141B2 (en) | Intermediate structure of semiconductor device and method of manufacturing the same | |
| TWI382501B (en) | Semiconductor device manufacturing method | |
| US20210407821A1 (en) | Semiconductor package and method of manufacturing semiconductor package | |
| TWI450348B (en) | Electronic device with vertical conductive connectors and method thereof | |
| JP2002270627A (en) | Semiconductor device manufacturing method | |
| JP2012015446A (en) | Method of manufacturing semiconductor device | |
| TWI654691B (en) | Semiconductor device package with a stress relax pattern | |
| JP2005142452A (en) | Semiconductor device and its manufacturing method | |
| JP5587464B2 (en) | Manufacturing method of semiconductor device |