JP2008182100A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP2008182100A
JP2008182100A JP2007015093A JP2007015093A JP2008182100A JP 2008182100 A JP2008182100 A JP 2008182100A JP 2007015093 A JP2007015093 A JP 2007015093A JP 2007015093 A JP2007015093 A JP 2007015093A JP 2008182100 A JP2008182100 A JP 2008182100A
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Prior art keywords
substrate
substrates
semiconductor device
sealing resin
semiconductor chip
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JP4344752B2 (en
Inventor
Fujio Kanayama
富士夫 金山
Tomoshi Oide
知志 大出
Mitsuru Adachi
充 足立
Tetsunaga Niimi
哲永 新美
Hidetoshi Kusano
英俊 草野
Yuji Nishitani
祐司 西谷
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Sony Interactive Entertainment Inc
Sony Corp
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Sony Corp
Sony Computer Entertainment Inc
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Priority to JP2007015093A priority Critical patent/JP4344752B2/en
Priority to TW096143567A priority patent/TWI382501B/en
Publication of JP2008182100A publication Critical patent/JP2008182100A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of reducing damage in the end of a thinned substrate. <P>SOLUTION: Semiconductor chips 30 are respectively flip-flop mounted on a plurality of substrates 20 with an insulating layer and a wiring layer laminated therein. The size of the substrate 20 is larger than a stipulated size. Sealing resins 40 are molded in a state where the plurality of substrates 20, where the semiconductor chips 30 are mounted, respectively, is aligned in one direction. The molding regions of the sealing resins 40 are made to be larger than the outer shapes of a sealing resin layers to be molded in the respective substrates 20. Then, surplus regions R are cut by using a dicing device, etc., so as to meet the prescribed dimension, and the respective substrates 20 are made into single pieces. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、基板に半導体チップが実装された半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a substrate.

近年、コンピュータ、携帯電話、ＰＤＡ（Personal Digital Assistance）などの電子機器の小型化、高機能化・高速化に伴い、こうした電子機器向けのＩＣ（集積回路）、ＬＳＩ（大規模集積回路）などの半導体チップを搭載した半導体装置のさらなる小型化、高速化および高密度が要求されている。   In recent years, as electronic devices such as computers, mobile phones, and PDAs (Personal Digital Assistance) have become smaller, more sophisticated, and faster, ICs (integrated circuits), LSIs (Large Scale Integrated Circuits), etc. There is a demand for further miniaturization, higher speed and higher density of a semiconductor device on which a semiconductor chip is mounted.

半導体装置の小型化に伴い、多層配線基板の薄型化が進められている。薄型化が進められた多層配線基板として、たとえば、絶縁樹脂層と配線層とが交互に形成されたビルドアップ層を主体とし、コア基板を有さないコアレス基板が知られている（特許文献１参照）。   With the miniaturization of semiconductor devices, multilayer wiring boards are being made thinner. As a multilayer wiring board whose thickness has been reduced, for example, a coreless board that is mainly composed of a buildup layer in which insulating resin layers and wiring layers are alternately formed and does not have a core board is known (Patent Document 1). reference).

特開２００４−１８６２６５号公報JP 2004-186265 A

コアレス基板のように多層配線基板の薄型化が進むと、半導体装置の製造時または検査時において外部からの衝撃を受けたときに多層配線基板が損傷を受けやすくなる。多層配線基板の上に封止樹脂を成型したパッケージ構造であっても、多層配線基板の外形に比べて、封止樹脂の外形が小さく、多層配線基板の端部が封止樹脂からはみ出ている構造の場合には、多層配線基板の端部の損傷が問題となっている。このため、封止樹脂の外形と多層配線基板の外形とを合わせる構造が望まれている。しかし、基板単体での封止では、型ズレのため、封止樹脂の外形と多層配線基板の外形とを合わせることは困難である。   When the multilayer wiring board is made thinner like a coreless board, the multilayer wiring board is easily damaged when subjected to an impact from the outside during manufacturing or inspection of a semiconductor device. Even in a package structure in which a sealing resin is molded on a multilayer wiring board, the outer shape of the sealing resin is smaller than that of the multilayer wiring board, and the end of the multilayer wiring board protrudes from the sealing resin. In the case of the structure, damage to the end of the multilayer wiring board is a problem. For this reason, a structure that matches the outer shape of the sealing resin and the outer shape of the multilayer wiring board is desired. However, in sealing with a single substrate, it is difficult to match the outer shape of the sealing resin and the outer shape of the multilayer wiring board due to misalignment.

本発明はこうした課題に鑑みてなされたものであり、その目的は、薄型化された基板の端部における損傷を低減することが可能な半導体装置の製造方法の提供にある。   The present invention has been made in view of these problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing damage at an end portion of a thinned substrate.

本発明のある態様は、半導体装置の製造方法である。当該半導体装置の製造方法は、複数の基板にそれぞれ半導体チップを実装する実装工程と、半導体チップが実装された各基板の少なくとも１辺が他の基板の辺と接するように複数の基板を配設する配設工程と、複数の基板の上に形成されるべき封止樹脂層の外形より大きい領域にまで封止樹脂を成型し、隣接する基板同士を連結する封止工程と、各基板および各基板上の封止樹脂を所定の寸法に従って切断し、各基板を個片化する個片化工程と、を備えることを特徴とする。上記配設工程において、前記複数の基板を一方向に並置してもよい。   One embodiment of the present invention is a method for manufacturing a semiconductor device. The manufacturing method of the semiconductor device includes a mounting step of mounting semiconductor chips on a plurality of substrates, and disposing a plurality of substrates so that at least one side of each substrate on which the semiconductor chips are mounted is in contact with a side of another substrate A sealing step for molding the sealing resin to a region larger than the outer shape of the sealing resin layer to be formed on the plurality of substrates, and connecting adjacent substrates; And a separation step of cutting each sealing resin on the substrate according to a predetermined dimension to separate each substrate. In the arrangement step, the plurality of substrates may be juxtaposed in one direction.

この態様によれば、薄型化された基板の外形と封止樹脂の外形とを一致させることができるので、基板の端部に外力が加わる可能性を大幅に低減することができる。これにより、半導体装置の製造過程や検査工程において、基板の端部を損傷する可能性を低減し、半導体装置の製造歩留まりを向上させることができる。   According to this aspect, since the outer shape of the thinned substrate can be matched with the outer shape of the sealing resin, the possibility that an external force is applied to the end portion of the substrate can be greatly reduced. Thereby, in the manufacturing process and inspection process of the semiconductor device, the possibility of damaging the edge of the substrate can be reduced, and the manufacturing yield of the semiconductor device can be improved.

本発明によれば、半導体の製造過程において、薄型化された基板の端部における損傷を低減させることができる。   ADVANTAGE OF THE INVENTION According to this invention, the damage in the edge part of the board | substrate made thin can be reduced in the manufacture process of a semiconductor.

実施の形態に係る半導体装置の製造方法について図面を参照して説明する。   A method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings.

図１は、実施の形態に係る半導体装置の製造方法で用いる基板の構造を示す図である。基板２０は、層間絶縁膜と配線層とが交互に積層され、コア基板を有さない多層配線構造を有する。より具体的には、複数の配線層２２が層間絶縁膜２４を介して積層されている。配線層２２には、たとえば銅が用いられる。層が異なる配線層２２間は、層間絶縁膜２４に設けられたビアプラグ２６により電気的に接続されている。基板２０の裏面の配線層２２ａの周囲には、耐熱性に優れた樹脂材料からなるソルダーレジスト膜２８が形成され、基板２０にハンダ付けを行う際に、必要な箇所以外にハンダが付着しないように最下層の層間絶縁膜２４ａがコーティングされる。また、基板２０の裏面には、ＢＧＡボール５０が接合されるボールランド部２９がアレイ状に複数配設されている。各ボールランド部２９の表面には、有機表面保護コーティング材（ＯＳＰ）２１が被覆されている。一方、半導体チップが実装される側にあたる基板２０の表面には、電解メッキにより形成されたニッケル（Ｎｉ）、鉛（Ｐｄ）、金（Ａｕ）またはこれらの合金からなる電極パッド２５がアレイ状に複数配設され、各電極パッド２５の上に、錫、鉛またはこれらの合金からなるＣ４（Controlled Collapse Chip Connection）バンプ２７が設けられている。   FIG. 1 is a diagram showing a structure of a substrate used in a method for manufacturing a semiconductor device according to an embodiment. The substrate 20 has a multilayer wiring structure in which interlayer insulating films and wiring layers are alternately stacked and does not have a core substrate. More specifically, a plurality of wiring layers 22 are stacked via an interlayer insulating film 24. For example, copper is used for the wiring layer 22. The wiring layers 22 having different layers are electrically connected by via plugs 26 provided in the interlayer insulating film 24. A solder resist film 28 made of a resin material having excellent heat resistance is formed around the wiring layer 22a on the back surface of the substrate 20 so that when soldering to the substrate 20, the solder does not adhere to other than necessary portions. The lowermost interlayer insulating film 24a is coated. A plurality of ball land portions 29 to which the BGA balls 50 are bonded are arranged in an array on the back surface of the substrate 20. The surface of each ball land portion 29 is covered with an organic surface protective coating material (OSP) 21. On the other hand, electrode pads 25 made of nickel (Ni), lead (Pd), gold (Au), or alloys thereof are formed in an array on the surface of the substrate 20 on the side where the semiconductor chip is mounted. A plurality of C4 (Controlled Collapse Chip Connection) bumps 27 made of tin, lead, or an alloy thereof are provided on each electrode pad 25.

基板２０の製造方法は特に限定されず、周知のフォトリソグラフィ、エッチング、めっき、ラミネートなどの技術を組み合わせることにより実現され得る。コアレス基板を得る方法としては、銅などの金属板の上に層間絶縁膜と配線層電解とからなるビルドアップ層を形成した後、金属板をエッチングあるいは剥離する手法が挙げられる。   The manufacturing method of the board | substrate 20 is not specifically limited, It can implement | achieve by combining well-known techniques, such as photolithography, an etching, plating, and a lamination. As a method for obtaining a coreless substrate, there is a method in which a build-up layer composed of an interlayer insulating film and wiring layer electrolysis is formed on a metal plate such as copper and then the metal plate is etched or peeled off.

なお、基板２０の外形は、半導体装置用に予め定められた寸法より大きいものを用いる。たとえば、半導体装置に用いられる基板の寸法を４５ｍｍ角とした場合に、基板２０の各辺の長さを４５ｍｍより１ｍｍ程度大きく取る。   Note that the outer shape of the substrate 20 is larger than a predetermined dimension for a semiconductor device. For example, when the size of the substrate used in the semiconductor device is 45 mm square, the length of each side of the substrate 20 is set to be about 1 mm larger than 45 mm.

複数個の基板２０を用意し、図２（Ａ）に示すように、基板２０にＬＳＩ（大規模集積回路）などの半導体チップ３０の実装を行う。具体的には、半導体チップ３０の外部電極端子が設けられた表面をフェイスダウンにした状態で、各ハンダバンプ３２とそれらに対応するＣ４バンプ２７とをハンダ付けすることにより、半導体チップ３０をフリップチップ実装する。   A plurality of substrates 20 are prepared, and a semiconductor chip 30 such as an LSI (Large Scale Integrated Circuit) is mounted on the substrate 20 as shown in FIG. Specifically, in a state where the surface of the semiconductor chip 30 on which the external electrode terminals are provided is face-down, the solder bumps 32 and the corresponding C4 bumps 27 are soldered so that the semiconductor chip 30 is flip-chiped. Implement.

次に、図２（Ｂ）に示すように、半導体チップ３０と基板２０との間にアンダーフィル７０を充填する。これにより、ハンダ接合部分から生じるストレスが分散されるため、半導体装置１０の耐温度変化特性が改善されるとともに、半導体装置１０の反りが抑制される。   Next, as shown in FIG. 2B, an underfill 70 is filled between the semiconductor chip 30 and the substrate 20. As a result, stress generated from the solder joint portion is dispersed, so that the temperature resistance change characteristic of the semiconductor device 10 is improved and the warpage of the semiconductor device 10 is suppressed.

このような半導体チップ実装工程を複数個の基板についてそれぞれ行った後、図３（Ａ）および図３（Ｂ）に示すように、各基板２０の少なくとも１辺が他の基板２０の辺と接するように複数の基板２０を配設する。本実施の形態では、４個の基板２０を一方向に並置する。このとき、隣接する基板２０間で基板２０の上面の高さが一致していることが好ましい。   After performing such a semiconductor chip mounting process for each of the plurality of substrates, at least one side of each substrate 20 is in contact with the side of the other substrate 20 as shown in FIGS. 3 (A) and 3 (B). A plurality of substrates 20 are arranged as described above. In the present embodiment, four substrates 20 are juxtaposed in one direction. At this time, it is preferable that the height of the upper surface of the board | substrate 20 corresponds between the board | substrates 20 adjacent.

次に、図４（Ａ）および図４（Ｂ）に示すように、トランスファーモールド法により、並置された各基板２０の上に封止樹脂４０を成型する。このとき、トランスファーモールド装置で使用される上型は、各半導体装置の封止樹脂の設計形状に合う型ではなく、当該設計形状より大きいものを用いる。本実施の形態では、各半導体チップ３０の裏面が露出するように各半導体チップ３０の周囲に離間し、かつ、隣接する基板２０上の封止樹脂４０が連結するような上型を用いて、複数の基板２０上に封止樹脂をモールドする。モールドされる封止樹脂の形状を設計形状より大きくすることにより、設計領域内でフラッシュバリなどのバリが生じることを避けることができる。また、封止樹脂４０が硬化することにより各基板２０が連結されるため、複数の基板２０の集合体としてハンドリングすることができる。また、封止樹脂をインジェクションするためのゲートを製品領域外の基板の上に設けることができるため、特殊なモールド装置を開発する必要がなく、モールドに要する費用を安価にすることができる。   Next, as shown in FIGS. 4A and 4B, the sealing resin 40 is molded on the substrates 20 arranged in parallel by a transfer molding method. At this time, the upper mold used in the transfer mold apparatus is not a mold that matches the design shape of the sealing resin of each semiconductor device, but a mold larger than the design shape. In the present embodiment, using an upper mold that is separated from the periphery of each semiconductor chip 30 so that the back surface of each semiconductor chip 30 is exposed and the sealing resin 40 on the adjacent substrate 20 is connected, A sealing resin is molded on the plurality of substrates 20. By making the shape of the sealing resin to be molded larger than the design shape, it is possible to avoid the occurrence of burrs such as flash burrs in the design region. Moreover, since each board | substrate 20 is connected when the sealing resin 40 hardens | cures, it can handle as an aggregate | assembly of the some board | substrate 20. FIG. Further, since a gate for injecting the sealing resin can be provided on the substrate outside the product region, it is not necessary to develop a special molding apparatus, and the cost required for molding can be reduced.

次に、図５（Ａ）および図５（Ｂ）に示すように、ダイシング装置などの切削機械を用いて、所定の製品寸法に合わせて基板２０を個片化する。ダイシング加工により、各基板２０およびその上の封止樹脂４０について、製品寸法よりはみ出た部分Ｒが切除される。   Next, as shown in FIGS. 5A and 5B, using a cutting machine such as a dicing machine, the substrate 20 is separated into pieces in accordance with a predetermined product dimension. By the dicing process, the portion R protruding from the product size is cut out for each substrate 20 and the sealing resin 40 on the substrate 20.

各基板２０の個片化を行った後、図６に示すように、個々の基板２０に設けられたボールランド部２９（図１参照）にＢＧＡボール５０を実装する。以上の工程により、基板２０に半導体チップ３０がフリップチップ実装され、半導体チップ３０の周囲に離間した位置に封止樹脂４０が成型された半導体装置１０を得ることができる。より具体的には、半導体チップ３０に設けられたハンダバンプ３２とそれらに対応して基板２０に設けられたＣ４バンプ２７とがはんだ付けされ、半導体チップ３０と基板２０との間にアンダーフィル７０が充填されている。   After the individual substrates 20 are separated, the BGA balls 50 are mounted on the ball land portions 29 (see FIG. 1) provided on the individual substrates 20 as shown in FIG. Through the above steps, it is possible to obtain the semiconductor device 10 in which the semiconductor chip 30 is flip-chip mounted on the substrate 20 and the sealing resin 40 is molded at a position apart from the periphery of the semiconductor chip 30. More specifically, the solder bumps 32 provided on the semiconductor chip 30 and the corresponding C4 bumps 27 provided on the substrate 20 are soldered, and an underfill 70 is formed between the semiconductor chip 30 and the substrate 20. Filled.

以上説明した半導体装置の製造方法によれば、薄型化された基板の外形と封止樹脂の外形とを一致させることができるので、基板の端部に外力が加わる可能性を大幅に低減することができる。これにより、半導体装置の製造過程や検査工程において、基板の端部を損傷する可能性を低減し、半導体装置の製造歩留まりを向上させることができる。   According to the semiconductor device manufacturing method described above, the outer shape of the thinned substrate and the outer shape of the sealing resin can be matched, so that the possibility of external force being applied to the end portion of the substrate is greatly reduced. Can do. Thereby, in the manufacturing process and inspection process of the semiconductor device, the possibility of damaging the edge of the substrate can be reduced, and the manufacturing yield of the semiconductor device can be improved.

また、モールド時に設計形状より大きな封止樹脂が基板に成型されているため、基板上にモールドによるフラッシュバリが生じる可能性がある箇所は製品領域の外側となる。製品領域の外側は、ダイシングなどにより切除させるため、製品して得られる半導体装置上にフラッシュバリが残らない。これにより、半導体装置の製品の品質を向上させることができる。   In addition, since a sealing resin larger than the design shape is molded on the substrate at the time of molding, a portion where flash burrs due to molding may occur on the substrate is outside the product region. Since the outside of the product region is cut away by dicing or the like, flash burrs do not remain on the semiconductor device obtained as a product. Thereby, the quality of the product of the semiconductor device can be improved.

なお、半導体装置を封止樹脂を用いてパッケージ化する方法は、モールド装置を用いて、キャビティに導入された封止樹脂を熱硬化させる手法に限られない。たとえば、モールド装置での熱硬化を最後まで行わず、途中から図７に示すような、簡便な構造の熱硬化装置を用いて熱硬化処理を完了させてもよい。   Note that the method of packaging the semiconductor device using the sealing resin is not limited to the method of thermally curing the sealing resin introduced into the cavity using a molding device. For example, the thermosetting process may be completed by using a thermosetting apparatus having a simple structure as shown in FIG.

熱硬化装置１００は、下側プレート１１０、上側プレート１２０、加圧手段（図示せず）および加熱手段（図示せず）を備える。下側プレート１１０は、半導体装置の基板２０の下面と接する平面を有する。一方、上側プレート１２０は、半導体装置の封止樹脂４０の上面と接する平面を有する。下側プレート１１０および上側プレート１２０には、それぞれヒータなどの加熱手段が設けられており、下側プレート１１０および上側プレート１２０は、加熱手段により半導体装置に用いられる封止樹脂４０の硬化温度に加熱される。また、下側プレート１１０と上側プレート１２０との間に狭持された複数の基板２０の集合体は、加圧手段により所定の圧力で押圧される。このような熱硬化装置１００を用いることにより、所定の温度に加熱された下側プレート１１０と上側プレート１２０との間に複数の基板２０の集合体を保持し、反りを押さえながら、封止樹脂４０の硬化を完了させることができる。   The thermosetting device 100 includes a lower plate 110, an upper plate 120, a pressurizing unit (not shown), and a heating unit (not shown). The lower plate 110 has a plane in contact with the lower surface of the substrate 20 of the semiconductor device. On the other hand, the upper plate 120 has a plane in contact with the upper surface of the sealing resin 40 of the semiconductor device. The lower plate 110 and the upper plate 120 are each provided with heating means such as a heater, and the lower plate 110 and the upper plate 120 are heated to the curing temperature of the sealing resin 40 used in the semiconductor device by the heating means. Is done. In addition, the aggregate of the plurality of substrates 20 held between the lower plate 110 and the upper plate 120 is pressed with a predetermined pressure by the pressing means. By using such a thermosetting device 100, an assembly of a plurality of substrates 20 is held between the lower plate 110 and the upper plate 120 heated to a predetermined temperature, and the sealing resin is pressed while suppressing warpage. 40 cures can be completed.

上述した熱硬化装置を用いて半導体装置をパッケージ化する手順について図８（Ａ）を用いて説明する。パッケージ化する複数の基板の集合体（以下、基板集合体という）を順にＰ１，Ｐ２，Ｐ３・・・とする。所定の硬化温度で硬化までに要する時間を標準硬化時間Ｔ１とする。まず、基板集合体Ｐ１について、モールド装置による熱硬化をＴ１の半分の時間（１／２×Ｔ１）まで行う。この後、基板集合体Ｐ１を熱硬化装置に設置するとともに、次にパッケージ化すべき基板集合体Ｐ２をモールド装置に設置する。続いて、基板集合体Ｐ１を熱硬化装置による熱硬化をＴ１の半分の時間（１／２×Ｔ１）まで行うとともに、基板集合体Ｐ２について、モールド装置による熱硬化をＴ１の半分の時間（１／２×Ｔ１）まで行う。すなわち、異なる基板集合体について、モールド装置による熱硬化と、熱硬化装置による熱硬化とを並行して行う。これによれば、図８（Ｂ）のように、モールド装置のみを用いて、基板集合体を順にパッケージ化した場合に要する時間に比べて、パッケージ化に要する時間を半減することができ、半導体装置の生産性向上を図ることができる。なお、モールド装置に比べて熱硬化装置は構造が簡便なため、比較的安価であり、モールド装置を２台保有する場合に比べて投資に要する費用を抑えることができる。   A procedure for packaging a semiconductor device using the above-described thermosetting apparatus will be described with reference to FIG. Assume that an assembly of a plurality of substrates to be packaged (hereinafter referred to as a substrate assembly) is P1, P2, P3. The time required for curing at a predetermined curing temperature is defined as a standard curing time T1. First, the substrate assembly P1 is thermally cured by a molding apparatus until half the time T1 / 2 (1/2 × T1). Thereafter, the substrate assembly P1 is installed in the thermosetting device, and the substrate assembly P2 to be packaged next is installed in the molding device. Subsequently, the substrate assembly P1 is thermally cured by the thermosetting device until half the time T1 / 2 (1/2 × T1), and the substrate assembly P2 is thermally cured by the molding device for half the time T1 (1). / 2 × T1). That is, for different substrate aggregates, thermosetting by the mold apparatus and thermosetting by the thermosetting apparatus are performed in parallel. According to this, as shown in FIG. 8B, the time required for packaging can be halved as compared with the time required for packaging the substrate aggregate in order using only the molding apparatus. The productivity of the apparatus can be improved. In addition, since the thermosetting apparatus has a simple structure as compared with the molding apparatus, it is relatively inexpensive, and the cost required for investment can be suppressed as compared with the case where two molding apparatuses are provided.

より具体的には、封止樹脂としてＴ１が６０秒の従来型のエポキシ樹脂を用いた場合には、基板集合体１つ当たりに要する熱硬化処理でのワークタイムを約３０秒とすることができる。また、従来型に比べて長いＴ１必要な場合であっても、熱硬化処理でのワークタイムを半減させることができる。たとえば、Ｔ１が１２０秒の場合には、基板集合体１つ当たりに要する熱硬化処理でのワークタイムを約６０秒とすることができる。   More specifically, when a conventional epoxy resin having a T1 of 60 seconds is used as the sealing resin, the work time in the thermosetting process required for each substrate assembly may be about 30 seconds. it can. Further, even when T1 longer than that of the conventional type is required, the work time in the thermosetting process can be halved. For example, when T1 is 120 seconds, the work time in the thermosetting process required for each substrate assembly can be set to about 60 seconds.

なお、熱硬化装置１００の下側プレート１１０または／および上側プレート１２０において、基板集合体の反り特性に合わせて、基板集合体と接する面を反りを矯正するような形状としてもよい。これによれば、基板集合体の反りをより抑制することができる。   In addition, in the lower plate 110 and / or the upper plate 120 of the thermosetting device 100, the surface in contact with the substrate assembly may be shaped so as to correct the warp in accordance with the warp characteristics of the substrate assembly. According to this, the curvature of a board | substrate assembly can be suppressed more.

また、上述したパッケージ化の手順では、Ｔ１を２分割としているが、熱硬化装置を２台以上用いることにより、Ｔ１を３分割以上とし、モールド装置と複数の熱硬化装置を含む３カ所以上で熱硬化処理を並行的に行ってもよい。   Moreover, in the packaging procedure described above, T1 is divided into two parts. However, by using two or more thermosetting devices, T1 is divided into three or more parts at three or more locations including a molding device and a plurality of thermosetting devices. You may perform a thermosetting process in parallel.

本発明は、上述の実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本発明の範囲に含まれうるものである。   The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. Embodiments to which such modifications are added Can also be included in the scope of the present invention.

たとえば、図２（Ａ）において、半導体チップ３０が基板２０にフリップチップ接続されているが、半導体チップ３０は、ワイヤボンディングにより基板２０と電気的に接続されていてもよい。   For example, in FIG. 2A, the semiconductor chip 30 is flip-chip connected to the substrate 20, but the semiconductor chip 30 may be electrically connected to the substrate 20 by wire bonding.

また、図３（Ａ）および図３（Ｂ）において、複数の基板２０が一方向に並置されているが、複数の基板２０を縦横の２次元配列としてもよい。   3A and 3B, the plurality of substrates 20 are juxtaposed in one direction. However, the plurality of substrates 20 may be two-dimensionally arranged vertically and horizontally.

また、図４（Ａ）および図４（Ｂ）において、封止樹脂４０が各半導体チップ３０の周囲に設けられ、各半導体チップ３０の裏面が露出しているが、封止樹脂の４０の形状は任意であり、封止樹脂４０により各半導体チップ３０の全体が被覆されていてもよい。   4A and 4B, the sealing resin 40 is provided around each semiconductor chip 30 and the back surface of each semiconductor chip 30 is exposed. Is optional, and the entire semiconductor chip 30 may be covered with the sealing resin 40.

半導体装置の製造に用いる基板の構造を示す図である。It is a figure which shows the structure of the board | substrate used for manufacture of a semiconductor device. 半導体チップの実装工程を示す断面図である。It is sectional drawing which shows the mounting process of a semiconductor chip. 図３（Ａ）は、基板を載置する工程を示す平面図である。図３（Ｂ）は、図３（Ａ）のＡ−Ａ’線上の断面図である。FIG. 3A is a plan view showing a step of placing a substrate. FIG. 3B is a cross-sectional view taken along line A-A ′ of FIG. 図４（Ａ）は、モールド工程を示す平面図である。図４（Ｂ）は、図４（Ａ）のＡ−Ａ’線上の断面図である。FIG. 4A is a plan view showing a molding process. FIG. 4B is a cross-sectional view taken along line A-A ′ of FIG. 図５（Ａ）は、基板の個片化工程を示す平面図である。図５（Ｂ）は、図５（Ａ）のＡ−Ａ’線上の断面図である。FIG. 5A is a plan view showing a substrate dividing step. FIG. 5B is a cross-sectional view taken along line A-A ′ of FIG. はんだボール実装工程を示す図である。It is a figure which shows a solder ball mounting process. 簡便な構造の熱硬化装置による成型樹脂層の形成方法を示す図であるIt is a figure which shows the formation method of the molding resin layer by the thermosetting apparatus of a simple structure 図８（Ａ）は、熱硬化装置を用いて半導体装置の成型樹脂層を硬化する手順を示す図である。図８（Ｂ）は、モールド装置のみを用いて半導体装置の成型樹脂層を硬化する手順を示す図である。FIG. 8A is a diagram illustrating a procedure of curing a molded resin layer of a semiconductor device using a thermosetting device. FIG. 8B is a diagram illustrating a procedure for curing the molding resin layer of the semiconductor device using only the molding apparatus.

符号の説明Explanation of symbols

１０ 半導体装置、２０ 基板、３０ 半導体チップ、４０ 封止樹脂、５０ ＢＧＡボール、７０ アンダーフィル。   10 semiconductor device, 20 substrate, 30 semiconductor chip, 40 sealing resin, 50 BGA ball, 70 underfill.

Claims (2)

複数の基板にそれぞれ半導体チップを実装する実装工程と、
前記半導体チップが実装された各基板の少なくとも１辺が他の基板の辺と接するように前記複数の基板を配設する配設工程と、
前記複数の基板の上に形成されるべき封止樹脂層の外形より大きい領域にまで封止樹脂を成型し、隣接する基板同士を連結する封止工程と、
各基板および各基板上の封止樹脂を所定の寸法に従って切断し、各基板を個片化する個片化工程と、
を備えることを特徴とする半導体装置の製造方法。 A mounting process for mounting a semiconductor chip on each of a plurality of substrates;
Disposing the plurality of substrates such that at least one side of each substrate on which the semiconductor chip is mounted is in contact with a side of another substrate;
A sealing step of molding the sealing resin to a region larger than the outer shape of the sealing resin layer to be formed on the plurality of substrates, and connecting adjacent substrates;
Each substrate and the sealing resin on each substrate are cut according to predetermined dimensions, and each substrate is separated into individual pieces,
A method for manufacturing a semiconductor device, comprising: 前記配設工程において、前記複数の基板を一方向に並置することを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the arranging step, the plurality of substrates are juxtaposed in one direction.
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