JPH11297750A - Semiconductor device, manufacture thereof, and mounting of the semiconductor device - Google Patents

Semiconductor device, manufacture thereof, and mounting of the semiconductor device

Info

Publication number
JPH11297750A
JPH11297750A JP10095639A JP9563998A JPH11297750A JP H11297750 A JPH11297750 A JP H11297750A JP 10095639 A JP10095639 A JP 10095639A JP 9563998 A JP9563998 A JP 9563998A JP H11297750 A JPH11297750 A JP H11297750A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor
semiconductor device
electrode
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10095639A
Other languages
Japanese (ja)
Other versions
JP3417292B2 (en
Inventor
Ryuichi Sawara
隆一 佐原
Takayuki Yoshida
隆幸 吉田
Nozomi Shimoishizaka
望 下石坂
Yoshifumi Nakamura
嘉文 中村
Takahiro Kumagawa
隆博 隈川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9563998A priority Critical patent/JP3417292B2/en
Publication of JPH11297750A publication Critical patent/JPH11297750A/en
Application granted granted Critical
Publication of JP3417292B2 publication Critical patent/JP3417292B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PROBLEM TO BE SOLVED: To relax thermal stresses caused by non-matching thermal linear expansion coefficients between a semiconductor element and a circuit substrate, by noting the productivity of a semiconductor device, enabling its repair and providing a thermoplastic resin layer on a semiconductor element, without providing encapsulating resin. SOLUTION: In this semiconductor device, a metal layer 10 is provided on a semiconductor element electrode 9 on a semiconductor element 8, a bump 11 is provided on the metal layer 10, and a thermoplastic resin layer 12 is formed in regions other than the region of the semiconductor element electrode 9. As a result of such a structure, at reflowing for mounting, the resin 12 is melted and then set, whereby the bonding between a semiconductor device and a circuit substrate can be made firm and stresses generated in the bump 11 can be relaxed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体の集積回路
部を保護し、かつ外部装置と半導体素子の電気的な接続
を確保し、さらにもっとも高密度な実装を可能とした半
導体装置およびその製造方法に関するものである。ま
た、本発明の半導体装置により、情報通信機器、事務用
電子機器等の小型化を容易にするものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor, secures an electrical connection between an external device and a semiconductor element, and enables the highest density mounting, and its manufacture. It is about the method. Further, the semiconductor device of the present invention facilitates miniaturization of information communication equipment, office electronic equipment, and the like.

【0002】[0002]

【従来の技術】近年、半導体装置は電子機器の小型化、
高機能化に伴い、小型化、高密度化、高速化を要求され
るようになり、それにともなって例えばC4(Cont
rolled Collapse Chip Conn
ection)あるいはSBB(Stud Bump
Bonding)といったいわゆるフリップチップボン
ディングを用いた実装技術が開発されている。また半導
体パッケージにおいては半導体素子の大きさに限りなく
近いCSP(Chip Size Package)と
いった小型の半導体パッケージ製品が開発されている。
2. Description of the Related Art In recent years, semiconductor devices have become smaller in electronic equipment.
With the advancement of functions, miniaturization, high density, and high speed are required, and accordingly, for example, C4 (Cont.
rolled Collapse Chip Conn
section) or SBB (Stud Bump)
Bonding), a mounting technique using so-called flip chip bonding has been developed. In the field of semiconductor packages, small-sized semiconductor package products such as CSP (Chip Size Package), which are as close as possible to the size of a semiconductor element, have been developed.

【0003】以下、従来のSBBと称される実装技術を
用いた半導体装置およびその製造方法について、図面を
参照しながら説明する。
Hereinafter, a semiconductor device using a conventional mounting technique called SBB and a method of manufacturing the same will be described with reference to the drawings.

【0004】図6は、従来のSBB工法を用いた半導体
装置を示す断面図である。図6において、1は半導体素
子、2は半導体素子電極、3はバンプ、4は導電性接着
剤、5は回路基板、6は回路基板ランド、7は封止樹脂
である。
FIG. 6 is a sectional view showing a semiconductor device using a conventional SBB method. In FIG. 6, 1 is a semiconductor element, 2 is a semiconductor element electrode, 3 is a bump, 4 is a conductive adhesive, 5 is a circuit board, 6 is a circuit board land, and 7 is a sealing resin.

【0005】図6に示すように、従来の半導体装置は、
半導体素子1上の半導体素子電極2上にバンプ3が形成
され、そのバンプ3が導電性接着剤4を介して回路基板
5の回路基板ランド6(電極)に接続されているもので
あり、半導体素子1と回路基板5との間隔は封止樹脂7
が充填封止されている構造である。
[0005] As shown in FIG.
A bump 3 is formed on a semiconductor element electrode 2 on a semiconductor element 1, and the bump 3 is connected to a circuit board land 6 (electrode) of a circuit board 5 via a conductive adhesive 4. The distance between the element 1 and the circuit board 5 is determined by the sealing resin 7.
Are filled and sealed.

【0006】次に従来の半導体装置の製造方法について
同様に図6の断面図を参照しながら説明する。
Next, a conventional method of manufacturing a semiconductor device will be described with reference to the sectional view of FIG.

【0007】まず半導体素子1上の半導体素子電極2上
にSBB工法として、ボールボンディング法を用いてバ
ンプ3を形成する。次に導電性接着剤4を形成したバン
プ3の先端部に転写法により形成する。次に位置合わせ
を行い、バンプ3と回路基板5上の回路基板ランド6上
に搭載する。導電性接着剤4の熱硬化後、半導体素子1
と回路基板5との間隙に封止樹脂7を注入して充填し、
熱硬化させる。封止樹脂7の作用は半導体素子1の保護
および半導体素子1と回路基板5との熱線膨張係数の不
一致によるバンプ3、導電性接着剤4にかかる熱ストレ
スの緩和である。以上のような工法により従来の半導体
装置が製造されるものである。
First, bumps 3 are formed on a semiconductor element electrode 2 on a semiconductor element 1 by a ball bonding method as an SBB method. Next, the conductive adhesive 4 is formed on the tip of the bump 3 by the transfer method. Next, alignment is performed, and the bump 3 and the circuit board land 6 on the circuit board 5 are mounted. After the thermosetting of the conductive adhesive 4, the semiconductor element 1
The sealing resin 7 is injected and filled in the gap between the circuit board 5 and
Heat cured. The function of the sealing resin 7 is to protect the semiconductor element 1 and to alleviate the thermal stress applied to the bump 3 and the conductive adhesive 4 due to the mismatch in the coefficient of linear thermal expansion between the semiconductor element 1 and the circuit board 5. A conventional semiconductor device is manufactured by the above-described method.

【0008】[0008]

【発明が解決しようとする課題】しかしながら前記従来
の方法では、半導体素子と回路基板との間隙が狭く、封
止樹脂の注入が非常に困難であり、また個々の半導体素
子を個別に封止するため、生産性が悪いという課題を有
していた。さらに樹脂封止後、半導体素子の故障、不良
が発見された場合、封止樹脂と回路基板との密着が強固
なため故障、不良のあった半導体素子を回路基板から取
り外すのは困難であり、仮に取り外せた場合であっても
回路基板を損傷させてしまうため、その回路基板への半
導体素子の再搭載は不可能であり、生産性、生産コスト
性上の課題があった。
However, in the above-mentioned conventional method, the gap between the semiconductor element and the circuit board is narrow, it is very difficult to inject the sealing resin, and the individual semiconductor elements are individually sealed. Therefore, there is a problem that productivity is poor. Furthermore, if a failure or defect of the semiconductor element is found after resin sealing, it is difficult to remove the defective or defective semiconductor element from the circuit board because the adhesion between the sealing resin and the circuit board is strong. Even if it can be removed, the circuit board will be damaged, so it is impossible to remount the semiconductor element on the circuit board, and there has been a problem in productivity and production cost.

【0009】本発明は前記従来の課題を解決するもの
で、半導体装置の生産性に着目し、またリペアを可能と
して、封止樹脂を設けず半導体素子上に熱可塑性樹脂層
を設けることで半導体素子と回路基板との熱線膨張係数
の不一致による熱ストレスを緩和できる半導体装置およ
びその製造方法を提供することを目的とする。
The present invention solves the above-mentioned conventional problems, and focuses on the productivity of a semiconductor device, enables repair, and provides a thermoplastic resin layer on a semiconductor element without providing a sealing resin. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can relieve thermal stress caused by a mismatch in the coefficient of linear thermal expansion between an element and a circuit board.

【0010】[0010]

【課題を解決するための手段】前記課題を解決するため
に、本発明の半導体装置は、半導体素子と、前記半導体
素子の電極上に形成された金属層と、前記金属層以外の
半導体素子表面の領域に形成された熱可塑性樹脂層とよ
りなるものである。また、半導体素子と、前記半導体素
子の電極上に形成された金属層と、前記金属層上に形成
された突起電極と、前記突起電極以外の半導体素子表面
の領域に形成された熱可塑性樹脂層とよりなる半導体装
置である。また、回路基板と、前記回路基板上に搭載さ
れた半導体素子と、前記回路基板の配線と前記半導体素
子とを電気的に接続した接続手段と、前記回路基板上の
半導体素子の外囲を封止した樹脂と、前記回路基板の底
面に設けられた突起電極とを有する半導体装置であっ
て、前記回路基板の底面に設けられた突起電極と突起電
極との間の回路基板底面には熱可塑性樹脂が設けられて
いる半導体装置である。また、リードフレームの支持部
に搭載された半導体素子と、前記半導体素子とインナー
リード部とを電気的に接続した接続手段と、前記インナ
ーリード部の底面側を露出させて前記半導体素子の外囲
を封止した封止樹脂とよりなる半導体装置であって、前
記封止樹脂より露出した前記インナーリード部面はアウ
ターリード部を構成し、前記アウターリード部とアウタ
ーリード部との間には熱可塑性樹脂が形成されている半
導体装置である。
In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a semiconductor element, a metal layer formed on an electrode of the semiconductor element, and a surface of the semiconductor element other than the metal layer. And a thermoplastic resin layer formed in the region. Further, the semiconductor element, a metal layer formed on the electrode of the semiconductor element, a protruding electrode formed on the metal layer, and a thermoplastic resin layer formed in a region of the semiconductor element surface other than the protruding electrode And a semiconductor device comprising: Further, a circuit board, a semiconductor element mounted on the circuit board, connection means for electrically connecting a wiring of the circuit board and the semiconductor element, and an outer periphery of the semiconductor element on the circuit board are sealed. A semiconductor device having a fixed resin and a protruding electrode provided on the bottom surface of the circuit board, wherein the bottom surface of the circuit board between the protruding electrode provided on the bottom surface of the circuit board and the This is a semiconductor device provided with a resin. A semiconductor element mounted on the support portion of the lead frame; connecting means for electrically connecting the semiconductor element to the inner lead portion; and an outer periphery of the semiconductor element by exposing a bottom surface side of the inner lead portion. A semiconductor device comprising a sealing resin sealing the inner lead portion, wherein the inner lead portion surface exposed from the sealing resin constitutes an outer lead portion, and heat is applied between the outer lead portion and the outer lead portion. This is a semiconductor device on which a plastic resin is formed.

【0011】また半導体装置の製造方法においては、半
導体素子上の半導体素子電極上全面に金属層を形成し、
前記半導体素子電極に相当する位置を露出させ、半導体
素子電極上に金属層を形成する工程と、前記半導体素子
電極上の金属層上に突起電極を形成する工程と、前記半
導体素子の突起電極を形成した面側に柔軟性シートを覆
い、金型内に保持し、熱可塑性樹脂を半導体素子と柔軟
性シートとの間隙に封入する工程と、金型内から半導体
素子を取り出し、柔軟性シートを剥離して、熱可塑性樹
脂を半導体素子の突起電極以外の領域に形成する工程と
よりなる半導体装置の製造方法である。
In the method of manufacturing a semiconductor device, a metal layer is formed on the entire surface of the semiconductor element electrode on the semiconductor element.
Exposing a position corresponding to the semiconductor element electrode, forming a metal layer on the semiconductor element electrode, forming a projecting electrode on the metal layer on the semiconductor element electrode, and projecting the projecting electrode of the semiconductor element. A step of covering the flexible sheet on the formed surface side, holding the flexible sheet in a mold, enclosing the thermoplastic resin in a gap between the semiconductor element and the flexible sheet, and taking out the semiconductor element from the mold and removing the flexible sheet. Forming a thermoplastic resin in a region other than the protruding electrodes of the semiconductor element by peeling off the semiconductor resin.

【0012】また、半導体装置の実装方法としては、半
導体装置を基板に実装する半導体装置の実装方法であっ
て、半導体装置として、半導体素子と、前記半導体素子
の電極上に形成された金属層と、前記金属層上に形成さ
れた突起電極と、前記突起電極以外の半導体素子表面の
領域に形成された熱可塑性樹脂層とよりなる半導体装置
を用い、前記半導体装置を前記熱可塑性樹脂面を基板に
対向させ、前記半導体装置のバンプと基板上の電極とを
位置合わせして搭載し、加熱処理して前記半導体装置の
突起電極を溶融させて前記基板の電極と接続するととも
に、前記加熱処理により半導体装置の熱可塑性樹脂を溶
融、硬化させて半導体装置と基板とを接続させる半導体
装置の実装方法である。
A method of mounting a semiconductor device is a method of mounting a semiconductor device on a substrate, wherein the semiconductor device includes a semiconductor element and a metal layer formed on an electrode of the semiconductor element. A semiconductor device comprising a protruding electrode formed on the metal layer and a thermoplastic resin layer formed in a region on the surface of the semiconductor element other than the protruding electrode; The bumps of the semiconductor device and the electrodes on the substrate are aligned and mounted, and heated to melt the protruding electrodes of the semiconductor device and connect to the electrodes of the substrate. This is a method of mounting a semiconductor device in which a thermoplastic resin of the semiconductor device is melted and cured to connect the semiconductor device and a substrate.

【0013】前記構成により、本発明の半導体装置は、
熱可塑性樹脂を用いているので、回路基板に半導体素子
を接合した後、加熱処理するだけで半導体素子と回路基
板との間隔を封止することができ、また複数の半導体素
子に対して同時に加熱することにより、生産性を向上さ
せて樹脂封止することができる。特に目的に応じて熱可
塑性樹脂の種類を半導体素子の品種ごとに変えるような
場合は、品種ごとに対応して半導体素子を加熱処理して
樹脂封止できるので、将来的な多品種生産に対しては非
常に効果が大きい。また、熱可塑性樹脂を用いているの
で、半導体素子に欠陥、不良が発見された場合には、加
熱処理することで、回路基板を破壊したり、基板に損傷
を与えることなく、回路基板から半導体素子を容易に取
り外すことができるため、生産性、生産コスト的にも有
利である。
With the above configuration, the semiconductor device of the present invention has
Since a thermoplastic resin is used, the gap between the semiconductor element and the circuit board can be sealed simply by heating after joining the semiconductor element to the circuit board, and heating of multiple semiconductor elements simultaneously. By doing so, it is possible to improve productivity and perform resin sealing. In particular, when the type of thermoplastic resin is changed for each type of semiconductor element according to the purpose, the semiconductor element can be heat-treated and sealed with resin for each type of product. Is very effective. In addition, since a thermoplastic resin is used, if a defect or defect is found in a semiconductor element, the semiconductor element can be removed from the circuit board by heat treatment without destroying or damaging the circuit board. Since the element can be easily removed, it is advantageous in terms of productivity and production cost.

【0014】また本発明は単に熱可塑性樹脂を半導体素
子の表面に対して、表面保護用として設けたものではな
く、後々の回路基板への実装等の基板と半導体装置との
接着、生産性を考慮し、実装時のリフロー加熱によって
熱可塑性樹脂が溶融し、そして硬化する性質を基板実装
に効果的に適用したものであり、フリップチップ実装技
術における封止樹脂による樹脂封止に代わる技術を提供
するものである。
Further, the present invention does not merely provide a thermoplastic resin on the surface of a semiconductor element for surface protection, but also enhances adhesion and productivity between a substrate and a semiconductor device for later mounting on a circuit board. Considering the fact that the thermoplastic resin melts and hardens due to reflow heating during mounting, it is effectively applied to board mounting, providing a technology that replaces resin sealing with sealing resin in flip chip mounting technology Is what you do.

【0015】[0015]

【発明の実施の形態】以下、本発明の実施形態について
図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0016】図1は本発明の第1の実施形態における半
導体装置を示す断面図である。図1に示すように本実施
形態の半導体装置は、半導体素子8上の半導体素子電極
9上に金属層10が設けられ、その金属層10上に突起
電極としてバンプ11が形成されているものである。そ
して半導体素子8の半導体素子電極9領域以外の領域に
は熱可塑性樹脂層12が形成されているものである。
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the present embodiment has a metal layer 10 provided on a semiconductor element electrode 9 on a semiconductor element 8 and a bump 11 formed on the metal layer 10 as a protruding electrode. is there. The thermoplastic resin layer 12 is formed in a region other than the region of the semiconductor device electrode 9 of the semiconductor device 8.

【0017】本実施形態において、半導体素子電極9上
に設けた金属層10としては、Ti(チタン)を密着金
属、Cu(銅)を拡散防止金属として用いた2層構造を
有した金属層を用いている。なお、金属材料としてはT
i(チタン)、Cr(クロム)、TiW(チタン・タン
グステン)、Cu(銅)、Ni(ニッケル)、Au
(金)、Pd(パラジウム)などを用いても構わない
し、それぞれの金属の組み合わせでも構わない。また、
バンプ11としては、Sn(スズ)、Pb(鉛)、Sn
(スズ)、Ag(銀)、Cu(銅)とPb(鉛)の合
金、Au(金)などである。
In this embodiment, as the metal layer 10 provided on the semiconductor element electrode 9, a metal layer having a two-layer structure using Ti (titanium) as an adhesion metal and Cu (copper) as a diffusion preventing metal is used. Used. The metal material is T
i (titanium), Cr (chromium), TiW (titanium / tungsten), Cu (copper), Ni (nickel), Au
(Gold), Pd (palladium) or the like may be used, or a combination of the respective metals may be used. Also,
As the bump 11, Sn (tin), Pb (lead), Sn
(Tin), Ag (silver), an alloy of Cu (copper) and Pb (lead), and Au (gold).

【0018】以上のように構成された本実施形態の半導
体装置について、以下その製造方法を図2を参照しなが
ら説明する。
A method of manufacturing the semiconductor device of the present embodiment having the above-described configuration will be described below with reference to FIG.

【0019】まず図2(a)には、個々の半導体素子が
形成された半導体ウェハ13を示しており、半導体素子
電極9が形成されている。
FIG. 2A shows a semiconductor wafer 13 on which individual semiconductor elements are formed, on which semiconductor element electrodes 9 are formed.

【0020】次に図2(b)に示すように、真空蒸着
法、スパッタリング法、CVD法あるいは無電解めっき
法により、半導体ウェハ13上に形成された半導体素子
の半導体素子電極9上全面に金属層10を形成する。こ
こで金属層10の一例としては、Ti(チタン)とCu
(銅)の組み合わせによる金属層を用いる。また金属材
料としてはTi(チタン)、Cr(クロム)、TiW
(チタン・タングステン)、Cu(銅)、Ni(ニッケ
ル)、Au(金)、Pd(パラジウム)などの金属を用
いても構わないし、それぞれの金属の組み合わせでも構
わない。次に感光性レジストを塗布し、乾燥、露光、現
像することにより、半導体素子電極9に相当する位置を
露出させる。
Next, as shown in FIG. 2B, metal is formed on the entire surface of the semiconductor element electrode 9 of the semiconductor element formed on the semiconductor wafer 13 by vacuum evaporation, sputtering, CVD or electroless plating. The layer 10 is formed. Here, as an example of the metal layer 10, Ti (titanium) and Cu
A metal layer using a combination of (copper) is used. As the metal material, Ti (titanium), Cr (chromium), TiW
Metals such as (titanium / tungsten), Cu (copper), Ni (nickel), Au (gold), and Pd (palladium) may be used, or a combination of these metals may be used. Next, a position corresponding to the semiconductor element electrode 9 is exposed by applying a photosensitive resist, drying, exposing, and developing.

【0021】次に例えば、電解めっきを用いてバンプ金
属層、例えばSn(スズ)とPb(鉛)を形成する。バ
ンプ金属層を形成後、レジストを溶融除去する。そして
バンプ金属層を溶解せず、金属層10の材料を選択的に
溶かすことのできるエッチング剤に浸し、バンプ金属層
以外の金属層を溶解除去し、フラックスを塗布後、溶融
することにより、図2(c)に示すように、バンプ11
を形成する。
Next, for example, a bump metal layer, for example, Sn (tin) and Pb (lead) is formed by using electrolytic plating. After forming the bump metal layer, the resist is melted and removed. Then, without dissolving the bump metal layer, the material of the metal layer 10 is immersed in an etchant capable of selectively dissolving, the metal layer other than the bump metal layer is dissolved and removed, and the flux is applied and then melted. As shown in FIG.
To form

【0022】また半導体素子電極9上にバンプ金属層を
形成するのではなく、あらかじめ金属層を写真法を用い
て所望のパターンを形成し、半導体素子電極9以外の位
置の半導体素子上に半導体素子電極9と電気的に接続す
るランドを形成する。次にめっきレジストを塗布し、写
真技術を用いてランド部のみを露出させ、電解めっきを
用いてバンプ金属層を形成してもよい。バンプ金属層を
形成した面にフラックスを塗布し、バンプ金属層を溶融
することでバンプ11を形成する。なお、バンプ11を
形成する方法としては、上記した方法に限定するもので
はなく、ワイヤーボンダーを用いたボールボンディング
法を用いてスタッドバンプを生成してもよく、この場
合、バンプの材質はAu(金)、Cu(銅)、Sn(ス
ズ)といった金属である。
Instead of forming a bump metal layer on the semiconductor element electrode 9, a desired pattern is formed on the metal layer in advance by using a photographic method, and the semiconductor element is formed on the semiconductor element at a position other than the semiconductor element electrode 9. A land electrically connected to the electrode 9 is formed. Next, a plating resist may be applied, only the lands may be exposed using photographic technology, and a bump metal layer may be formed using electrolytic plating. A flux is applied to the surface on which the bump metal layer is formed, and the bump 11 is formed by melting the bump metal layer. The method for forming the bump 11 is not limited to the above-described method, and a stud bump may be generated using a ball bonding method using a wire bonder. In this case, the material of the bump is Au ( Gold), Cu (copper) and Sn (tin).

【0023】次にバンプ11を形成した半導体ウェハ1
3のバンプ11を形成した面側に柔軟性シート(図示せ
ず)を覆い、金型内に保持する。熱可塑性樹脂を射出成
形技術により半導体ウェハ13と柔軟性シートとの間隙
に封入する。封入後、金型内から半導体ウェハ13を取
り出し、柔軟性シートを剥離することにより、図2
(d)に示すように、熱可塑性樹脂12を半導体ウェハ
13のバンプ11以外の領域に形成することができる。
熱可塑性樹脂封入の間、バンプ11の先端部分は柔軟性
シートに金型締め付け圧力により埋設しているためシー
ト剥離後、バンプ11の先端部は熱可塑性樹脂12の上
面よりも突出している。また熱可塑性樹脂12の形成方
法としてはポッティング法を用いても構わない。また熱
可塑性樹脂による樹脂シートを半導体ウェハ13のバン
プ11側から熱圧着しても構わない。この場合、熱圧着
後、バンプ11の表面の樹脂を取り除くために機械的研
磨、あるいはサンドブラストなどを用いる必要がある。
なお、柔軟性シートとしては、耐熱性、特に樹脂封止時
の熱に耐える材質よりなるものであり、絶縁性、剥離性
を有しているものであればよいが、加熱により溶融、軟
化して、半導体素子の表面に接着するようなものでなけ
ればよい。また熱可塑性樹脂の厚みとしては、バンプ1
1の高さ以内の厚みであり、半導体装置を基板実装した
際のリフローによって、熱可塑性樹脂が溶融し、実装基
板と半導体装置とを強固に接続できる程度の量を保持し
た厚みであればよい。
Next, the semiconductor wafer 1 on which the bumps 11 are formed
A flexible sheet (not shown) is covered on the surface on which the third bumps 11 are formed, and is held in a mold. A thermoplastic resin is sealed in the gap between the semiconductor wafer 13 and the flexible sheet by an injection molding technique. After encapsulation, the semiconductor wafer 13 is taken out of the mold and the flexible sheet is peeled off to obtain the semiconductor wafer 13 shown in FIG.
As shown in (d), the thermoplastic resin 12 can be formed in a region other than the bumps 11 of the semiconductor wafer 13.
During the encapsulation of the thermoplastic resin, the tip of the bump 11 is embedded in the flexible sheet by the mold clamping pressure, so that the tip of the bump 11 protrudes from the upper surface of the thermoplastic resin 12 after the sheet is peeled off. As a method for forming the thermoplastic resin 12, a potting method may be used. Alternatively, a resin sheet made of a thermoplastic resin may be thermocompression-bonded from the bump 11 side of the semiconductor wafer 13. In this case, after the thermocompression bonding, it is necessary to use mechanical polishing or sandblasting to remove the resin on the surface of the bump 11.
The flexible sheet is made of a material having heat resistance, particularly a material that can withstand heat during resin encapsulation, and any material having insulation and peeling properties may be used. It does not have to be such that it adheres to the surface of the semiconductor element. The thickness of the thermoplastic resin is as follows: bump 1
The thickness is within a height of 1 and the thickness is such that the thermoplastic resin is melted by the reflow when the semiconductor device is mounted on the substrate, and the amount is large enough to firmly connect the mounting substrate and the semiconductor device. .

【0024】次に図2(e)に示すように、半導体ウェ
ハ13の個々の半導体素子の分割として、半導体ウェハ
13に形成されたスクライブラインに沿ってダイシング
ソーにより半導体素子を個々に分割し、半導体素子8上
の半導体素子電極9上に金属層10が設けられ、その金
属層10上にバンプ11が形成され半導体素子電極9領
域以外の領域には熱可塑性樹脂層12が形成された半導
体装置を形成する。
Next, as shown in FIG. 2E, the semiconductor elements of the semiconductor wafer 13 are divided into individual semiconductor elements by a dicing saw along scribe lines formed on the semiconductor wafer 13, A semiconductor device in which a metal layer 10 is provided on a semiconductor element electrode 9 on a semiconductor element 8, a bump 11 is formed on the metal layer 10, and a thermoplastic resin layer 12 is formed in a region other than the semiconductor element electrode 9 region To form

【0025】次に本実施形態の半導体装置を基板実装す
る実装方法について説明する。半導体装置を実装基板と
して回路基板に実装する方法としては、熱可塑性樹脂面
を基板に対向させ、半導体装置のバンプと回路基板の電
極とを位置合わせして、回路基板に搭載後、リフロー
(加熱)することで、半導体装置に設けたバンプ11が
溶融して回路基板に設けた電極と接続させる。さらに、
半導体装置に設けた熱可塑性樹脂が溶融、硬化し、半導
体装置と回路基板とを接続させる。このように本実施形
態の半導体装置を基板実装した場合、半導体装置と回路
基板とを電気的に接続するとともに、熱可塑性樹脂の接
続により回路基板と半導体装置との接続をより強固とす
ることができる。
Next, a mounting method for mounting the semiconductor device of this embodiment on a substrate will be described. As a method of mounting a semiconductor device on a circuit board as a mounting board, a thermoplastic resin surface is opposed to the board, bumps of the semiconductor device are aligned with electrodes of the circuit board, and after mounting on the circuit board, reflow (heating) is performed. 2), the bumps 11 provided on the semiconductor device are melted and connected to the electrodes provided on the circuit board. further,
The thermoplastic resin provided in the semiconductor device is melted and hardened, and the semiconductor device and the circuit board are connected. As described above, when the semiconductor device of the present embodiment is mounted on a board, the semiconductor device and the circuit board can be electrically connected, and the connection between the circuit board and the semiconductor device can be further strengthened by the connection of the thermoplastic resin. it can.

【0026】本実施形態では、熱可塑性樹脂を用いてい
るので、回路基板に半導体素子を接合した後、加熱処理
するだけで半導体素子と回路基板との間隔を封止するこ
とができ、また複数の半導体素子に対して同時に加熱す
ることにより、生産性を向上させて樹脂封止することが
できる。もちろん必要に応じては個々の半導体素子ごと
に個別に熱処理することによっても樹脂封止することが
できる。特に目的に応じて熱可塑性樹脂の種類を半導体
素子の品種ごとに変えるような場合は、品種ごとに対応
して半導体素子を加熱処理して樹脂封止できるので、将
来的な多品種生産に対しては非常に効果が大きい。ま
た、熱可塑性樹脂を用いているので、半導体素子に欠
陥、不良が発見された場合には、加熱処理することで、
回路基板を破壊したり、基板に損傷を与えることなく、
回路基板から半導体素子を容易に取り外すことができる
ため、生産性、生産コスト的にも有利である。
In the present embodiment, since the thermoplastic resin is used, the gap between the semiconductor element and the circuit board can be sealed only by heating after bonding the semiconductor element to the circuit board. By simultaneously heating the semiconductor elements, the productivity can be improved and resin sealing can be performed. Of course, if necessary, resin sealing can be performed by individually performing heat treatment for each semiconductor element. In particular, when the type of thermoplastic resin is changed for each type of semiconductor element according to the purpose, the semiconductor element can be heat-treated and sealed with resin for each type of product. Is very effective. In addition, since a thermoplastic resin is used, when a defect or defect is found in a semiconductor element, by performing a heat treatment,
Without destroying the circuit board or damaging the board,
Since the semiconductor element can be easily removed from the circuit board, it is advantageous in terms of productivity and production cost.

【0027】次に本発明の第2の実施形態について図面
を参照しながら説明する。図3は本実施形態における半
導体装置を示す断面図である。
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view illustrating the semiconductor device according to the present embodiment.

【0028】図3に示すように本実施形態の半導体装置
は、半導体素子14上の半導体素子電極15上に金属層
16が設けられ、そして半導体素子14の半導体素子電
極15領域以外の領域には熱可塑性樹脂層17が形成さ
れているものである。
As shown in FIG. 3, in the semiconductor device of this embodiment, a metal layer 16 is provided on a semiconductor element electrode 15 on a semiconductor element 14, and a region other than the semiconductor element electrode 15 area of the semiconductor element 14 is provided. In this case, a thermoplastic resin layer 17 is formed.

【0029】以上のように構成された本実施形態の半導
体装置について以下、その製造方法を説明する。
The method of manufacturing the semiconductor device of the present embodiment having the above-described configuration will be described below.

【0030】前記した第1の実施形態と同様に、半導体
ウェハ上に真空蒸着法、スパッタリング法、CVD法あ
るいは無電解めっき法により半導体素子電極側全面に金
属層を形成する。ここでの一例としてはTiとCuの組
み合わせを用いる。金属材料としてはTi、Cr、Ti
W、Cu、Ni、Au、Pdなどを用いても構わない
し、それぞれの金属の組み合わせでも構わない。次にエ
ッチングレジストを塗布し、乾燥、露光、現像すること
により、半導体素子電極に相当する位置のレジストを残
す。次にエッチング剤により電極部以外の金属層を溶解
除去する。次にエッチングレジストを形成した側に柔軟
性シートを覆い、金型内に保持し、熱可塑性樹脂を射出
成形技術により半導体ウェハと柔軟性シートの間隙に封
入する。封入後、金型内から半導体ウェハを取り出し、
柔軟性シートを剥離する。また熱可塑性樹脂の形成方法
としてポッティング法を用いても構わない。次にエッチ
ングレジストを溶融除去し、金属層を露出させる。次に
半導体ウェハのスクライブラインに沿って、半導体素子
を個々に分割することにより、図3に示した半導体装置
を形成するものである。
As in the first embodiment, a metal layer is formed on the entire surface of the semiconductor device electrode on a semiconductor wafer by vacuum deposition, sputtering, CVD, or electroless plating. Here, a combination of Ti and Cu is used as an example. Ti, Cr, Ti
W, Cu, Ni, Au, Pd, or the like may be used, or a combination of respective metals may be used. Next, an etching resist is applied, dried, exposed and developed to leave a resist at a position corresponding to the semiconductor element electrode. Next, the metal layer other than the electrode portion is dissolved and removed with an etching agent. Next, a flexible sheet is covered on the side on which the etching resist is formed, held in a mold, and a thermoplastic resin is sealed in a gap between the semiconductor wafer and the flexible sheet by an injection molding technique. After encapsulation, take out the semiconductor wafer from the mold,
Peel off the flexible sheet. Further, a potting method may be used as a method for forming the thermoplastic resin. Next, the etching resist is removed by melting to expose the metal layer. Next, the semiconductor device shown in FIG. 3 is formed by dividing the semiconductor elements individually along scribe lines of the semiconductor wafer.

【0031】次に本発明を別のタイプの半導体装置に適
用した例について図面を参照しながら説明する。
Next, an example in which the present invention is applied to another type of semiconductor device will be described with reference to the drawings.

【0032】図4に示した半導体装置は、前記した実施
形態における熱可塑性樹脂の作用効果をBGA(Bal
l Grid Array)型半導体パッケージに適用
したものであり、基板18に対して熱可塑性樹脂19を
設け、基板電極20上にははんだボール21を設けたも
のである。そして基板18の上面には半導体素子22を
搭載し、基板配線(図示せず)と半導体素子22とを金
属細線23により接続し、基板18の上面であって半導
体素子22の外囲を封止樹脂24で封止した構造であ
る。
The semiconductor device shown in FIG. 4 uses the BGA (Bal
(1 Grid Array) type semiconductor package, in which a thermoplastic resin 19 is provided on a substrate 18 and a solder ball 21 is provided on a substrate electrode 20. The semiconductor element 22 is mounted on the upper surface of the substrate 18, and a substrate wiring (not shown) and the semiconductor element 22 are connected to each other by a thin metal wire 23. This is a structure sealed with a resin 24.

【0033】なお、熱可塑性樹脂の供給については、第
1の実施形態と同様に金型に設置して熱可塑性樹脂層を
形成してもいいし、ポッティング法を用いてもよい。
As for the supply of the thermoplastic resin, a thermoplastic resin layer may be formed by installing it in a mold as in the first embodiment, or a potting method may be used.

【0034】熱可塑性樹脂19を基板18のはんだボー
ル21を設けた側に設けることにより、ボード実装時に
熱可塑性樹脂19の溶融により、実装強度が向上すると
ともに、熱可塑性樹脂19の介在により、ボードとBG
A型半導体パッケージの基板18との熱線膨張係数の不
一致による熱ストレスを緩和することができる。
By providing the thermoplastic resin 19 on the side of the substrate 18 on which the solder balls 21 are provided, the mounting strength is improved by melting the thermoplastic resin 19 at the time of mounting the board, and the board is interposed by the thermoplastic resin 19. And BG
It is possible to reduce the thermal stress caused by the mismatch of the coefficient of linear thermal expansion with the substrate 18 of the A-type semiconductor package.

【0035】次に図5には、SON(Small Ou
tline Non−leadedPackage)や
QFN(Quad Flat Non−leaded
Package)といった片面樹脂封止型の半導体パッ
ケージに適用した例を示す。
FIG. 5 shows a SON (Small Ou).
line Non-leaded Package) or QFN (Quad Flat Non-leaded)
An example in which the present invention is applied to a single-sided resin-encapsulated semiconductor package such as a package is shown.

【0036】図5に示した半導体装置は、前記した実施
形態における熱可塑性樹脂の作用効果をQFN型半導体
パッケージに適用したものであり、リードフレームの支
持部(図示せず)上に半導体素子25が搭載され、リー
ドフレームのインナーリード部26と半導体素子25の
半導体素子電極とは金属細線27で接続され、インナー
リード部26の底面側を露出させるように半導体素子2
5の外囲を封止樹脂28で封止した構造である。封止樹
脂28より露出したインナーリード部26の底面および
側面領域はアウターリード部29を構成している。ここ
でQFN型半導体パッケージの底面のアウターリード部
29間には熱可塑性樹脂30が形成されているものであ
る。熱可塑性樹脂30の供給については、同様に金型に
設置して熱可塑性樹脂層を形成してもいいし、封止樹脂
に凹部を形成した後にポッティング法により熱可塑性樹
脂を形成してもよい。
The semiconductor device shown in FIG. 5 is one in which the function and effect of the thermoplastic resin in the above-described embodiment are applied to a QFN type semiconductor package, and a semiconductor element 25 is provided on a support portion (not shown) of a lead frame. Is mounted, the inner lead portion 26 of the lead frame and the semiconductor element electrode of the semiconductor element 25 are connected by a thin metal wire 27, and the semiconductor element 2 is exposed so that the bottom side of the inner lead section 26 is exposed.
5 is sealed with a sealing resin 28. The bottom and side surfaces of the inner lead portion 26 exposed from the sealing resin 28 constitute an outer lead portion 29. Here, a thermoplastic resin 30 is formed between the outer lead portions 29 on the bottom surface of the QFN type semiconductor package. As for the supply of the thermoplastic resin 30, the thermoplastic resin layer may be formed by installing the same in a mold, or the thermoplastic resin may be formed by a potting method after forming a concave portion in the sealing resin. .

【0037】熱可塑性樹脂30を半導体パッケージの露
出しているアウターリード部間に設けることにより、半
導体パッケージの実装時に熱可塑性樹脂30の溶融によ
り、実装強度を向上させることができ、また半導体パッ
ケージの熱ストレスを緩和することができる。
By providing the thermoplastic resin 30 between the exposed outer leads of the semiconductor package, the mounting strength can be improved by melting the thermoplastic resin 30 when the semiconductor package is mounted. Thermal stress can be reduced.

【0038】以上のように本発明における半導体素子へ
の熱可塑性樹脂の適用により、半導体装置の生産性向
上、半導体パッケージ実装上、多大な効果が期待できる
ものである。
As described above, by applying the thermoplastic resin to the semiconductor element in the present invention, a great effect can be expected on the improvement of the productivity of the semiconductor device and the mounting of the semiconductor package.

【0039】なお、熱可塑性樹脂としては絶縁性を有す
るものがよく、成形性に優れたものがよい。
The thermoplastic resin preferably has an insulating property, and preferably has excellent moldability.

【0040】[0040]

【発明の効果】以上説明したように、本発明では熱可塑
性樹脂を用いているので、回路基板に半導体素子を接合
した後、加熱処理するだけで半導体素子と回路基板との
間隔を封止することができ、また複数の半導体素子に対
して同時に加熱することにより、生産性を向上させて樹
脂封止することができる。特に目的に応じて熱可塑性樹
脂の種類を半導体素子の品種ごとに変えるような場合
は、品種ごとに対応して半導体素子を加熱処理して樹脂
封止できるので、将来的な多品種生産に対しては非常に
効果が大きい。また、熱可塑性樹脂を用いているので、
半導体素子に欠陥、不良が発見された場合には、加熱処
理することで、回路基板を破壊したり、基板に損傷を与
えることなく、回路基板から半導体素子を容易に取り外
すことができるため、生産性、生産コスト的にも有利で
ある。
As described above, since a thermoplastic resin is used in the present invention, the gap between the semiconductor element and the circuit board is sealed only by heating after bonding the semiconductor element to the circuit board. By simultaneously heating a plurality of semiconductor elements, productivity can be improved and resin sealing can be performed. In particular, when the type of thermoplastic resin is changed for each type of semiconductor element according to the purpose, the semiconductor element can be heat-treated and sealed with resin for each type of product. Is very effective. Also, since a thermoplastic resin is used,
If a defect or defect is found in a semiconductor element, the semiconductor element can be easily removed from the circuit board by heat treatment without destroying the circuit board or damaging the board. It is also advantageous in terms of performance and production cost.

【0041】さらに、本発明は熱可塑性樹脂を半導体装
置、回路基板、半導体パッケージの実装面側に設けるこ
とにより、基板実装時にリフローすることで基板との電
気的接続を行うとともにリフロー温度で熱可塑性樹脂が
溶融し、硬化するため基板と半導体装置の接続とをより
強固とすることができ、また熱可塑性樹脂の介在によ
り、基板、半導体素子の熱ストレスを緩和し、接続部、
例えばバンプにかかる熱応力を緩和でき、信頼性を向上
させることができる。
Further, according to the present invention, by providing a thermoplastic resin on the mounting surface side of a semiconductor device, a circuit board, and a semiconductor package, reflow can be performed at the time of mounting the substrate, thereby making an electrical connection with the substrate and at the reflow temperature. Since the resin is melted and hardened, the connection between the substrate and the semiconductor device can be further strengthened, and the thermal stress of the substrate and the semiconductor element is reduced by the interposition of the thermoplastic resin, and the connection portion,
For example, the thermal stress applied to the bump can be reduced, and the reliability can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態における半導体装置を示す
断面図
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 2 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】本発明の一実施形態における半導体装置を示す
断面図
FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図4】本発明の一実施形態の半導体パッケージへの適
用を示す断面図
FIG. 4 is a sectional view showing an embodiment of the present invention applied to a semiconductor package;

【図5】本発明の一実施形態の半導体パッケージへの適
用を示す断面図
FIG. 5 is a sectional view showing an embodiment of the present invention applied to a semiconductor package.

【図6】従来の半導体装置を示す断面図FIG. 6 is a sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 半導体素子電極 3 バンプ 4 導電性接着剤 5 回路基板 6 回路基板ランド 7 封止樹脂 8 半導体素子 9 半導体素子電極 10 金属層 11 バンプ 12 熱可塑性樹脂 13 半導体ウェハ 14 半導体素子 15 半導体素子電極 16 金属層 17 熱可塑性樹脂 18 基板 19 熱可塑性樹脂 20 基板電極 21 はんだボール 22 半導体素子 23 金属細線 24 封止樹脂 25 半導体素子 26 インナーリード部 27 金属細線 28 封止樹脂 29 アウターリード部 30 熱可塑性樹脂 Reference Signs List 1 semiconductor element 2 semiconductor element electrode 3 bump 4 conductive adhesive 5 circuit board 6 circuit board land 7 sealing resin 8 semiconductor element 9 semiconductor element electrode 10 metal layer 11 bump 12 thermoplastic resin 13 semiconductor wafer 14 semiconductor element 15 semiconductor element Electrode 16 Metal layer 17 Thermoplastic resin 18 Substrate 19 Thermoplastic resin 20 Substrate electrode 21 Solder ball 22 Semiconductor element 23 Fine metal wire 24 Sealing resin 25 Semiconductor element 26 Inner lead portion 27 Fine metal wire 28 Sealing resin 29 Outer lead portion 30 Heat Plastic resin

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 23/31 (72)発明者 中村 嘉文 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 隈川 隆博 大阪府高槻市幸町1番1号 松下電子工業 株式会社内──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification symbol FI H01L 23/31 (72) Inventor Yoshifumi Nakamura 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Industrial Co., Ltd. (72) Inventor Takahiro Kumakawa 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Corporation

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、前記半導体素子の電極上
に形成された金属層と、前記金属層以外の半導体素子表
面の領域に形成された熱可塑性樹脂層とよりなることを
特徴とする半導体装置。
1. A semiconductor comprising: a semiconductor element; a metal layer formed on an electrode of the semiconductor element; and a thermoplastic resin layer formed in a region on the surface of the semiconductor element other than the metal layer. apparatus.
【請求項2】 半導体素子と、前記半導体素子の電極上
に形成された金属層と、前記金属層上に形成された突起
電極と、前記突起電極以外の半導体素子表面の領域に形
成された熱可塑性樹脂層とよりなることを特徴とする半
導体装置。
2. A semiconductor element, a metal layer formed on an electrode of the semiconductor element, a protruding electrode formed on the metal layer, and heat formed on a region of the semiconductor element surface other than the protruding electrode. A semiconductor device comprising a plastic resin layer.
【請求項3】 回路基板と、前記回路基板上に搭載され
た半導体素子と、前記回路基板の配線と前記半導体素子
とを電気的に接続した接続手段と、前記回路基板上の半
導体素子の外囲を封止した樹脂と、前記回路基板の底面
に設けられた突起電極とを有する半導体装置であって、
前記回路基板の底面に設けられた突起電極と突起電極と
の間の回路基板底面には熱可塑性樹脂が設けられている
ことを特徴とする半導体装置。
3. A circuit board, a semiconductor element mounted on the circuit board, connection means for electrically connecting a wiring of the circuit board and the semiconductor element, and an external part of the semiconductor element on the circuit board. A semiconductor device having a resin sealing an enclosure and a protruding electrode provided on a bottom surface of the circuit board,
A semiconductor device, wherein a thermoplastic resin is provided on the bottom surface of the circuit board between the projecting electrodes provided on the bottom surface of the circuit board.
【請求項4】 リードフレームの支持部に搭載された半
導体素子と、前記半導体素子とインナーリード部とを電
気的に接続した接続手段と、前記インナーリード部の底
面側を露出させて前記半導体素子の外囲を封止した封止
樹脂とよりなる半導体装置であって、前記封止樹脂より
露出した前記インナーリード部面はアウターリード部を
構成し、前記アウターリード部とアウターリード部との
間には熱可塑性樹脂が形成されていることを特徴とする
半導体装置。
4. A semiconductor element mounted on a support portion of a lead frame, connecting means for electrically connecting the semiconductor element to an inner lead part, and exposing a bottom side of the inner lead part to the semiconductor element. Wherein the inner lead portion surface exposed from the sealing resin constitutes an outer lead portion, and is formed between the outer lead portion and the outer lead portion. Wherein a thermoplastic resin is formed on the semiconductor device.
【請求項5】 半導体素子上の半導体素子電極上全面に
金属層を形成し、前記半導体素子電極に相当する位置を
露出させ、半導体素子電極上に金属層を形成する工程
と、前記半導体素子電極上の金属層上に突起電極を形成
する工程と、前記半導体素子の突起電極を形成した面側
に柔軟性シートを覆い、金型内に保持し、熱可塑性樹脂
を半導体素子と柔軟性シートとの間隙に封入する工程
と、金型内から半導体素子を取り出し、柔軟性シートを
剥離して、熱可塑性樹脂を半導体素子の突起電極以外の
領域に形成する工程とよりなることを特徴とする半導体
装置の製造方法。
5. A step of forming a metal layer on the entire surface of a semiconductor element electrode on a semiconductor element, exposing a position corresponding to the semiconductor element electrode, and forming a metal layer on the semiconductor element electrode; Forming a protruding electrode on the upper metal layer, covering the flexible sheet on the surface of the semiconductor element on which the protruding electrode is formed, holding the flexible sheet in a mold, and forming a thermoplastic resin between the semiconductor element and the flexible sheet. And a step of taking out the semiconductor element from the mold, peeling off the flexible sheet, and forming a thermoplastic resin in a region other than the projecting electrode of the semiconductor element. Device manufacturing method.
【請求項6】 複数の半導体素子が形成された半導体ウ
ェハの半導体素子電極上全面に金属層を形成し、前記半
導体素子電極に相当する位置を露出させ、半導体素子電
極上に金属層を形成する工程と、前記半導体素子電極上
の金属層上に突起電極を形成する工程と、前記半導体ウ
ェハの突起電極を形成した面側に柔軟性シートを覆い、
金型内に保持し、熱可塑性樹脂を半導体ウェハと柔軟性
シートとの間隙に封入する工程と、金型内から半導体ウ
ェハを取り出し、柔軟性シートを剥離して、熱可塑性樹
脂を半導体ウェハの突起電極以外の領域に形成する工程
と、前記半導体ウェハを分割して、個々の半導体装置を
形成する工程とよりなることを特徴とする半導体装置の
製造方法。
6. A metal layer is formed on an entire surface of a semiconductor device electrode of a semiconductor wafer on which a plurality of semiconductor devices are formed, a position corresponding to the semiconductor device electrode is exposed, and a metal layer is formed on the semiconductor device electrode. And forming a protruding electrode on the metal layer on the semiconductor element electrode, and covering a flexible sheet on the surface of the semiconductor wafer on which the protruding electrode is formed,
Holding the thermoplastic resin in the gap between the semiconductor wafer and the flexible sheet, holding the semiconductor wafer in the mold, removing the semiconductor wafer from the mold, peeling off the flexible sheet, and removing the thermoplastic resin from the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: forming a semiconductor wafer in a region other than a protruding electrode; and dividing the semiconductor wafer to form individual semiconductor devices.
【請求項7】 半導体装置を基板に実装する半導体装置
の実装方法であって、半導体装置として、半導体素子
と、前記半導体素子の電極上に形成された金属層と、前
記金属層上に形成された突起電極と、前記突起電極以外
の半導体素子表面の領域に形成された熱可塑性樹脂層と
よりなる半導体装置を用い、前記半導体装置を前記熱可
塑性樹脂面を基板に対向させ、前記半導体装置のバンプ
と基板上の電極とを位置合わせして搭載し、加熱処理し
て前記半導体装置の突起電極を溶融させて前記基板の電
極と接続するとともに、前記加熱処理により半導体装置
の熱可塑性樹脂を溶融、硬化させて半導体装置と基板と
を接続させることを特徴とする半導体装置の実装方法。
7. A semiconductor device mounting method for mounting a semiconductor device on a substrate, wherein the semiconductor device includes a semiconductor element, a metal layer formed on an electrode of the semiconductor element, and a metal layer formed on the metal layer. Using a semiconductor device composed of a thermoplastic resin layer formed in a region of the surface of the semiconductor element other than the protruding electrode, the semiconductor device having the thermoplastic resin surface facing a substrate, The bumps and the electrodes on the substrate are aligned and mounted, and heated to melt the protruding electrodes of the semiconductor device and connect to the electrodes of the substrate, and to melt the thermoplastic resin of the semiconductor device by the heat treatment. Curing the semiconductor device and connecting the substrate to the substrate.
JP9563998A 1998-04-08 1998-04-08 Semiconductor device Expired - Fee Related JP3417292B2 (en)

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