JPH01173733A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01173733A JPH01173733A JP33201887A JP33201887A JPH01173733A JP H01173733 A JPH01173733 A JP H01173733A JP 33201887 A JP33201887 A JP 33201887A JP 33201887 A JP33201887 A JP 33201887A JP H01173733 A JPH01173733 A JP H01173733A
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- electrodes
- insulating
- resin
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract 3
- 229920001169 thermoplastic Polymers 0.000 claims description 6
- 239000004416 thermosoftening plastic Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims 2
- 238000000206 photolithography Methods 0.000 claims 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000005520 cutting process Methods 0.000 abstract description 2
- 229920005992 thermoplastic resin Polymers 0.000 abstract 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 241000723438 Cercidiphyllum japonicum Species 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に狭ピッチ、多端子の半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a narrow pitch, multi-terminal semiconductor device.
従来の技術
多端子、狭ピッチ化が進む半導体素子の電極を絶縁性基
板の導体配線に一括接合する実装方法としてマイクロバ
ンプボンディング実装技術がある。BACKGROUND ART Microbump bonding is a mounting method for collectively bonding the electrodes of semiconductor devices, which are becoming increasingly multi-terminal and narrower in pitch, to conductor wiring on an insulating substrate.
この実装方法の１実施例を第４図に示した。まず第４図
ａに示した様に半導体素子２の電極１を有する側に熱硬
化性の絶縁性樹脂３をデイスペンサー等で塗布する。つ
いで第４図すに示した様に絶縁性基板４の導体配線６′
ｆ：有する面が半導体素子２の電極１と向かい合う様に
して絶縁性基板４を熱硬化性の絶縁性樹脂３の上から半
導体素子２に載せ、絶縁性基板４の配線電極６と半導体
素子２の電極１とを位置合わせする。次に第４図Ｃに示
した様に、加圧治具６を用いて半導体素子２と絶縁性基
板４を加圧し、半導体素子２の電極１と絶縁性基板４の
配線電極６とを圧接する。この状態のまま加熱し、熱硬
化性の絶縁性樹脂を硬化させる。硬化終了後は加圧を取
り去る。この際、半導体素子２の電極１は絶縁性基板１
の配線電極６に、熱硬化性の絶縁性樹脂３の硬化によっ
て生じる収縮応力により圧接されており、加圧を取り去
っても、両者の電気的接続は保たれる。An example of this mounting method is shown in FIG. First, as shown in FIG. 4a, a thermosetting insulating resin 3 is applied to the side of the semiconductor element 2 having the electrode 1 using a dispenser or the like. Next, as shown in Figure 4, the conductor wiring 6' of the insulating substrate 4
f: Place the insulating substrate 4 on the semiconductor element 2 from above the thermosetting insulating resin 3 so that the surface thereof faces the electrode 1 of the semiconductor element 2, and connect the wiring electrode 6 of the insulating substrate 4 and the semiconductor element 2. Align with electrode 1 of. Next, as shown in FIG. 4C, the semiconductor element 2 and the insulating substrate 4 are pressurized using the pressing jig 6, and the electrode 1 of the semiconductor element 2 and the wiring electrode 6 of the insulating substrate 4 are pressed together. do. This state is heated to harden the thermosetting insulating resin. After curing is complete, remove the pressure. At this time, the electrode 1 of the semiconductor element 2 is connected to the insulating substrate 1.
It is pressed against the wiring electrode 6 by the shrinkage stress generated by the hardening of the thermosetting insulating resin 3, and even if the pressure is removed, the electrical connection between the two is maintained.
第６図に半導体素子１２に突起電極１１を形成させる方
法を示した。まず第４図ａに示す様に半導体ウェハー１
４に光硬化性の絶縁性樹脂１６をスピンナー等を使って
均一に塗布する。ついでフォ） ＩＪソ技術に用いて、
第４図すに示す様に突起電極１１を形成させる部分（開
孔部絶縁性樹脂１６）以外の絶縁性樹脂（レジスト部絶
縁性樹脂１３）のみにＵＶ線を照射して、レジスト部絶
縁性樹脂１３を硬化させる。FIG. 6 shows a method for forming the protruding electrodes 11 on the semiconductor element 12. First, as shown in FIG. 4a, a semiconductor wafer 1 is
A photo-curable insulating resin 16 is uniformly applied to 4 using a spinner or the like. Then, using the IJ technology,
As shown in FIG. 4, only the insulating resin (the resist part insulating resin 13) other than the part where the protruding electrode 11 is formed (the opening part insulating resin 16) is irradiated with UV rays, and the resist part is insulated. The resin 13 is cured.
次に、第６図Ｃに示す様に開孔部絶縁性樹脂１５のみを
溶剤を用いて溶出させ、開孔部１７を形成させる。つい
で半導体ウエノ・−１４ごと絶縁性樹脂１３のベーキン
グを行った後、これをレジスト皮膜として用いて電気メ
ツキ法等により第５図ｄに示した様な突起電極１１全形
成させる。突起電極を形成させた後は、第６図ｅに示し
た様に溶剤を用いて、残りの未硬化の絶縁性樹脂１６を
完全り取り除く。最後に半導体ウエノ・−１４のダイシ
ングを行い、半導体ウェハーを第６図ｒに示した様な半
導体素子１２に分割する０
発明が解決しようとする問題点
マイクロバンプボンディング実装技術では以上に示した
様なプロセスを経て半導体装置を製造する訳であるが、
この方式では、半導体素子に突起電極を設ける為に形成
させたレジスト皮膜を取り除き、ウェハーのダイシング
を行ってから、あらためて半導体素子に光硬化性の絶縁
性の樹脂を塗布する必要があり、工程が多く、コスト高
につながる。Next, as shown in FIG. 6C, only the hole insulating resin 15 is eluted using a solvent to form the hole 17. After baking the insulating resin 13 together with the semiconductor Ueno-14, the entire protruding electrode 11 as shown in FIG. 5d is formed by electroplating or the like using this as a resist film. After forming the protruding electrodes, the remaining uncured insulating resin 16 is completely removed using a solvent as shown in FIG. 6e. Finally, the semiconductor wafer is diced to divide the semiconductor wafer into semiconductor elements 12 as shown in FIG. Semiconductor devices are manufactured through various processes,
In this method, it is necessary to remove the resist film formed to provide the protruding electrodes on the semiconductor element, dice the wafer, and then recoat the semiconductor element with a photocurable insulating resin. This often leads to higher costs.
問題点を解決するための手段
本発明は上記問題点を解決するために、レジスト皮膜を
形成する光硬化性の絶縁性樹脂に硬化物が熱可塑性の性
質を有するものを用い、突起電極形成後もレジスト皮膜
を除去せず、そのままダイシングし、半導体素子と絶縁
性基板の接着の際に、半導体素子上に残っているレジス
ト皮膜を熱によＶ溶融させ、そのまま接着剤として用い
ることとした。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a photocurable insulating resin that forms the resist film, the cured product of which has thermoplastic properties, and after forming the protruding electrodes. However, the resist film was not removed, but was diced as it was, and when bonding the semiconductor element and the insulating substrate, the resist film remaining on the semiconductor element was V-melted by heat and used as an adhesive as it was.
作用
上記工法で突起電極を形成させ、かつ半導体素子を配線
電極を有する絶縁性基板に実装することにより、レジス
ト皮膜を半導体素子から除去する工程及び半導体素子を
基板上に接着する為の樹脂を半導体素子上に塗布する工
程をマイクロバンプボンディングの工程から取り除くこ
とができる。Function: By forming protruding electrodes using the above method and mounting the semiconductor element on an insulating substrate having wiring electrodes, the resist film is removed from the semiconductor element and the resin for bonding the semiconductor element to the substrate is applied to the semiconductor element. The process of coating on the device can be removed from the microbump bonding process.
実施例 本発明の実施例を第１図及び第２図を用いて説明する。Example Embodiments of the present invention will be described with reference to FIGS. 1 and 2.
まず第１図を用いて突起電極形成プロセスを説明する。First, the protrusion electrode forming process will be explained using FIG.
初めに第１図ａに示す様に半導体ウェハー２４の電極金
有する側の面に光硬化性でしかも硬化物が熱可塑性であ
る様な絶縁性樹脂２６をスピ／す−等で塗布する。つい
で第１図すに示す様に、ガラスマスクを用いて突起電極
２１全形成させる部分（開孔部絶縁性樹脂２５）以外の
絶縁性樹脂（レジスト部絶縁性樹脂２３）のみにＵＶ線
を照射して、レジスト部絶縁性樹脂２３のみ全硬化させ
る。ＵＶ線の照射を受けず、未硬化のままである開孔部
絶縁性樹脂２６は有機溶剤等により溶出させ、第１図Ｃ
に示す様に突起電極２１を形成させる部分のみに開孔部
２７を開ける。こうして形成させたレジスト皮膜を用い
て電気メツキ法によυ開孔部２７を開けた場所に突起電
極２１を形成させる。First, as shown in FIG. 1A, an insulating resin 26 which is photocurable and whose cured material is thermoplastic is coated on the surface of the semiconductor wafer 24 on the side having the electrode metal using a sprayer or the like. Next, as shown in FIG. 1, using a glass mask, UV rays are irradiated only to the insulating resin (insulating resin 23 in the resist part) other than the part where the entire protruding electrode 21 is to be formed (the insulating resin 25 in the opening part). Then, only the resist portion insulating resin 23 is completely cured. The insulating resin 26 in the openings, which is not irradiated with UV rays and remains uncured, is eluted with an organic solvent or the like, and the resin 26 shown in FIG.
As shown in FIG. 2, an opening 27 is made only in the portion where the protruding electrode 21 is to be formed. Using the resist film thus formed, the protruding electrodes 21 are formed at the locations where the υ openings 27 are made by electroplating.
ただし、本発明による実装法ではメツキ後にバリアメタ
ルのエツチング処理ができない。そこで第３図に示す様
に電気メツキ法により突起電極２１を形成させる電極部
４ｏへ電気を流すために必要な配線部４１以外のバリア
メタルはあらかじめエツチングにより除去しておく必要
がある。配線部４１はウェハー２４のダイシングライン
４２に沿わせておき、その幅をダイシングの際のカッテ
ィング幅よシ細くしておく。また、この際、形成させる
突起電極２１はレジスト皮膜の厚さより低くしておく必
要がある。最後に第１図ｅに示す様にレジスト皮膜を表
面に有したままで半導体ウェハー２４のダイシングを行
い、半導体素子をチップ状に分割する。この際、配線部
４１はダイシングの際に削り取られ、それぞれの突起電
極２１は電気的に分離される。こうして突起電極２１と
、熱可塑性の絶縁性樹脂を表面に有する半導体素子が用
意される。次に第２図を用いてその実装プロセスについ
て説明する。However, in the mounting method according to the present invention, the barrier metal cannot be etched after plating. Therefore, as shown in FIG. 3, it is necessary to remove by etching in advance the barrier metal other than the wiring part 41 necessary for flowing electricity to the electrode part 4o on which the protruding electrode 21 is formed by electroplating. The wiring portion 41 is placed along the dicing line 42 of the wafer 24, and its width is made narrower than the cutting width during dicing. Further, at this time, the thickness of the protruding electrode 21 to be formed needs to be lower than the thickness of the resist film. Finally, as shown in FIG. 1e, the semiconductor wafer 24 is diced with the resist film still on the surface to divide the semiconductor elements into chips. At this time, the wiring portion 41 is scraped off during dicing, and each protruding electrode 21 is electrically isolated. In this way, the protruding electrode 21 and the semiconductor element having the thermoplastic insulating resin on the surface are prepared. Next, the mounting process will be explained using FIG. 2.
まず第２図ａに示した半導体素子３２の突起電極３１を
有する側の面に第２図すに示した様に配線電極３６ｆ：
有する絶縁性基板３４を配線電極３６が突起電極３１と
向かい合う様にして載せ、配線電極３６と突起電極３１
の位置合わせを行う。この状態のまま、第２図Ｃに示す
様に加熱し絶縁性樹脂３３を溶融させながら加圧治具３
６を用いて半導体素子３２を絶縁性基板３４に加圧し、
配線電極３６と突起電極３１を圧接する。ついで系全体
を冷却し、絶縁性樹脂３３が再硬化したら第２図ｄに示
す様に加圧を取り去る。この際、半導体素子３２の突起
電極３１と絶縁性基板３２の配線電極３５とは、絶縁性
樹脂３３の再硬化の際に発生する収縮応力により圧接さ
れ、電気的接続を保つ。本実施例では電気メツキ法によ
り突起電極を形成させたが、突起電極を無電解メツキ法
により形成させてもよい。First, a wiring electrode 36f is placed on the surface of the semiconductor element 32 shown in FIG. 2a on the side having the protruding electrode 31 as shown in FIG.
Place the insulating substrate 34 with the wiring electrode 36 facing the protruding electrode 31, and place the wiring electrode 36 and the protruding electrode 31.
Perform alignment. In this state, as shown in FIG. 2C, the pressing jig 3 is heated while melting the insulating resin 33.
6 to pressurize the semiconductor element 32 to the insulating substrate 34,
The wiring electrode 36 and the protruding electrode 31 are brought into pressure contact. The entire system is then cooled, and once the insulating resin 33 has re-hardened, the pressure is removed as shown in FIG. 2d. At this time, the protruding electrodes 31 of the semiconductor element 32 and the wiring electrodes 35 of the insulating substrate 32 are pressed together by the shrinkage stress generated when the insulating resin 33 is re-hardened to maintain electrical connection. In this embodiment, the protruding electrodes were formed by electroplating, but the protruding electrodes may also be formed by electroless plating.
発明の効果
以上のように本発明によれば、次のような効果を得るこ
とができる。Effects of the Invention As described above, according to the present invention, the following effects can be obtained.
（１） マイクロバンプポンディング実装技術の実装
プロセスにおいて、レジスト皮膜を除去する工程と、半
導体素子に接着用の熱硬化性の絶縁性樹脂を塗布する工
程とを除去することが可能となり、低コスト化を実現で
きる。(1) In the mounting process of micro bump bonding mounting technology, it is possible to eliminate the process of removing the resist film and the process of applying thermosetting insulating resin for adhesion to the semiconductor element, resulting in lower costs. can be realized.
（２）また、絶縁性樹脂の量が均一になる為、品質がよ
く、信頼性が高い。(2) Also, since the amount of insulating resin is uniform, the quality is good and reliability is high.
第１図は本発明の一実施例方法における突起電極形成工
程を示す断面図、第２図は本発明の実施例の実装工程を
示す断面図、第３図は本発明に用いる半導体素子部の平
面図、第４図は従来のマイクロボンディング実装工程の
断面図、第５図は突起電極の形成工程の断面図である。
２３・・・・・・レジスト部絶縁性樹脂（硬化物）、２
４・・・・・・半導体ウェハー、２６・・・・・・開孔
部絶縁性樹脂（未硬化物）、２６・・・・・・絶縁性樹
脂、２７・・・・・・開孔部、２１．３１・・・・・・
突起電極、３２・・・・・・半導体素子、３３・・・・
・・ＵＶ硬化型熱可塑性絶縁樹脂、３４・・・・・・絶
縁性基板、３６・・・・・・配線電極、３６・・・・・
・加圧治具、４０・・・・・・電極、４１・・・・・・
配線、４２・・・・・・ダイシングライン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ｗ＆
Ｓ フ
へ Ｑ
Ｑ ℃
７第２図 ３ｊ−突μｔＩ
ｃ桂
３ざ−・−配様電縁
３１’）Ｅ−“７は゛′−パ
第３図
４０−電極
４１−−一霞ごｉ’−Ｙ＜
第４図
第５図FIG. 1 is a cross-sectional view showing the protruding electrode forming process in an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the mounting process in the embodiment of the present invention, and FIG. 3 is a cross-sectional view of the semiconductor element part used in the present invention. A plan view, FIG. 4 is a sectional view of a conventional microbonding mounting process, and FIG. 5 is a sectional view of a protrusion electrode formation process. 23... Resist part insulating resin (cured product), 2
4... Semiconductor wafer, 26... Opening part insulating resin (uncured material), 26... Insulating resin, 27... Opening part , 21.31...
Projection electrode, 32... Semiconductor element, 33...
...UV curing thermoplastic insulating resin, 34...Insulating substrate, 36...Wiring electrode, 36...
・Pressure jig, 40... Electrode, 41...
Wiring, 42...Dicing line. Name of agent: Patent attorney Toshio Nakao and one other person w&
S Fuhe Q
Q ℃
7Figure 2 3j-TutμtI
c Katsura 3za--Distribution electric edge 31')E-"7 is"-Pa Fig.3
Claims (4)
絶縁性樹脂膜を用いて、突起電極形成部に開孔部を形成
する工程と次いで前記開孔部に金属突起電極を形成する
工程と、前記半導体ウェハーを前記絶縁性樹脂膜を表面
に有するままチップ状態の半導体素子に分割する工程と
、分割した前記半導体素子を配線電極を有する絶縁性基
板に互いの電極同志が向い合う様にして搭載する工程と
、前記絶縁性樹脂を用いて前記半導体素子を前記絶縁性
基板に固着し、電極同志を電気的に接続する工程を有す
る半導体装置の製造方法。(1) On the surface of a semiconductor wafer using photolithography technology,
a step of forming an aperture in the protruding electrode forming portion using an insulating resin film, a step of forming a metal protruding electrode in the aperture, and a step of forming the semiconductor wafer with the insulating resin film on its surface. a step of dividing the semiconductor element into chip-like semiconductor elements, a step of mounting the divided semiconductor element on an insulating substrate having wiring electrodes with the electrodes facing each other, and a step of dividing the semiconductor element using the insulating resin. A method for manufacturing a semiconductor device, comprising the steps of fixing the electrode to the insulating substrate and electrically connecting the electrodes to each other.
あり、加熱により前記絶縁性樹脂を軟化させた後に冷却
し、再硬化させることにより、半導体素子を絶縁性基板
に固着させる特許請求の範囲第１項記載の半導体装置の
製造方法。(2) A patent claim in which the insulating resin is UV curable and thermoplastic, and the semiconductor element is fixed to the insulating substrate by softening the insulating resin by heating, cooling it, and hardening it again. A method for manufacturing a semiconductor device according to item 1.
基板ウェハー表面に、絶縁性樹脂膜により突起電極形成
部に開孔部を形成する工程と、前記開孔部に突起電極を
形成する工程と、及び前記絶縁性基板ウェハーを前記絶
縁性樹脂を表面に有するままチップ状態の絶縁性基板に
分割する工程と、分割した前記絶縁性基板に電極を有す
る半導体素子を互いの電極が向かいあう様にして搭載す
る工程と、前記絶縁性樹脂を用いて前記半導体素子を前
記絶縁性基板に固着し、電極同志を電気的に接続する工
程を有する半導体装置の製造方法。(3) a step of forming an opening in a protruding electrode formation part with an insulating resin film on the surface of an insulating substrate wafer having wiring electrodes using photolithography technology; and a step of forming a protruding electrode in the opening. , a step of dividing the insulating substrate wafer into insulating substrates in the form of chips while having the insulating resin on the surface, and forming semiconductor elements having electrodes on the divided insulating substrates so that the electrodes face each other. A method for manufacturing a semiconductor device, comprising a step of mounting, and a step of fixing the semiconductor element to the insulating substrate using the insulating resin and electrically connecting electrodes to each other.
あり、加熱により前記絶縁性樹脂を軟化させた後に冷却
し、再硬化させることにより、半導体素子を絶縁性基板
に固着させる特許請求の範囲第３項記載の半導体装置の
製造方法。(4) A patent claim in which the insulating resin is UV curable and thermoplastic, and the semiconductor element is fixed to the insulating substrate by softening the insulating resin by heating, cooling it, and hardening it again. A method for manufacturing a semiconductor device according to item 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62332018A JPH0793343B2 (en) | 1987-12-28 | 1987-12-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62332018A JPH0793343B2 (en) | 1987-12-28 | 1987-12-28 | Method for manufacturing semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7052547A Division JP2532825B2 (en) | 1995-03-13 | 1995-03-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01173733A true JPH01173733A (en) | 1989-07-10 |
| JPH0793343B2 JPH0793343B2 (en) | 1995-10-09 |
Family
ID=18250221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62332018A Expired - Fee Related JPH0793343B2 (en) | 1987-12-28 | 1987-12-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793343B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11297750A (en) * | 1998-04-08 | 1999-10-29 | Matsushita Electron Corp | Semiconductor device, manufacture thereof, and mounting of the semiconductor device |
| US6501169B1 (en) | 1999-11-29 | 2002-12-31 | Casio Computer Co., Ltd. | Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise |
| US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
| EP1022774A3 (en) * | 1999-01-21 | 2003-08-06 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
| WO2004070826A1 (en) * | 2003-02-06 | 2004-08-19 | Fujitsu Limited | Method of forming electrode connection structure and electrode connection structure |
| USRE39603E1 (en) | 1994-09-30 | 2007-05-01 | Nec Corporation | Process for manufacturing semiconductor device and semiconductor wafer |
| JP2010062514A (en) * | 2008-09-03 | 2010-03-18 | Ultratera Corp | Semiconductor wafer with adhesive protection layer |
-
1987
- 1987-12-28 JP JP62332018A patent/JPH0793343B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE39603E1 (en) | 1994-09-30 | 2007-05-01 | Nec Corporation | Process for manufacturing semiconductor device and semiconductor wafer |
| JPH11297750A (en) * | 1998-04-08 | 1999-10-29 | Matsushita Electron Corp | Semiconductor device, manufacture thereof, and mounting of the semiconductor device |
| EP1022774A3 (en) * | 1999-01-21 | 2003-08-06 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
| US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
| US6501169B1 (en) | 1999-11-29 | 2002-12-31 | Casio Computer Co., Ltd. | Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise |
| WO2004070826A1 (en) * | 2003-02-06 | 2004-08-19 | Fujitsu Limited | Method of forming electrode connection structure and electrode connection structure |
| JP2010062514A (en) * | 2008-09-03 | 2010-03-18 | Ultratera Corp | Semiconductor wafer with adhesive protection layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793343B2 (en) | 1995-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |