JPS62281361A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62281361A
JPS62281361A JP12393286A JP12393286A JPS62281361A JP S62281361 A JPS62281361 A JP S62281361A JP 12393286 A JP12393286 A JP 12393286A JP 12393286 A JP12393286 A JP 12393286A JP S62281361 A JPS62281361 A JP S62281361A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring
electrode
adhesive
bonding agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12393286A
Other languages
Japanese (ja)
Other versions
JPH0752741B2 (en
Inventor
Hiroaki Fujimoto
博昭 藤本
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12393286A priority Critical patent/JPH0752741B2/en
Publication of JPS62281361A publication Critical patent/JPS62281361A/en
Publication of JPH0752741B2 publication Critical patent/JPH0752741B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain an electric connection by directly contacting an electrode to the wiring of a wiring substrate by a method wherein the coefficient of expansion of the insulative bonding agent, to be used for adhesion of a semiconductor element, is made smaller than that of the electrode of a semiconductor element. CONSTITUTION:The electrode 14 of a semiconductor element 13 and a wiring 12 are brought to come in coincidence with each other, and the semiconductor element 13 is pressed to a wiring substrate 11 using a pressurizing tool 16. At this time, the bonding agent 15 on the wiring 12 is pushed out toward the circumference, and the electrode 14 of the semiconductor element 13 and the wiring 12 are connected electrically. Then, the bonding agent 15 is hardened in a pressurized state. Al, Cu, Pb/Sn solder and the like are used as the materiel for the electrode 14 of the semiconductor element 13, the expansion coefficient of said material is l.4 X 10<-5>1/ deg.C-2.5 X 10 <-5>1/ deg.C, which is the value substantially smaller than the expansion coefficient of the bonding agent 15. Then, the pressurizing tool 16 is released, and the semiconductor element 13 is fixed to the wiring substrate 11. At this time, the electrode 14 of the semiconductor element 13 is maintained in the state wherein it comes in contact with the wiring 12 by the adhesive strength of the bonding agent 15, and electric connection is obtained.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 産業上の利用分野 本発明は半導体装置とくに多端子、狭ピッチのＩＣ，Ｌ
ＳＩのパッケージング構造に関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention Field of Industrial Application The present invention is applicable to semiconductor devices, particularly multi-terminal, narrow pitch ICs, L
This relates to the packaging structure of SI.

従来の技術 従来の技術を第２図とともに説明する。まず、セラミッ
ク、ガラス、ガラスエポキシ等よりなる配線基板１の配
線２を有する面に、接着剤６を塗布する。配線２は、Ｃ
ｒ−Ａｕ、Ａｌ、Ｃｕ、ＩＴＯ等であり、接着剤６は、
熱硬化型又は、紫外線硬化型のエポキシ、シリコーン、
アクリル等の樹脂である。次に、半導体素子３の電極４
を導体配線２とを一致させ半導体素子３を加圧し配線基
板１に押し当てる。この時、配線２上の接着剤５は周囲
に押し出され、半導体素子３の電極４と配線２は電気的
に接触する。半導体素子３の電極４は、ＡＩ。BACKGROUND ART A conventional technique will be explained with reference to FIG. First, the adhesive 6 is applied to the surface of the wiring board 1 made of ceramic, glass, glass epoxy, etc., on which the wiring 2 is provided. Wiring 2 is C
r-Au, Al, Cu, ITO, etc., and the adhesive 6 is
Thermosetting or ultraviolet curing epoxy, silicone,
It is a resin such as acrylic. Next, the electrode 4 of the semiconductor element 3
are aligned with the conductor wiring 2, and the semiconductor element 3 is pressurized and pressed against the wiring board 1. At this time, the adhesive 5 on the wiring 2 is pushed out to the periphery, and the electrode 4 of the semiconductor element 3 and the wiring 2 are brought into electrical contact. The electrode 4 of the semiconductor element 3 is made of AI.

Ａｕ、Ｃｕ等であり、接着剤５が樹脂である為、膨張係
数は、接着剤６より半導体素子３の電極４のほうが小さ
い。次に、半導体素子３を加圧した状態で接着剤６を硬
化させ、その後加圧を解除し、半導体素子３を配線基板
に固着する。この時、半導体素子３の電極４と配線２は
接着剤５の接着力により電気的に接触した状態を保持す
ることができるものである。Since the adhesive 5 is a resin, the expansion coefficient of the electrode 4 of the semiconductor element 3 is smaller than that of the adhesive 6. Next, the adhesive 6 is cured while applying pressure to the semiconductor element 3, and then the pressure is released to fix the semiconductor element 3 to the wiring board. At this time, the electrode 4 of the semiconductor element 3 and the wiring 2 can be kept in electrical contact with each other due to the adhesive force of the adhesive 5.

、発明が解決しようとする問題点 以上の様に従来の技術では、半導体素子の電極を基板の
配線に直接接触させる方法である為、多端子、狭ピッチ
の半導体素子のパッケージングに有利な方法であるが、
接着剤６が樹脂である為、その膨張係数が半導体素子の
電極４のそれよりも大きい為、次に示す問題点がある。, Problems to be Solved by the Invention As mentioned above, in the conventional technology, the electrodes of the semiconductor element are brought into direct contact with the wiring on the substrate, so this method is advantageous for packaging multi-terminal, narrow-pitch semiconductor elements. In Although,
Since the adhesive 6 is a resin, its coefficient of expansion is larger than that of the electrode 4 of the semiconductor element, resulting in the following problems.

（１）高温時に、樹脂の厚み方向での膨張が生じ、半導
体素子の電極と基板の導体配線との間にギャップが生じ
て導通不良となり、非常に耐熱性の低いものである。(1) At high temperatures, the resin expands in the thickness direction, creating gaps between the electrodes of the semiconductor element and the conductor wiring of the substrate, resulting in poor conductivity, resulting in extremely low heat resistance.

問題点を解決するための手段 本発明では、上記問題点を解決する為に半導体素子の電
極の膨張係数よりも、半導体素子の固着に用いる絶縁性
接着剤の膨張係数を小さくした構成とするものである。Means for Solving the Problems In the present invention, in order to solve the above problems, the expansion coefficient of the insulating adhesive used for fixing the semiconductor element is made smaller than the expansion coefficient of the electrode of the semiconductor element. It is.

作　　用 半導体素子の電極よｐ、絶縁性接着剤の膨張係数？小さ
くすることにより、高温時において接着剤が膨張しても
それ以上に半導体素子の電極が膨張する為導通不良が生
じないものである。What is the electrode of the working semiconductor element, p, and the expansion coefficient of the insulating adhesive? By making the size small, even if the adhesive expands at high temperatures, the electrodes of the semiconductor element will expand even more, so poor conductivity will not occur.

実施例 本発明の一実施例を第１図と共に説明する。まず、第１
図ａに示す様に、セラミック、ガラス等よりなる配線基
板１１の後に半導体素子が固着される領域に、導体配線
１２を含んで、接着剤１５を塗布する。導体配線１２は
、Ｃｒ−へＵ、へｄ、Ｃｕ。Embodiment An embodiment of the present invention will be described with reference to FIG. First, the first
As shown in FIG. 1A, an adhesive 15 is applied to a region of a wiring board 11 made of ceramic, glass, etc., to which a semiconductor element is to be fixed, including conductor wiring 12. As shown in FIG. The conductor wiring 12 is Cr- to U, to d, to Cu.

Ｉ　Ｔｏ　　ｌ　タ／　クス７　／　、Ａｇ／Ｐ　ｄ　
等テアＤ、ソノ厚みは、０．１μ〜５０μ程度である。I To l Ta / Cus 7 / , Ag / P d
The equal tear D and thickness are approximately 0.1 μm to 50 μm.

接着剤１６は後に固着する半導体素子の電極に比べ、膨
張係数の小さい材料を選択する。例えば、Ｓ　１０２を
有機溶剤に溶かしたＳ　ｉ　Ｏ２被膜形成用塗布液を用
いる。これによシ形成したＳ　ｉＯ２膜の膨張係数は６
ｘ１ｏ　　１．／”Ｃ程度であり、半導体素子の電極よ
りも十分小さい値である。接着剤１５の塗布方法は、デ
ィスペンサー等を用いる。For the adhesive 16, a material with a smaller coefficient of expansion than the electrodes of the semiconductor element to be fixed later is selected. For example, a coating liquid for forming a SiO2 film in which S102 is dissolved in an organic solvent is used. The expansion coefficient of the SiO2 film thus formed is 6.
x1o 1. /''C, which is sufficiently smaller than the electrode of the semiconductor element. The adhesive 15 is applied using a dispenser or the like.

次に、第１図すに示す様に、半導体素子１３の電極１４
と配ａ１２を一致させ半導体素子１３を配線基板１１に
加圧ツール１６により加圧する。Next, as shown in FIG.
The semiconductor element 13 is pressed against the wiring board 11 by the pressing tool 16 with the alignment a12 aligned with that of the semiconductor element 13.

この時、配線１２上の接着剤１６は、周囲に押し出され
、半導体素子１３の電極１４と配線１２は電気的に接触
する。次に加圧した状態で、接着剤１６を硬化する。硬
化の方法は、接着剤１６が前記したＳ　１０２被膜形成
用塗布液の場合は、加熱硬化型である為、加圧ツール１
６に加熱部を設け、３００’Ｃ〜４００’Ｃの加熱で硬
化することができる。半導体素子１３の電極１４の厚み
は、０．６μ〜３０μ程度であり、材料はＡｌｌ　、　
Ｃｕ　、　Ａｕ　、　ＰｂＡｎ半田等である。これらの
材料の膨張係数は、１．４Ｘ１０　１／’Ｃ〜２．Ｅｉ
　Ｘ　１０１．／’Ｃであり、接着剤１５の膨張係数よ
りも十分小さい値である。At this time, the adhesive 16 on the wiring 12 is pushed out to the periphery, and the electrode 14 of the semiconductor element 13 and the wiring 12 come into electrical contact. Next, the adhesive 16 is cured under pressure. The curing method is as follows: If the adhesive 16 is the S102 coating liquid for film formation, it is a heat curing type, so the pressure tool 1 is used.
6 is provided with a heating section, and can be cured by heating at 300'C to 400'C. The thickness of the electrode 14 of the semiconductor element 13 is about 0.6μ to 30μ, and the material is All,
These include Cu, Au, PbAn solder, etc. The expansion coefficients of these materials range from 1.4X10 1/'C to 2. Ei
X 101. /'C, which is a value sufficiently smaller than the expansion coefficient of the adhesive 15.

次に、第１図Ｃに示す様に、加圧ツール１６を解除し、
半導体素子１３を配線基板１１に固着する。この時、半
導体素子１３の電極１４は、接着剤１５の接着力により
、配線１２と接触した状態が保持され、電気的な接続を
得るものである。Next, as shown in FIG. 1C, the pressure tool 16 is released,
The semiconductor element 13 is fixed to the wiring board 11. At this time, the electrode 14 of the semiconductor element 13 is kept in contact with the wiring 12 due to the adhesive force of the adhesive 15, thereby obtaining an electrical connection.

発明の効果 以上の様に、本発明では半導体素子の電極を配線基板の
配線に直接接触させて電気的な接続を得る方法である為
、多端子、狭ピッチの半導体素子の接続に非常に有利な
方法でありまた、半導体素子を固着する接着剤の熱膨張
係数を、半導体素子の電極の熱膨張係数よりも小さい構
成としている為、次に示す効果がある。Effects of the Invention As described above, the present invention is a method of obtaining electrical connection by directly contacting the electrodes of the semiconductor element with the wiring of the wiring board, so it is very advantageous for connecting multi-terminal, narrow-pitch semiconductor elements. Moreover, since the coefficient of thermal expansion of the adhesive for fixing the semiconductor element is smaller than the coefficient of thermal expansion of the electrodes of the semiconductor element, it has the following effects.

（１）高温時において、熱膨張量が接着剤より半導体素
子の電極のほうが多い為、半導体素子の電極と配線基板
の配線とは接触した状態が保持され、信頼性が著しく向
上する。(1) At high temperatures, the amount of thermal expansion of the electrodes of the semiconductor element is greater than that of the adhesive, so the electrodes of the semiconductor element and the wiring of the wiring board are maintained in contact with each other, significantly improving reliability.

（２）　　（１）の理由により、大電力用や使用温度の
高い電装品への適用も可能となり、適用範囲が広がる。(2) Due to the reason in (1), it can be applied to electrical components that use high power or have high operating temperatures, expanding the range of application.

【図面の簡単な説明】 第１図は本発明の一実施例の工程別断面図、第２図は従
来の技術を示す断面図である。 １１゜・・・・・・配線基板、１２・・・・・・配線、
１３・・・・・半導体素子、１４・・・・・・半導体素
子の電極、１Ｓ・・・・・・接着剤、１６・・・・・・
加圧ツール。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing each step of an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a conventional technique. 11゜...Wiring board, 12...Wiring,
13... Semiconductor element, 14... Electrode of semiconductor element, 1S... Adhesive, 16...
Pressure tool.

Claims (2)

【特許請求の範囲】[Claims] （１）絶縁性基板の導体配線を有する面に、半導体素子
の電極を有する面を、前記導体配線と半導体素子の電極
が一致する様に前記半導体素子と絶縁基板間に形成され
た絶縁性接着剤により固着し、前記半導体素子の電極と
前記導体配線が接触により電気的に接続されており、前
記絶縁性接着剤の膨張係数が前記半導体素子の電極より
小さいことを特徴とする半導体装置。(1) Insulating adhesive formed between the semiconductor element and the insulating substrate such that the surface having the electrode of the semiconductor element is aligned with the surface having the conductor wiring of the insulating substrate, and the conductor wiring and the electrode of the semiconductor element are aligned. A semiconductor device, wherein the electrodes of the semiconductor element and the conductor wiring are electrically connected by contact, and the expansion coefficient of the insulating adhesive is smaller than that of the electrodes of the semiconductor element. （２）半導体素子の電極が突起電極であることを特徴と
する特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the electrode of the semiconductor element is a protruding electrode.
JP12393286A 1986-05-29 1986-05-29 Semiconductor device Expired - Lifetime JPH0752741B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12393286A JPH0752741B2 (en) 1986-05-29 1986-05-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12393286A JPH0752741B2 (en) 1986-05-29 1986-05-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62281361A true JPS62281361A (en) 1987-12-07
JPH0752741B2 JPH0752741B2 (en) 1995-06-05

Family

ID=14872917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12393286A Expired - Lifetime JPH0752741B2 (en) 1986-05-29 1986-05-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0752741B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321239A2 (en) * 1987-12-17 1989-06-21 Matsushita Electric Industrial Co., Ltd. Fabricating method of semiconductor device
JPH01244627A (en) * 1988-03-25 1989-09-29 Matsushita Electric Ind Co Ltd Method of mounting semiconductor device
JPH02185050A (en) * 1989-01-12 1990-07-19 Matsushita Electric Ind Co Ltd Mounting method for semiconductor device
US5021888A (en) * 1987-12-18 1991-06-04 Kabushiki Kaisha Toshiba Miniaturized solid state imaging device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321239A2 (en) * 1987-12-17 1989-06-21 Matsushita Electric Industrial Co., Ltd. Fabricating method of semiconductor device
US5021888A (en) * 1987-12-18 1991-06-04 Kabushiki Kaisha Toshiba Miniaturized solid state imaging device
JPH01244627A (en) * 1988-03-25 1989-09-29 Matsushita Electric Ind Co Ltd Method of mounting semiconductor device
JPH02185050A (en) * 1989-01-12 1990-07-19 Matsushita Electric Ind Co Ltd Mounting method for semiconductor device

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