JPH0482241A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0482241A JPH0482241A JP19663890A JP19663890A JPH0482241A JP H0482241 A JPH0482241 A JP H0482241A JP 19663890 A JP19663890 A JP 19663890A JP 19663890 A JP19663890 A JP 19663890A JP H0482241 A JPH0482241 A JP H0482241A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- board
- insulating resin
- semiconductor element
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 229920005989 resin Polymers 0.000 claims abstract description 54
- 239000011347 resin Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims 4
- 230000005611 electricity Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 12
- 238000011084 recovery Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 229920001187 thermosetting polymer Polymers 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 230000005489 elastic deformation Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241001092070 Eriobotrya Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 235000013305 food Nutrition 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置 特に多端子、狭チップのＩＣ，Ｌ
ＳＩのパッケージング構造に関するものであ４
従来の技術
従来の技術を第３＠ 第４図と共に説明する。[Detailed Description of the Invention] Industrial Field of Application The present invention relates to semiconductor devices, particularly multi-terminal, narrow chip ICs, L
This relates to the packaging structure of SI. 4. Prior Art The conventional technology will be explained with reference to FIG. 3@FIG.
まず第３図（ａ＞の様にセラミツ久 ガラ入 ガラスエ
ポキシ等よりなる配線基板１の基材２の基板配線３を有
する面に 接着用絶縁性樹脂４を塗布すム 基板配線３
はＣｒ−Ａｕ、 Ａ４． Ｃｕ、 ＩＴＯ等であ
りスパッタリング汰 蒸着法により基板配線用金属を形
成した後フォト・レジスト法によりレジストを基板配線
を形成する部分に残し基板配線用金属をエツチングする
力＼ 又は印刷法を用い形成する。絶縁性樹脂４は紫外
線硬化型又は熱硬化型のエポキシ、シリコーン、アクリ
ル等の樹脂であム
次に第３図（ｂ）の様に半導体素子５の突起電極６を基
板配線３と一致させ、半導体素子５を加圧し配線基板１
の基材２に押し当ても この時の突起電極６近傍の状態
は第４図の様に 半導体素子５のアルミ電極７上に電気
めっき法等により形成したＡｕ、Ａｇ、Ｃｕより成る突
起電極６（よ 配線基板１の基板配線３に押し当てられ
て突起電極６と基板配線３の間の紫外線硬化型あるいは
熱硬化型の接着用絶縁性樹脂４は押し出され突起電極６
と基板配線３は電気的な接続を得も
次に 半導体素子５を加圧した状態で接着用絶縁性樹脂
４を紫外線硬化型ならば紫外線を加え熱硬化型ならば熱
を加え硬化させ、その後加圧を解除し半導体素子５を配
線基板１に固着する。この時、半導体素子５の突起電極
６と基板配線３は紫外線硬化型或は熱硬化型の接着用絶
縁性樹脂４の収縮力により、電気的に接触した状態を保
持することが出来ると言うものであっち
発明が解決しようとする課題
以上の様に 従来の技術では半導体素子の突起電極と基
板配線の接続に紫外線硬化型あるいは熱硬化型の絶縁性
樹脂を用いる方式である八 次の様な課題がある。First, as shown in FIG. 3 (a), an insulating adhesive resin 4 is applied to the surface of the base material 2 of the wiring board 1 made of ceramic glass epoxy or the like having the board wiring 3.
is Cr-Au, A4. It is made of Cu, ITO, etc., and is formed using a sputtering method.After forming the metal for the board wiring by vapor deposition method, a resist is left on the part where the board wiring is to be formed by the photoresist method, and the metal for the board wiring is etched by the force or printing method. . The insulating resin 4 is an ultraviolet curing or thermosetting resin such as epoxy, silicone, or acrylic. Next, as shown in FIG. 3(b), the protruding electrodes 6 of the semiconductor element 5 are aligned with the substrate wiring 3, The semiconductor element 5 is pressurized and the wiring board 1
At this time, the state near the protruding electrode 6 is as shown in FIG. (When pressed against the board wiring 3 of the wiring board 1, the ultraviolet curing or thermosetting adhesive insulating resin 4 between the protruding electrode 6 and the board wiring 3 is pushed out and the protruding electrode 6
and the board wiring 3 are electrically connected.Next, with the semiconductor element 5 under pressure, the adhesive insulating resin 4 is cured by applying ultraviolet rays if it is an ultraviolet curing type or by heating if it is a thermosetting type. The pressure is released and the semiconductor element 5 is fixed to the wiring board 1. At this time, the protruding electrodes 6 of the semiconductor element 5 and the substrate wiring 3 can be kept in electrical contact with each other by the contraction force of the ultraviolet curing or thermosetting adhesive insulating resin 4. In addition to the problems that the invention aims to solve, the conventional technology uses an ultraviolet curing type or thermosetting type insulating resin to connect the protruding electrodes of the semiconductor element and the wiring on the board. There is.
高温環境での使用時、又はパワーモジュール等の高発熱
の半導体素子の使用時で（よ 絶縁性樹脂が熱的影響を
受は膨張する。そして、絶縁性樹脂の膨張量が硬化時の
絶縁性樹脂の収縮量を上回ると突起電極と基板配線の間
に間隙が生に 電気的な接続不良が生じる課題があった
この課題は絶縁性樹脂の膨張係数を小さくすることによ
り解決することが出来る力（しかし絶縁性樹脂の膨張係
数を小さくすると、絶縁性樹脂のヤング率は増大し 半
導体素子及び配線基板１に大きなストレスが加わり半導
体素子または配線基板１の破壊が生じると言う課題があ
る。When used in high-temperature environments or when using semiconductor devices that generate high heat such as power modules, insulating resin expands under the influence of heat. If the amount of shrinkage exceeds the shrinkage of the resin, a gap will be created between the protruding electrode and the board wiring, resulting in poor electrical connection.This problem can be solved by reducing the expansion coefficient of the insulating resin. (However, if the coefficient of expansion of the insulating resin is reduced, the Young's modulus of the insulating resin increases, and a large stress is applied to the semiconductor element and the wiring board 1, causing a problem that the semiconductor element or the wiring board 1 may be destroyed.
課題を解決する為の手段
本発明でζよ 上記課題を解決する為に配線基板の基材
と基板配線との間に高弾性率絶縁性樹脂層を形成し半導
体素子の突起電極により基板配線及び絶縁性樹脂層を弾
性変形させた状態で接着用絶縁性樹脂で固着した構成と
するものである。Means for Solving the Problems In order to solve the above problems, a high elastic modulus insulating resin layer is formed between the base material of the wiring board and the board wiring, and the protruding electrodes of the semiconductor element are used to connect the board wiring and The structure is such that the insulating resin layer is elastically deformed and fixed with an adhesive insulating resin.
作用
本発明ζよ 基板配線と配線基板の間の絶縁性樹脂層の
弾性変形を半導体素子の突起電極と基板配線との接続に
利用する方法であるム 半導体素子を加圧したとき、微
少な力で基板配線及び絶縁性樹脂層は変形する。又 絶
縁性樹脂層は高弾性率をもつ絶縁性樹脂を利用する為
容易に弾性回復する。Effects of the present invention ζ This is a method that utilizes the elastic deformation of an insulating resin layer between a board wiring and a wiring board to connect a protruding electrode of a semiconductor element to a board wiring. This deforms the board wiring and the insulating resin layer. In addition, the insulating resin layer uses an insulating resin with a high modulus of elasticity.
Easily recovers elasticity.
そして、この弾性回復により常温環境下においては接着
用絶縁性樹脂の収縮力と絶縁性樹脂層の弾性回復力によ
り半導体素子の突起電極と基板配線は接触し電気的接続
を得る。又 高温環境下においては接着用絶縁性樹脂が
膨張し 膨張量が収縮量を上回る場合でも基板配線と配
線基板の基材との間の絶縁性樹脂層の弾性回復がある八
半導体素子の突起電極と基板配線は接触し電気的接続
を得る。Due to this elastic recovery, the protruding electrodes of the semiconductor element and the substrate wiring come into contact with each other due to the shrinkage force of the adhesive insulating resin and the elastic recovery force of the insulating resin layer in a normal temperature environment to obtain an electrical connection. In addition, the adhesive insulating resin expands in a high-temperature environment, and even if the amount of expansion exceeds the amount of contraction, there is elastic recovery of the insulating resin layer between the board wiring and the base material of the wiring board. and the board wiring come into contact to obtain an electrical connection.
実施例
本発明の一実施例を第１図〜第２図と共に説明する。ま
ず第１図（ａ）の様にセラミツ久 ガラ入ガラスエポキ
シ等よりなる配線基板１０の基材１１の後に半導体素子
１２が固着される領域に基板配線１３及び配線基板１０
の絶縁性樹脂層１４を含み接着用絶縁性樹脂１５を塗布
する。この時、基板配線１３及び配線基板１０の絶縁性
樹脂層１４は次の様にして形成する。まず、配線基板１
０の基材】１の絶縁性樹脂層１４をスピンナー等を用い
て塗布し 次に基板配線１３としてＣｒ−Ａｕ、 Ａ
Ｉ、 Ｃｕ、 ＩＴＯ等をスパッタリング法蒸着法
により基板配線用金属を配線基板１ｏの基材１１の絶縁
性樹脂層１４の上に堆積した後フォト・リソ技術により
レジストを基板配線１３を形成する部分に残し基板配線
用金属をエツチングする力＼ 又は印刷法等の方法を用
いて形成する。絶縁性樹脂１４はゴム等の樹脂であり、
厚みハ０゜１〜５０μｍ程度である。又 接着用絶縁性
樹脂１５は紫外線硬化型又は熱硬化型のゴム エポキシ
、シリコーン、アクリルポリイミド等の樹脂であり、厚
みは０．５〜５０μｍ程度である。Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2. First, as shown in FIG. 1(a), after the base material 11 of the wiring board 10 made of ceramic glass epoxy or the like, the wiring board 13 and the wiring board 10 are placed in the area where the semiconductor element 12 is fixed.
Insulating resin layer 14 is coated with insulating resin 15 for adhesion. At this time, the board wiring 13 and the insulating resin layer 14 of the wiring board 10 are formed as follows. First, wiring board 1
0 base material] The insulating resin layer 14 of 1 is applied using a spinner, etc., and then Cr-Au, A
After depositing I, Cu, ITO, etc. on the insulating resin layer 14 of the base material 11 of the wiring board 1o by sputtering or vapor deposition, a resist is applied to the portion where the board wiring 13 is to be formed by photolithography. It is formed using a method such as a force that etches the metal for wiring on the board or a printing method. The insulating resin 14 is a resin such as rubber,
The thickness is about 0°1 to 50 μm. The adhesive insulating resin 15 is an ultraviolet curing or thermosetting resin such as rubber epoxy, silicone, or acrylic polyimide, and has a thickness of about 0.5 to 50 μm.
次に第１図（ｂ）の様に半導体素子１２の突起電極１６
を基板配線１３と一致させ、半導体素子１２を加圧し
配線基板１０の基材１１に押し当てる。Next, as shown in FIG. 1(b), the protruding electrode 16 of the semiconductor element 12 is
is aligned with the board wiring 13, and the semiconductor element 12 is pressurized.
It is pressed against the base material 11 of the wiring board 10.
この時の突起電極１６近傍の状態は第２図（ａ）の様に
半導体素子１２のアルミ電極１７上に電気めっき法等
により形成したＡｕ、Ａｇ、Ｃｕより成る突起電極１６
は 配線基板１０の基材１１の基板配線１３に押し当て
られて突起電極１６と基板配線１３の間の紫外線硬化型
あるいは熱硬化型の接着用絶縁性樹脂１５は押し出され
突起電極１６と基板配線１３は電気的な接続を得る。そ
して、この時、突起電極１６により基板配線１３と絶縁
性樹脂層１４は押され凹形状に弾性変形する。従来は配
線基板の絶縁性樹脂層が無い八 基板配線と半導体素子
の突起電極の接続は接着用絶縁性樹脂の収縮力のみを使
用したものであツ九次に第１図（ｂ）に示す様に半導体
素子１２を加圧し 基板配線１３と絶縁性樹脂層１４の
変形を保持した状態で接−着用絶縁性樹脂１５を紫外線
硬化型ならば紫外線を加え熱硬化型ならば熱を加え硬化
させ、その後加圧を解除し半導体素子１２を配線基板１
０の基材１１に固着する。この時、半導体素子１２の突
起電極１６と基板配線１３は常温において（よ 第２図
（ａ）に示す様に紫外線硬化型或は熱硬化型の接着用絶
縁性樹脂１５の収縮力Ｓと基板配線１３と絶縁性樹脂層
１４の変形により発生する弾性回復力りが働くた臥 電
気的に接触した状態を保持することが出来る。又 高温
において接着用絶縁性樹脂１５が第２図（ｂ）に示す様
に接着用絶縁性樹脂１５の初期厚ＬＯが△Ｌだけ膨張し
たとしたとしてＬ 基板配線１３と絶縁性樹脂層１４の
弾性回復可能量Ｌｄを△Ｌより大きくすることにより基
板配線１３と突起電極１６は接触を保持し電気的な接続
を保つ。At this time, the state near the protruding electrode 16 is as shown in FIG.
When pressed against the board wiring 13 of the base material 11 of the wiring board 10, the ultraviolet curing or thermosetting adhesive insulating resin 15 between the protruding electrode 16 and the board wiring 13 is pushed out, and the protruding electrode 16 and the board wiring are pushed out. 13 obtains electrical connection. At this time, the substrate wiring 13 and the insulating resin layer 14 are pushed by the protruding electrode 16 and are elastically deformed into a concave shape. Conventionally, there was no insulating resin layer on the wiring board, and the connection between the board wiring and the protruding electrodes of the semiconductor element was made using only the shrinkage force of the insulating adhesive resin, as shown in Figure 1 (b). Pressure is applied to the semiconductor element 12 as shown in FIG. Then, the pressure is released and the semiconductor element 12 is attached to the wiring board 1.
0 base material 11. At this time, the protruding electrodes 16 of the semiconductor element 12 and the substrate wiring 13 are bonded at room temperature (as shown in FIG. Since the elastic recovery force generated by the deformation of the wiring 13 and the insulating resin layer 14 acts, the state of electrical contact can be maintained.Furthermore, the insulating resin 15 for adhesion can be bonded at high temperatures as shown in FIG. 2(b). As shown in , assuming that the initial thickness LO of the adhesive insulating resin 15 expands by ΔL, the board wiring 13 is expanded by making the elastic recovery amount Ld of the board wiring 13 and the insulating resin layer 14 larger than ΔL. The protruding electrode 16 maintains contact and maintains electrical connection.
発明の効果
以上の様に本発明では配線基板の絶縁性樹脂層の上に基
板配線を形成した配線基板を用（＼ 基板配線と絶縁性
樹脂層の弾性回復を基板配線と突起電極との接触に利用
する方法であるム 高温環境下で接続用絶縁性樹脂が膨
張してＬ 基板配線と絶縁性樹脂層の弾性回復量を接続
用絶縁性樹脂の膨張量より大きくすることにより、基板
配線と半導体素子の突起電極は接触し電気的な接続を保
つので、高温環境下での信頼性に非常に有利な方法であ
る。Effects of the Invention As described above, the present invention uses a wiring board in which the board wiring is formed on the insulating resin layer of the wiring board. This is a method used to increase the elasticity of the insulating resin for connection in a high-temperature environment. Since the protruding electrodes of the semiconductor element make contact and maintain electrical connection, this method is very advantageous for reliability in high-temperature environments.
又、配線基板側の弾性回復を利用する方法であるム 絶
縁性樹脂層が配線基板の基材と基板配線との間にあるこ
とで、配線基板の弾性回復 すなわち基板配線と絶縁性
樹脂層の弾性回復を引きおこす弾性変形を低加重で作り
出すことが可能であり、次の様な効果がある。In addition, this is a method that utilizes the elastic recovery of the wiring board side. By having an insulating resin layer between the base material of the wiring board and the board wiring, the elastic recovery of the wiring board, that is, the elastic recovery of the wiring board and the insulating resin layer is suppressed. It is possible to create elastic deformation that causes elastic recovery with a low load, and has the following effects.
（１）半導体素子へ加わる加重が減り、半導体素子の信
頼性が向上する。(1) The load applied to the semiconductor device is reduced, and the reliability of the semiconductor device is improved.
（２）低加重で接続出来ることか仮 加圧装置の小型化
及び低コスト化が計れも(2) Is it possible to connect with a low load? It is possible to make the pressurizing device smaller and lower in cost.
第１図は本発明の一実施例の工程別断面云 第２図は本
発明の接続状態を示す断面医 第３図は従来の技術を示
す工程別断面医 第４図は従来の技術の突起電極近傍の
断面拡大図である。
１．１０．、、配線基板、５．１２．、、半導体素子、
２，１１．、、基材、６，１６．、、突起電極 ３，１
３．、、基板配線 ７．１７．。
、アルミ電！ ４，１５．、、接着用絶縁性樹脂 １
４．、、絶縁性樹脂層
代理人の氏名 弁理士 粟野 重孝 はか１名Ｉ仁ｕＩ
ｔ基板
１５−撞１用杷曝＋ｉ劉Ｂ１
ｌ６゛ 灸起１ｆ！＋糧
ｔａ−ｇｏ 瓦 ツ −ル
第 １１１１
１り
Ｉ乙ＩＩｋ基扱
基材
基板配球
６ 矢起； ［！
７゛フルミｔ＆
δ ｇｏ反ソーＪしFig. 1 is a cross-sectional view of an embodiment of the present invention by process. Fig. 2 is a cross-sectional view showing the connection state of the present invention. Fig. 3 is a cross-sectional view of a conventional technique by process. Fig. 4 is a protrusion of the conventional technology. FIG. 3 is an enlarged cross-sectional view of the vicinity of the electrode. 1.10. ,,wiring board, 5.12. ,, semiconductor device,
2,11. ,, base material, 6,16. ,,protrusion electrode 3,1
3. ,, Board wiring 7.17. . , aluminum electric! 4,15. ,,Insulating resin for adhesion 1
4. ,, Name of agent for insulating resin layer Patent attorney Shigetaka Awano
t substrate 15-1 for loquat exposure + i Liu B1 16゛ moxibustion 1f! + Food Ta-go Kawara Tool No. 1111 1st I Ots IIk Basic Handling Base Material Substrate Distribution Ball 6 Yagi; [! 7゛Furumi t & δ go anti-so J
Claims (1)
有する配線基板の前記導体配線と、半導体素子の突起電
極が合致し、前記突起電極が合致した部分の前記導体配
線及び樹脂層を凹となる様に弾性変形し、且つ前記半導
体素子と前記配線基板の間に介在した接着用絶縁性樹脂
により、前記半導体素子が前記配線基板に固着されると
ともに前記半導体素子の突起電極と導体配線が電気的に
接続されていることを特徴とする半導体装置。The conductor wiring of a wiring board having conductor wiring on at least one surface of the base material via a resin layer matches the protruding electrode of the semiconductor element, and the conductor wiring and resin layer in the part where the protruding electrode matches are made into a recess. The adhesive insulating resin, which is elastically deformed and interposed between the semiconductor element and the wiring board, fixes the semiconductor element to the wiring board, and connects the protruding electrodes of the semiconductor element and the conductor wiring with electricity. A semiconductor device characterized in that it is connected to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19663890A JP2502794B2 (en) | 1990-07-24 | 1990-07-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19663890A JP2502794B2 (en) | 1990-07-24 | 1990-07-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0482241A true JPH0482241A (en) | 1992-03-16 |
| JP2502794B2 JP2502794B2 (en) | 1996-05-29 |
Family
ID=16361100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19663890A Expired - Lifetime JP2502794B2 (en) | 1990-07-24 | 1990-07-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2502794B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270496A (en) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof |
| US5874780A (en) * | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
| US5959362A (en) * | 1996-06-13 | 1999-09-28 | Nec Corporation | Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics |
| WO2000019516A1 (en) * | 1998-09-30 | 2000-04-06 | Seiko Epson Corporation | Semiconductor device, connection method for semiconductor chip, circuit board and electronic apparatus |
| US6133066A (en) * | 1996-08-01 | 2000-10-17 | Nec Corporation | Semiconductor element mounting method |
| WO2002078079A1 (en) * | 2001-03-26 | 2002-10-03 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| SG108931A1 (en) * | 2002-09-02 | 2005-02-28 | Murata Manufacturing Co | Mounting board and electronic device using the same |
| US8035202B2 (en) | 2003-10-06 | 2011-10-11 | Nec Corporation | Electronic device having a wiring substrate |
| US8080447B2 (en) | 2004-09-15 | 2011-12-20 | Seiko Epson Corporation | Method of manufacturing semiconductor device including exposing a dicing line on a wafer |
-
1990
- 1990-07-24 JP JP19663890A patent/JP2502794B2/en not_active Expired - Lifetime
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874780A (en) * | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
| US6449838B2 (en) | 1995-07-27 | 2002-09-17 | Nec Corporation | Method of mounting a semiconductor device to a substrate |
| US5959362A (en) * | 1996-06-13 | 1999-09-28 | Nec Corporation | Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics |
| US6063649A (en) * | 1996-06-13 | 2000-05-16 | Nec Corporation | Device mounting a semiconductor element on a wiring substrate and manufacturing method thereof |
| US6133066A (en) * | 1996-08-01 | 2000-10-17 | Nec Corporation | Semiconductor element mounting method |
| JPH10270496A (en) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof |
| US6410364B1 (en) | 1998-09-30 | 2002-06-25 | Seiko Epson Corporation | Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment |
| WO2000019516A1 (en) * | 1998-09-30 | 2000-04-06 | Seiko Epson Corporation | Semiconductor device, connection method for semiconductor chip, circuit board and electronic apparatus |
| US6656771B2 (en) | 1998-09-30 | 2003-12-02 | Seiko Epson Corporation | Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment |
| WO2002078079A1 (en) * | 2001-03-26 | 2002-10-03 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| US7053479B2 (en) | 2001-03-26 | 2006-05-30 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| SG108931A1 (en) * | 2002-09-02 | 2005-02-28 | Murata Manufacturing Co | Mounting board and electronic device using the same |
| US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
| US8035202B2 (en) | 2003-10-06 | 2011-10-11 | Nec Corporation | Electronic device having a wiring substrate |
| US8080447B2 (en) | 2004-09-15 | 2011-12-20 | Seiko Epson Corporation | Method of manufacturing semiconductor device including exposing a dicing line on a wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2502794B2 (en) | 1996-05-29 |
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