JPH1187429A - Mounting method for semiconductor chip - Google Patents

Mounting method for semiconductor chip

Info

Publication number
JPH1187429A
JPH1187429A JP12200598A JP12200598A JPH1187429A JP H1187429 A JPH1187429 A JP H1187429A JP 12200598 A JP12200598 A JP 12200598A JP 12200598 A JP12200598 A JP 12200598A JP H1187429 A JPH1187429 A JP H1187429A
Authority
JP
Japan
Prior art keywords
semiconductor chip
anisotropic conductive
circuit board
conductive adhesive
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12200598A
Other languages
Japanese (ja)
Inventor
Makoto Watanabe
真 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP12200598A priority Critical patent/JPH1187429A/en
Publication of JPH1187429A publication Critical patent/JPH1187429A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494Heating methods for reflowing of solder

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability by suppressing production of bubble and increasing the bonding power in the case of mounting a semiconductor chip onto a circuit board through an anisotropic conductive thereby preventing a thermal strain from being developed in the semiconductor chip and the circuit board. SOLUTION: After an anisotropic conductive adhesive 18 is applied onto a circuit board 12, the circuit board 12 is heated temporarily at a temperature lower than the curing temperature of the anisotropic conductive adhesive 18 by means of a heating jig 20. Subsequently, a semiconductor chip 13 is set on the circuit board 12 and thermocompression-bonded by means of a hot press 19 thus curing the anisotropic conductive adhesive 18. Generation of thermal strain can be prevented by heating the circuit board 12 also from the lower surface side at a temperature lower than the heating temperature of the semiconductor chip 13.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、突起電極を設け
た半導体チップを配線パターンを形成した回路基板に実
装する半導体チップの実装方法に関し、特に異方性導電
接着剤を用いてその半導体の突起電極と回路基板上の配
線パターンとを接続すると共に、半導体チップを回路基
板に固着する実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method for mounting a semiconductor chip provided with protruding electrodes on a circuit board on which a wiring pattern is formed, and more particularly to a method of mounting a semiconductor chip using an anisotropic conductive adhesive. The present invention relates to a mounting method for connecting an electrode to a wiring pattern on a circuit board and fixing a semiconductor chip to the circuit board.

【0002】[0002]

【従来の技術】例えば、液晶パネルのガラス基板上に液
晶駆動用の半導体チップ(デバイス)を異方性導電接着剤
を用いて実装する方法が実用化されている。このような
従来の半導体チップの実装方法について、図5の平面図
とそのA−A線に沿う断面図である図6と、半導体チッ
プを実装する際の各工程を示す図6と同様な断面図であ
る図7とを用いて説明する。
2. Description of the Related Art For example, a method of mounting a semiconductor chip (device) for driving a liquid crystal on a glass substrate of a liquid crystal panel using an anisotropic conductive adhesive has been put to practical use. FIG. 6 is a plan view of FIG. 5 and a cross-sectional view taken along the line AA of FIG. 5, and FIG. 6 is a cross-sectional view showing each step of mounting the semiconductor chip. This will be described with reference to FIG.

【0003】液晶表示装置は、図5に示すように、液晶
パネルの回路基板である第1の基板11と第2の基板1
2の余白部16,16に液晶表示部への信号を送るため
の配線パターン15が形成されていて、その上に複数の
液晶駆動用の半導体チップ13を搭載する構成になって
いる。その配線パターン15の材料としては、透明導電
膜である酸化インジュウムスズ(ITO)膜や酸化スズ
膜を用いている。
As shown in FIG. 5, a liquid crystal display device has a first substrate 11 and a second substrate 1 which are circuit substrates of a liquid crystal panel.
A wiring pattern 15 for transmitting a signal to the liquid crystal display unit is formed in the margins 16 and 16, and a plurality of liquid crystal driving semiconductor chips 13 are mounted thereon. As a material of the wiring pattern 15, an indium tin oxide (ITO) film or a tin oxide film which is a transparent conductive film is used.

【0004】それぞれ配線パターン15が形成された基
板11,12の余白部16に搭載すされる半導体チップ
13は、図6に示すように異方性導電接着剤18によっ
て接着される。その異方性導電接着剤18は、絶縁性の
あるエポキシ系接着剤に導電性を持たせるために、直径
5μm〜10μmの銀または半田などの金属粒子、また
は表面に金メッキを施して導電性を持たせたプラスチッ
ク樹脂粒子等の導電粒子18aを混入したものである。
The semiconductor chips 13 mounted on the margins 16 of the substrates 11 and 12 on which the wiring patterns 15 are respectively formed are adhered by an anisotropic conductive adhesive 18 as shown in FIG. The anisotropic conductive adhesive 18 is made of metal particles such as silver or solder having a diameter of 5 μm to 10 μm, or gold-plated on the surface in order to impart conductivity to an insulating epoxy adhesive. It is obtained by mixing conductive particles 18a such as plastic resin particles.

【0005】そして、配線パターン15と半導体チップ
13に設けられた突起電極14との間に、異方性導電接
着剤18中に含まれる導電粒子18aを挟むことによっ
て、両者を導通させる。異方性導電接着剤18として
は、図11に示すように、ベースフィルム181とカバ
ーフィルム182の間に異方性導電フィルム(Anisotro
pic ConductuveFilm:ACF)180を挟んだフィルム
状のものがある。その異方性導電フィルム180は、接
着剤層である熱硬化型エポキシ樹脂中に導電粒子18a
が混入されている。
[0005] The conductive particles 18a contained in the anisotropic conductive adhesive 18 are interposed between the wiring pattern 15 and the protruding electrodes 14 provided on the semiconductor chip 13, so that both are electrically connected. As the anisotropic conductive adhesive 18, as shown in FIG. 11, an anisotropic conductive film (Anisotro conductive film) is provided between the base film 181 and the cover film 182.
pic Conductuve Film (ACF) 180 sandwiches a film. The anisotropic conductive film 180 has conductive particles 18a in a thermosetting epoxy resin as an adhesive layer.
Is mixed in.

【0006】その導電粒子18aは、図12に示すよう
に、直径5μm程度の球形をなし、プラスチックコア1
8a1の表面に金メッキ層18a2が形成され、さらに
その表面が絶縁層18a3で覆われている。したがっ
て、異方性導電フィルム180内で、この導電粒子18
aは互いに絶縁されており、厚さ方向に導電材に挟まれ
て加熱および加圧されると、導電粒子18aの絶縁層1
8a3が破壊されて導通する。他の部分の導電粒子18
aは絶縁層18a3が破壊されないので、異方性導電フ
ィルム180の平面方向には導通しない。
The conductive particles 18a have a spherical shape with a diameter of about 5 μm as shown in FIG.
A gold plating layer 18a2 is formed on the surface of 8a1, and the surface is further covered with an insulating layer 18a3. Therefore, in the anisotropic conductive film 180, the conductive particles 18
a are insulated from each other, and when heated and pressurized by being sandwiched between conductive materials in the thickness direction, the insulating layer 1 of the conductive particles 18a is formed.
8a3 is broken and becomes conductive. Other parts of conductive particles 18
a does not conduct in the plane direction of the anisotropic conductive film 180 because the insulating layer 18a3 is not broken.

【0007】その半導体チップの実装作業の工程は、図
7に示すように、最初の工程1で、基板12の余白部1
6の半導体チップ13を搭載する部分に異方性導電接着
剤18を転写して配置する。
[0007] As shown in FIG. 7, the process of mounting the semiconductor chip is as follows.
The anisotropic conductive adhesive 18 is transferred and arranged on the portion where the semiconductor chip 13 is mounted.

【0008】例えば、図11に示したカバーフィルム1
82をはがして異方性導電フィルム180を基板12上
に貼り付けた後、ベースフィルム181を剥がす。つぎ
に工程2で、半導体チップ13の突起電極14を対向す
る基板12の配線パターン15と位置合わせして、半導
体チップ13を異方性導電接着剤18を介して基板12
上に配置する。
For example, the cover film 1 shown in FIG.
After peeling off 82 and attaching anisotropic conductive film 180 on substrate 12, base film 181 is peeled off. Next, in step 2, the protruding electrode 14 of the semiconductor chip 13 is aligned with the wiring pattern 15 of the opposing substrate 12, and the semiconductor chip 13 is placed on the substrate 12 via the anisotropic conductive adhesive 18.
Place on top.

【0009】その後工程3で、ヒータ19aを内蔵する
加熱加圧治具19を用いて、半導体チップ13を第2の
基板12に加圧しながら加熱して熱圧着し、異方性導電
接着剤18を硬化させる。
Then, in step 3, the semiconductor chip 13 is heated and thermocompression-bonded to the second substrate 12 by using a heating and pressing jig 19 having a built-in heater 19a. To cure.

【0010】それによって、異方性導電接着剤18が硬
化した工程4では、半導体チップ13は基板12上に接
着され、その半導体チップ13の各突起電極14と基板
12上の配線パターン15との間にそれぞれ複数個ずつ
の導電粒子18aが挟持され、それによって、各突起電
極14と配線パターン15とが導通される。
Thus, in step 4 where the anisotropic conductive adhesive 18 is cured, the semiconductor chip 13 is bonded onto the substrate 12, and each of the bump electrodes 14 of the semiconductor chip 13 and the wiring pattern 15 on the substrate 12 are bonded. A plurality of conductive particles 18a are interposed between each other, whereby each protruding electrode 14 and the wiring pattern 15 are conducted.

【0011】なお、異方性導電接着剤18は絶縁性のあ
るエポキシ系接着剤中に導電粒子18aが分散してお
り、あるいはさらに図11及び図12に示した異方性導
電フィルム180のように導電粒子18aの外周面が絶
縁層18a3によって覆われているので、突起電極14
と配線パターン15との間に挟持された導電粒子18a
以外の導電粒子18aは互いに絶縁されており、突起電
極14同士や配線パターン15間を短絡させるようなこ
とはない。
The anisotropic conductive adhesive 18 has conductive particles 18a dispersed in an insulating epoxy-based adhesive, or further has an anisotropic conductive film 180 as shown in FIG. 11 and FIG. Since the outer peripheral surface of the conductive particles 18a is covered with the insulating layer 18a3,
Conductive particles 18a sandwiched between the wiring pattern 15
The other conductive particles 18a are insulated from each other, and do not short-circuit between the protruding electrodes 14 or between the wiring patterns 15.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体チップの実装方法では、異方性導電接
着剤18を加熱して硬化させる際に、その異方性導電接
着剤18中に含まれる揮発成分(稀釈剤や水分)や巻き
込んだ空気などが、気泡となって半導体チップ13と基
板12の間に発生する。
However, in such a conventional method of mounting a semiconductor chip, when the anisotropic conductive adhesive 18 is cured by heating, it is contained in the anisotropic conductive adhesive 18. Volatile components (diluent and water) and air entrained are generated as bubbles between the semiconductor chip 13 and the substrate 12.

【0013】それによって、図8に示すように、半導体
チップ13と基板12の間の異方性導電接着剤18のエ
ポキシ系接着材の接着面に気泡21が発生する。そのた
め、異方性導電接着剤18のエポキシ系接着材が半導体
チップ13と基板12の間に完全に充填されず、接着力
が低下する。それによって、半導体チップ13と基板1
2の間で剥離が発生し、突起電極14と配線パターン1
5間の導通が断たれることがあるという問題があった。
As a result, as shown in FIG. 8, bubbles 21 are generated on the bonding surface of the epoxy adhesive of the anisotropic conductive adhesive 18 between the semiconductor chip 13 and the substrate 12. Therefore, the epoxy adhesive of the anisotropic conductive adhesive 18 is not completely filled between the semiconductor chip 13 and the substrate 12, and the adhesive strength is reduced. Thereby, the semiconductor chip 13 and the substrate 1
2 between the projection electrode 14 and the wiring pattern 1
There has been a problem that conduction between the wires 5 may be interrupted.

【0014】また、半導体チップ13を基板12に熱圧
着後に、その半導体チップ13と基板12との間に熱歪
みが発生した状態になってしまう。例えば、液晶パネル
の基板12によく用いられるホウケイ酸系のガラス基板
とシリコンが主な構成材料である半導体チップ13の熱
膨張係数を比較すると、ガラス基板の方が熱膨張係数が
大きいので、半導体基板13を基板12に熱圧着して異
方性導電接着剤を硬化させた後、その温度が低下して室
温に戻ったとき、半導体チップ13と基板12の熱膨張
係数の違いにより、それぞれの材料間での縮み量が違っ
てくる。
Further, after the semiconductor chip 13 is thermocompression-bonded to the substrate 12, thermal distortion occurs between the semiconductor chip 13 and the substrate 12. For example, comparing the thermal expansion coefficients of a borosilicate glass substrate, which is often used for the liquid crystal panel substrate 12, and a semiconductor chip 13, which is mainly composed of silicon, the glass substrate has a larger thermal expansion coefficient. After the substrate 13 is thermocompression-bonded to the substrate 12 to cure the anisotropic conductive adhesive, when the temperature decreases and returns to room temperature, due to the difference in the coefficient of thermal expansion between the semiconductor chip 13 and the substrate 12, The amount of shrinkage differs between materials.

【0015】図9に、ホウケイ酸系のガラス基板と半導
体チップの加熱温度に対する熱膨張量を示す。この図に
よると、ホウケイ酸系のガラス基板の熱膨張係数αglas
sは、 αglass=51×10~7/℃ であり、シリコンが主な構成材料である半導体チップの
熱膨張係数αICは、 αIC=24.2×10~7/℃ である。
FIG. 9 shows the amount of thermal expansion of the borosilicate glass substrate and the semiconductor chip with respect to the heating temperature. According to this figure, the thermal expansion coefficient αglas of a borosilicate glass substrate
s is αglass = 51 × 10 ~ 7 / ℃, thermal expansion coefficient ArufaIC semiconductor chip silicon is the main constituent material is a αIC = 24.2 × 10 ~ 7 / ℃.

【0016】すなわち、図5から図7に示した第1,第
2の基板11,12はガラス基板であるから、半導体チ
ップ13のおよそ2倍の熱膨張係数を有する。一般に、
長さが1(m)で熱膨張係数αの材料にΔTの温度差が
かかったとき、その材料の伸び量L(m)は、 L=α×1×ΔT で表わされる。
That is, since the first and second substrates 11 and 12 shown in FIGS. 5 to 7 are glass substrates, they have a thermal expansion coefficient approximately twice that of the semiconductor chip 13. In general,
When a temperature difference of ΔT is applied to a material having a length of 1 (m) and a thermal expansion coefficient α, the elongation L (m) of the material is represented by L = α × 1 × ΔT.

【0017】ここで、210℃で異方性導電接着剤18
を硬化させるとすると、半導体チップ13には250℃
程度の温度をかけなければならない。また、圧着時間は
5秒から10秒である。圧着時間を5秒から10秒とし
たときは、基板12側の温度は100℃程度までしか上
昇しない。
Here, at 210 ° C., the anisotropic conductive adhesive 18
Is cured at 250 ° C.
Temperature must be applied. The pressing time is 5 seconds to 10 seconds. When the pressing time is set to 5 seconds to 10 seconds, the temperature of the substrate 12 increases only to about 100 ° C.

【0018】室温を20℃と仮定した場合に、基板(ガ
ラス基板)12と半導体チップ13に発生する伸び量を
計算する。半導体チップの一辺の長さを15mmとし、
熱膨張による伸びは左右対称に発生するものとして片側
半分について計算すると、このときの基板12の伸び量
は、 (15mm÷2)×51×10~7×(10
0℃−20℃)=0.0030600mm である。
Assuming that the room temperature is 20 ° C., the amount of elongation generated in the substrate (glass substrate) 12 and the semiconductor chip 13 is calculated. The length of one side of the semiconductor chip is 15 mm,
When the elongation due to thermal expansion is calculated symmetrically on one half, the amount of elongation of the substrate 12 at this time is (15 mm ÷ 2) × 51 × 10 × 7 × (10
(0 ° C.-20 ° C.) = 0.030600 mm.

【0019】一方、半導体チップの伸び量は (15mm÷2)×24.2×10~7×(100℃−2
0℃)=0.0041745mm である。したがって基板12と半導体チップ13のずれ
は 0.0041745mm−0.0030600mm=
0.0011145mm となり、約1μm程度基板12の方が多く伸びているこ
とになる。
Meanwhile, the elongation amount of the semiconductor chip (15mm ÷ 2) × 24.2 × 10 ~ 7 × (100 ℃ -2
0 ° C) = 0.0041745 mm 2. Therefore, the deviation between the substrate 12 and the semiconductor chip 13 is 0.0041745 mm−0.0030600 mm =
0.0011145 mm 2, which means that the substrate 12 extends more by about 1 μm.

【0020】この伸びの差が存在した状態で、これらの
材料を温度20℃の室温に戻してそのまま放置しておく
と、基板12と半導体チップ13の接着面(突起電極1
4と配線パターン15の間、半導体チップ13と基板1
2の間)で両者の縮み量の差によって熱歪みが生じた状
態になり、剥離を起こすという問題がある。図10にホ
ウケイ酸系のガラス基板の温度と、液晶駆動用半導体チ
ップを250℃に加熱した場合のガラス基板との歪みを
示す。
When these materials are returned to room temperature of 20 ° C. in a state where the difference in elongation exists, the bonding surface of the substrate 12 and the semiconductor chip 13 (the projecting electrode 1
4 and the wiring pattern 15, the semiconductor chip 13 and the substrate 1
2), there is a problem that thermal distortion occurs due to the difference in shrinkage between the two, and peeling occurs. FIG. 10 shows the temperature of the borosilicate glass substrate and the distortion of the glass substrate when the semiconductor chip for driving a liquid crystal is heated to 250 ° C.

【0021】この発明はこのような従来の異方性導電接
着剤を用いた半導体チップの実装方法における問題点を
解決するためになされたものであり、半導体チップと回
路基板の間の気泡の発生を抑え、あるいは半導体チップ
と回路基板の熱圧着後の縮み量に差が生じないようにし
て、半導体チップの回路基板からの剥離や、突起電極と
配線パターンとの導通不良などが発生しないようにし、
半導体チップの回路基板への信頼性の高い実装を実現す
ることを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the problems in such a conventional method of mounting a semiconductor chip using an anisotropic conductive adhesive. So that there is no difference in the amount of shrinkage between the semiconductor chip and the circuit board after thermocompression bonding, so that the semiconductor chip does not peel off from the circuit board or poor conduction between the protruding electrodes and the wiring pattern does not occur. ,
An object is to realize highly reliable mounting of a semiconductor chip on a circuit board.

【0022】[0022]

【課題を解決するための手段】この発明は上記の目的を
達成するため、前述したような半導体チップの回路基板
への実装方法において、回路基板上に異方性導電接着剤
を配置した後、半導体チップを回路基板に配置する前
に、異方性導電接着剤を配置した回路基板をその異方性
導電接着剤の硬化温度より低い温度で仮加熱することを
特徴とする。
In order to achieve the above object, the present invention provides a method for mounting a semiconductor chip on a circuit board as described above, wherein after arranging an anisotropic conductive adhesive on the circuit board, Prior to placing the semiconductor chip on the circuit board, the circuit board on which the anisotropic conductive adhesive is placed is temporarily heated at a temperature lower than the curing temperature of the anisotropic conductive adhesive.

【0023】このように、異方性導電接着剤を配置した
回路基板を仮加熱することにより、半導体チップの実装
前に異方性導電接着剤中に含まれる揮発成分を揮発さ
せ、半導体チップの熱圧着時に接着剤中に気泡が殆ど発
生しないようにすることができる。したがって、従来の
半導体チップの実装方法と比べて、半導体チップと回路
基板間に発生する気泡量が格段に減少し、信頼性の高い
実装を行なうことができる。
As described above, by temporarily heating the circuit board on which the anisotropic conductive adhesive is disposed, the volatile component contained in the anisotropic conductive adhesive is volatilized before mounting the semiconductor chip, and Almost no air bubbles can be generated in the adhesive during thermocompression bonding. Therefore, compared to the conventional semiconductor chip mounting method, the amount of bubbles generated between the semiconductor chip and the circuit board is remarkably reduced, and highly reliable mounting can be performed.

【0024】この発明はまた、前述のように半導体チッ
プを回路基板に加圧しながら加熱して異方性導電接着剤
を硬化させる工程において、その回路基板を半導体チッ
プを配置した面と反対側の面からも、半導体チップに対
する加熱温度より低い温度で加熱するようにしたことを
特徴とする半導体チップの実装方法も提供する。
According to the present invention, in the step of heating the semiconductor chip while applying pressure to the circuit board to cure the anisotropic conductive adhesive as described above, the circuit board is placed on the side opposite to the surface on which the semiconductor chip is arranged. The present invention also provides a semiconductor chip mounting method characterized in that the semiconductor chip is heated at a temperature lower than the heating temperature for the semiconductor chip.

【0025】このように、回路基板をも加熱してその温
度を調節することにより、回路基板の熱膨張量を半導体
チップの熱膨張量とほぼ同じにすることにより、熱圧着
後に室温に戻る際に回路基板と半導体チップ間で歪みが
発生することがなくなる。したがって、半導体チップの
剥離や突起電極と回路パターンとの導通不良などが発生
することがなくなり、信頼性の高い実装を行なうことが
できる。
As described above, the circuit board is also heated and its temperature is adjusted so that the thermal expansion of the circuit board is substantially equal to the thermal expansion of the semiconductor chip. Therefore, no distortion occurs between the circuit board and the semiconductor chip. Accordingly, peeling of the semiconductor chip and poor conduction between the protruding electrode and the circuit pattern do not occur, and highly reliable mounting can be performed.

【0026】前述の異方性導電接着剤を配置した回路基
板をその異方性導電接着剤の硬化温度より低い温度で仮
加熱することと、上記異方性導電接着剤を硬化させる工
程において、回路基板を半導体チップを配置した面と反
対側の面からも、半導体チップに対する加熱温度より低
い温度で加熱することの両方を行なうことにより、気泡
の発生を殆どなくすと共に、回路基板と半導体チップ間
での歪みの発生も防ぎ、一層信頼性の高い実装を実現す
ることができる。
In the step of temporarily heating the circuit board on which the anisotropic conductive adhesive is arranged at a temperature lower than the curing temperature of the anisotropic conductive adhesive, and the step of curing the anisotropic conductive adhesive, The circuit board is also heated from a surface opposite to the surface on which the semiconductor chip is arranged, at a temperature lower than the heating temperature for the semiconductor chip, so that generation of air bubbles is almost eliminated, and between the circuit board and the semiconductor chip. In this case, the occurrence of distortion can be prevented, and more reliable mounting can be realized.

【0027】[0027]

【発明の実施の形態】以下、この発明による半導体チッ
プの実装方法の実施形態を、図面に基づいて説明する。
以下の実施形態の説明では、図5乃至図7によって説明
した従来例と同様に、液晶パネルのガラス基板への液晶
駆動用の半導体チップ(デバイス)の実装方法を例にして
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for mounting a semiconductor chip according to the present invention will be described below with reference to the drawings.
In the following description of the embodiment, a method of mounting a semiconductor chip (device) for driving a liquid crystal on a glass substrate of a liquid crystal panel will be described as an example, similarly to the conventional example described with reference to FIGS.

【0028】図1は、この発明による半導体チップの実
装方法の第1の実施形態の各工程を示す図7と同様な断
面図であり、図7と同じ部分には同一の符号を付してあ
る。まず図1に示す最初の工程1で、液晶パネルの回路
基板である第2の基板(以下単に「基板」という)12
の余白部16の半導体チップ13を搭載する位置に、異
方性導電接着剤18を配置する。
FIG. 1 is a sectional view similar to FIG. 7 showing each step of the first embodiment of the method of mounting a semiconductor chip according to the present invention, and the same parts as those in FIG. is there. First, in a first step 1 shown in FIG. 1, a second substrate (hereinafter simply referred to as “substrate”) 12 which is a circuit substrate of a liquid crystal panel
The anisotropic conductive adhesive 18 is arranged in the margin 16 at a position where the semiconductor chip 13 is mounted.

【0029】この異方性導電接着剤18の配置は、図1
1に示した異方性導電フィルム(ACF)を貼り付けて
転写するとよいが、ペースト状のものを印刷したり、温
度80℃から100℃に加熱した加熱ヘッドを使用し、
ディスペンサ・ロボットによって塗布したりすることも
できる。この異方性導電接着剤18は、厚さ20μmか
ら100μmの膜厚で、実装する半導体チップ13と同
じ大きさか、その外形より2mm程度大きい範囲に転写
する。
The arrangement of the anisotropic conductive adhesive 18 is shown in FIG.
It is good to paste and transfer the anisotropic conductive film (ACF) shown in 1 above, but it is also possible to print a paste or use a heating head heated from 80 ° C to 100 ° C,
It can also be applied by a dispenser robot. This anisotropic conductive adhesive 18 is transferred to a thickness of 20 μm to 100 μm to the same size as the semiconductor chip 13 to be mounted or to a range about 2 mm larger than its outer shape.

【0030】次の工程2で、異方性導電接着剤18を配
置した基板12を、加熱治具20を用いて裏面から仮加
熱する。この仮加熱は、異方性導電接着剤18の硬化温
度より低い100℃から120℃の温度で、5秒から1
0秒間加熱する。加熱治具20は、ステンレス材の内部
にヒータ20aを内蔵しており、基板12の半導体チッ
プ13が実装される範囲全体を加熱できるようにセット
する。
In the next step 2, the substrate 12 on which the anisotropic conductive adhesive 18 is disposed is temporarily heated from the back surface by using a heating jig 20. This temporary heating is performed at a temperature of 100 ° C. to 120 ° C. lower than the curing temperature of the anisotropic conductive adhesive 18 for 5 seconds to 1 second.
Heat for 0 seconds. The heating jig 20 has a built-in heater 20a inside a stainless steel material, and is set so that the entire area of the substrate 12 where the semiconductor chip 13 is mounted can be heated.

【0031】その後、工程3で、半導体チップ13に形
成された突起電極14を、基板12上に透明電極膜であ
る酸化インジュウムスズ(ITO)膜や酸化スズ膜によ
って形成された配線パターン15と位置合わせし、半導
体チップ13を第2の基板12に異方性導電接着剤18
を介して搭載する。
Thereafter, in step 3, the protruding electrodes 14 formed on the semiconductor chip 13 are aligned with the wiring patterns 15 formed on the substrate 12 by using an indium tin oxide (ITO) film or a tin oxide film as a transparent electrode film. Then, the semiconductor chip 13 is attached to the second substrate 12 by the anisotropic conductive adhesive 18.
Mounted via

【0032】そして、工程4で、ヒータ19aを内蔵す
る加熱加圧治具19を用いて、半導体チップ13をガラ
ス基板に加圧しながら加熱して熱圧着し、異方性導電接
着剤18を硬化させる。この熱圧着時の温度は150℃
から260℃、好ましくは180℃から200℃で、圧
力は3kgから20kgの範囲で行なう。その加圧力
は、エアシリンダ又はモータ等の駆動力によって加える
ことができる。
Then, in step 4, the semiconductor chip 13 is heated and thermocompression-bonded to the glass substrate using a heating and pressing jig 19 having a built-in heater 19a, and the anisotropic conductive adhesive 18 is cured. Let it. The temperature during thermocompression bonding is 150 ° C
To 260 ° C., preferably 180 ° to 200 ° C., at a pressure in the range of 3 kg to 20 kg. The pressing force can be applied by a driving force of an air cylinder or a motor.

【0033】この工程によって、半導体チップ13は基
板12上に接着され、その半導体チップ13の各突起電
極14と基板12上の配線パターン15との間にそれぞ
れ複数個ずつの導電粒子18aが挟持され、それによっ
て、各突起電極14と配線パターン15とが導通され
る。
In this step, the semiconductor chip 13 is bonded onto the substrate 12, and a plurality of conductive particles 18 a are sandwiched between each of the protruding electrodes 14 of the semiconductor chip 13 and the wiring pattern 15 on the substrate 12. Accordingly, each protruding electrode 14 and the wiring pattern 15 are conducted.

【0034】異方性導電接着剤18を本硬化させる前
に、異方性導電接着剤18を配置した基板を仮加熱する
ことによって、異方性導電接着剤18中に含まれる揮発
成分が蒸発し、巻き込んだ気泡も脱泡され、図2に示す
ように異方性導電接着剤18の硬化時の気泡21の発生
が極めて少なくなる。
Before the anisotropic conductive adhesive 18 is completely cured, the substrate on which the anisotropic conductive adhesive 18 is disposed is temporarily heated, so that volatile components contained in the anisotropic conductive adhesive 18 are evaporated. Then, the entrained bubbles are also defoamed, and as shown in FIG. 2, the generation of bubbles 21 when the anisotropic conductive adhesive 18 is cured is extremely reduced.

【0035】気泡の発生が少なくなることにより、従来
の実装方法による気泡の発生が多かった場合と比べて、
基板12と半導体チップ13の間に異方性導電接着剤1
8の接着剤樹脂が密に充填されるので、接着力が強くな
り、突起電極14と配線パターン15間に挟んでいる導
電粒子18aを保持する力も強くなるので、接続抵抗値
が低くなり且つ安定する。
Since the generation of bubbles is reduced, compared with the case where the generation of bubbles by the conventional mounting method is large,
Anisotropic conductive adhesive 1 between substrate 12 and semiconductor chip 13
8 is densely filled, the adhesive strength is increased, and the force for holding the conductive particles 18a sandwiched between the protruding electrode 14 and the wiring pattern 15 is also increased, so that the connection resistance value is reduced and stable. I do.

【0036】ここで、実際に半導体チップを回路基板に
従来の方法で実装した場合と、この発明による方法で実
装した場合との比較実験を行なったので、その比較実験
およびその結果について説明する。
Here, a comparison experiment between a case where a semiconductor chip is actually mounted on a circuit board by a conventional method and a case where the semiconductor chip is mounted by a method according to the present invention is described. The comparison experiment and the result will be described.

【0037】実験方法は、接続抵抗値が測定できるよう
にITO配線パターンを形成したガラス基板上に異方性
導電接着剤を貼り付けた基板を作製し、従来の実装方法
では、そのまま半導体チップをガラス基板上に位置合わ
せして、約180℃の温度で20秒程度加熱して接着剤
を硬化させた。
In the experimental method, a substrate was prepared by pasting an anisotropic conductive adhesive on a glass substrate on which an ITO wiring pattern was formed so that the connection resistance value could be measured. The adhesive was positioned on a glass substrate and heated at a temperature of about 180 ° C. for about 20 seconds to cure the adhesive.

【0038】この発明の実装方法では、異方性導電接着
剤を貼り付けたガラス基板を、温度100℃程度に加熱
したホットプレート上に約10秒間放置して、異方性導
電接着剤中の揮発成分を蒸発させた後、半導体チップを
そのガラス基板上に位置合わせして、約180℃の温度
で20秒程度加熱して接着剤を硬化させた。
In the mounting method of the present invention, the glass substrate to which the anisotropic conductive adhesive has been adhered is left on a hot plate heated to about 100 ° C. for about 10 seconds, and After evaporating the volatile components, the semiconductor chip was positioned on the glass substrate and heated at a temperature of about 180 ° C. for about 20 seconds to cure the adhesive.

【0039】このようにして作製した従来の実装方法に
よるサンプルと、この発明の実装方法によるサンプルと
を、温度85℃,湿度85%の高温高湿雰囲気に設定し
た炉中に500時間放置して耐久試験を行なった。図3
は、その耐久試験における従来の実装方法のサンプルと
この発明の実装方法のサンプルとによる、半導体チップ
の突起電極とガラス基板上の配線パターンとの接続抵抗
値の変化を示す線図(グラフ)である。
The sample manufactured by the conventional mounting method and the sample manufactured by the mounting method of the present invention are left for 500 hours in a furnace set in a high-temperature and high-humidity atmosphere at a temperature of 85 ° C. and a humidity of 85%. A durability test was performed. FIG.
Is a diagram (graph) showing a change in connection resistance value between the protruding electrode of the semiconductor chip and the wiring pattern on the glass substrate according to the sample of the conventional mounting method and the sample of the mounting method of the present invention in the durability test. is there.

【0040】図3から明らかなように、500時間放置
後の接続抵抗値を比べると、従来の実装法のサンプルに
おける接続抵抗は約32Ωになっており、初期の接続抵
抗(約5Ω)よりかなり増加しているが、この発明の実
装方法のサンプルにおける接続抵抗値は約10Ωで、初
期の接続抵抗(約2Ω)から僅かしか増加していない。
As can be seen from FIG. 3, when the connection resistance after leaving for 500 hours is compared, the connection resistance in the sample of the conventional mounting method is about 32Ω, which is considerably larger than the initial connection resistance (about 5Ω). Although increasing, the connection resistance value in the sample of the mounting method of the present invention is about 10Ω, which is only slightly increased from the initial connection resistance (about 2Ω).

【0041】このように、この発明の方法によって半導
体チップを実装した方が、従来の方法によって半導体チ
ップを実装した場合よりも、長期に亘って接続抵抗を低
く維持することができる。
As described above, when the semiconductor chip is mounted by the method of the present invention, the connection resistance can be kept lower for a long time than when the semiconductor chip is mounted by the conventional method.

【0042】次に、この発明による半導体チップの実装
方法の第2の実施形態を、前述の実施形態と同様に図5
及び図6に示した液晶パネルに液晶駆動用の半導体チッ
プを実装する場合について説明する。図4はこの第2の
実施形態による半導体チップの実装工程を示す断面図で
あり、図7及び図1と同様に図5のA−A線に沿う断面
に相当する。この図4において図7及び図1と同じ部分
には同一の符号を付している。
Next, a second embodiment of the semiconductor chip mounting method according to the present invention will be described with reference to FIG.
A case where a semiconductor chip for driving liquid crystal is mounted on the liquid crystal panel shown in FIG. 6 will be described. FIG. 4 is a cross-sectional view showing a mounting step of the semiconductor chip according to the second embodiment, and corresponds to a cross-section along the line AA in FIG. 5, as in FIGS. In FIG. 4, the same parts as those in FIGS. 7 and 1 are denoted by the same reference numerals.

【0043】この第2の実施形態において、図4に示す
工程1および工程2は、図7に示した従来例の工程1お
よび工程2と同じである。すなわち、工程1では、液晶
パネルの回路基板である第2の基板(以下単に「基板」
という)12の余白部16上の半導体チップを搭載する
領域に、異方性導電接着剤18を転写等によって配置す
る。
In the second embodiment, steps 1 and 2 shown in FIG. 4 are the same as steps 1 and 2 of the conventional example shown in FIG. That is, in step 1, a second substrate (hereinafter simply referred to as a “substrate”) that is a circuit substrate of a liquid crystal panel is used.
An anisotropic conductive adhesive 18 is arranged by transfer or the like in a region where the semiconductor chip is to be mounted on the margin 16 of the 12).

【0044】工程2では、半導体チップ13の突起電極
14を対向する基板12の配線パターン15と位置合わ
せして、半導体チップ13を異方性導電接着剤18を介
して基板12上に配置する。
In step 2, the semiconductor chip 13 is arranged on the substrate 12 via the anisotropic conductive adhesive 18 by aligning the projecting electrodes 14 of the semiconductor chip 13 with the wiring patterns 15 of the substrate 12 facing the semiconductor chip 13.

【0045】工程3がこの実施形態特有の工程であり、
ヒータ19aを内蔵する加熱加圧治具19を用いて、半
導体チップ13を基板12に対して加圧しながら加熱し
て熱圧着し、異方性導電接着剤18を硬化させる際に、
同時に、ヒータ20aを内蔵する加熱治具20によって
基板12を下面(半導体チップ13を配置した面と反対
側の面)から加熱する。その加熱温度は、半導体チップ
13の加熱温度より低い温度であり、その具体例は後述
する。
Step 3 is a step unique to this embodiment.
When the semiconductor chip 13 is heated and thermocompression-bonded to the substrate 12 using a heating and pressing jig 19 having a built-in heater 19a, and the anisotropic conductive adhesive 18 is cured,
At the same time, the substrate 12 is heated from the lower surface (the surface opposite to the surface on which the semiconductor chips 13 are arranged) by the heating jig 20 incorporating the heater 20a. The heating temperature is lower than the heating temperature of the semiconductor chip 13, and a specific example thereof will be described later.

【0046】異方性導電接着剤18が硬化すれば、工程
4に示すように、半導体チップ13は第2の基板12上
に接着され、半導体チップ13の突起電極14と配線パ
ターン15との間に挟持された導電粒子18aによっ
て、突起電極14と配線パターン15との導通がなされ
る。
When the anisotropic conductive adhesive 18 is hardened, the semiconductor chip 13 is bonded on the second substrate 12 as shown in step 4, and the semiconductor chip 13 is placed between the protruding electrode 14 of the semiconductor chip 13 and the wiring pattern 15. By the conductive particles 18a sandwiched between the wirings, conduction between the protruding electrode 14 and the wiring pattern 15 is established.

【0047】工程3での熱圧着時に半導体チップ13に
加える温度は150℃から260℃、好ましくは180
℃〜240℃で、圧力は1kgから30kgの範囲で行
なう。圧着時間は5秒から10秒である。ところで、圧
着時間が5秒から10秒の間ではガラス基板の温度は、
100℃程度にしか上昇しない。
The temperature applied to the semiconductor chip 13 during the thermocompression bonding in the step 3 is 150 ° C. to 260 ° C., preferably 180 ° C.
C. to 240.degree. C. and a pressure in the range of 1 kg to 30 kg. The crimping time is 5 to 10 seconds. By the way, when the pressure bonding time is between 5 seconds and 10 seconds, the temperature of the glass substrate is
It only rises to about 100 ° C.

【0048】図9に示したように、ホウケイ酸系のガラ
ス基板である基板12と半導体チップ13とを同じ温度
で加熱していくと、熱膨張係数の大きいガラス基板の方
が半導体チップよりも伸び量が大きい。図9中に斜線で
示した部分がガラス基板と半導体チップとの熱膨張量の
ずれ量を示している。温度250℃では0.00502
5mmのずれを生じている。この伸び量の差をなくすた
めに、基板12の下面に加熱治具20を配置して基板1
2を加熱し、半導体チップ13との温度差を調節する。
As shown in FIG. 9, when a substrate 12 which is a borosilicate glass substrate and a semiconductor chip 13 are heated at the same temperature, a glass substrate having a larger coefficient of thermal expansion is larger than a semiconductor chip. Large elongation. The hatched portion in FIG. 9 indicates the amount of deviation in the amount of thermal expansion between the glass substrate and the semiconductor chip. 0.00502 at 250 ° C
There is a shift of 5 mm. In order to eliminate this difference in the amount of elongation, a heating jig 20 is
2 is heated to adjust the temperature difference from the semiconductor chip 13.

【0049】図10に示したガラス基板の温度と250
℃の半導体チップとの熱歪み量の関係を示す線図(グラ
フ)から、半導体チップ13を250℃に加熱した場合
には、ガラス基板である基板12をどれだけ加熱すれば
歪みがなくなるかが判かる。基板12を約130℃にす
ると熱歪み量がほぼゼロになる。以下この点を数値とと
もに説明する。
The temperature of the glass substrate shown in FIG.
From a diagram (graph) showing the relationship between the amount of thermal distortion with the semiconductor chip at a temperature of ° C., when the semiconductor chip 13 is heated to 250 ° C., it is determined how much the substrate 12 which is a glass substrate is heated to eliminate the distortion. I understand. When the temperature of the substrate 12 is set to about 130 ° C., the amount of thermal strain becomes almost zero. Hereinafter, this point will be described together with numerical values.

【0050】室温を20℃と設定した場合に、ガラス基
板と半導体チップに発生する伸び量を計算する。半導体
チップの一辺の長さを15mmとし、熱膨張による伸び
は左右対称に発生するものとして片側半分について計算
すると、250℃に加熱された半導体チップ13の伸び
量は、 (15mm÷2)×24.2×10~7×(250℃−2
0℃)=0.0041745mm である。
When the room temperature is set to 20 ° C., the amount of elongation generated in the glass substrate and the semiconductor chip is calculated. When the length of one side of the semiconductor chip is set to 15 mm and the elongation due to thermal expansion occurs symmetrically on one side, the amount of elongation of the semiconductor chip 13 heated to 250 ° C. is (15 mm ÷ 2) × 24 0.2 × 10 ~ 7 × (250 ℃ -2
(0 ° C.) = 0.0041745 mm 2.

【0051】このときの基板12の伸び量は、基板12
を130℃に加熱した場合、 (15mm÷2)×51×10~7×(130℃−20
℃)=0.0042075mm となる。したがって、ガラス基板と半導体チップのずれ
は、 0.0041745mm−0.0042075mm=0.
0000330mm となり、熱歪み量をほぼゼロにすることができる。
At this time, the extension amount of the substrate 12
Is heated to 130 ° C., (15 mm ÷ 2) × 51 × 10 to 7 × (130 ° C.-20
C) = 0.0042075 mm. Therefore, the deviation between the glass substrate and the semiconductor chip is 0.0041745 mm-0.00004275 mm = 0.
000330 mm 2, and the amount of thermal strain can be reduced to almost zero.

【0052】計算上では、基板12を129.1372
℃ 程度に加熱することによって、熱歪みを完全にをな
くすことができる。以上のようなことから、ホウケイ酸
系のガラス基板に液晶駆動用の半導体チップを実装する
場合には、ガラス基板を加熱治具で約130℃に加熱す
るとよいことが判かる。
In calculation, the substrate 12 is 129.1372.
By heating to about ° C, thermal distortion can be completely eliminated. From the above, it can be seen that when a semiconductor chip for driving liquid crystal is mounted on a borosilicate glass substrate, it is preferable to heat the glass substrate to about 130 ° C. with a heating jig.

【0053】他の熱膨張係数が異なる材料を使用した回
路基板に半導体チップを実装する場合や、異方性導電接
着剤の硬化温度が変わっても、それらの材料の熱膨張係
数から半導体チップと熱収縮量が同一となるような温度
を算出し、回路基板側の温度を調節して半導体チップを
実装することによって、熱歪みのない実装を行なうこと
ができる。
Even when a semiconductor chip is mounted on a circuit board using another material having a different coefficient of thermal expansion, or when the curing temperature of the anisotropic conductive adhesive changes, the semiconductor chip and the semiconductor chip are determined based on the coefficient of thermal expansion of those materials. By calculating a temperature at which the heat shrinkage becomes the same and adjusting the temperature on the circuit board side to mount the semiconductor chip, mounting without thermal distortion can be performed.

【0054】さらに、前述した第1の実施形態と上記第
2の実施形態とを組み合わせて、この発明による半導体
チップの実装方法の第3の実施形態とすることができ
る。すなわち、図1に示したこの発明の第1の実施形態
による半導体チップの実装工程において、その工程3に
代えて、図4に示した上記第2の実施形態の工程4を行
なうようにすることができる。
Further, the third embodiment of the semiconductor chip mounting method according to the present invention can be obtained by combining the first embodiment described above with the second embodiment. That is, in the step of mounting the semiconductor chip according to the first embodiment of the present invention shown in FIG. 1, step 4 of the above-described second embodiment shown in FIG. Can be.

【0055】具体的には、工程2において、異方性導電
接着剤18を配置した基板12を、加熱治具20によっ
て異方性導電接着剤18の硬化温度より低い温度で仮加
熱し、さらに、その異方性導電接着剤を硬化させる工程
3において、基板12をその下面側からも、加熱治具2
0によって半導体チップ13に対する加熱治具19によ
る加熱温度より低い温度で加熱することの両方を行な
う。
Specifically, in step 2, the substrate 12 on which the anisotropic conductive adhesive 18 is disposed is temporarily heated by a heating jig 20 at a temperature lower than the curing temperature of the anisotropic conductive adhesive 18. In the step 3 of curing the anisotropic conductive adhesive, the substrate 12 is also moved from the lower surface thereof to the heating jig 2.
In the case of 0, the semiconductor chip 13 is both heated at a temperature lower than the heating temperature of the heating jig 19.

【0056】それによって、異方性導電接着剤18と半
導体チップ13および基板12との間での気泡の発生を
殆どなくすと共に、基板12と半導体チップ13間での
熱歪みの発生も防ぎ、一層信頼性の高い実装を実現する
ことができる。
As a result, the generation of bubbles between the anisotropic conductive adhesive 18 and the semiconductor chip 13 and the substrate 12 is almost eliminated, and the generation of thermal distortion between the substrate 12 and the semiconductor chip 13 is also prevented. A highly reliable mounting can be realized.

【0057】[0057]

【発明の効果】以上説明してきたように、この発明によ
る半導体チップの実装方法では、半導体チップを回路基
板上に配置する前に、異方性導電接着剤を加熱して、接
着剤中に含まれる揮発成分を飛ばした後、半導体チップ
を搭載して熱圧着することによって、異方性導電接着剤
の硬化時の気泡の発生を押さえることができるので、接
着力を高め、信頼性の高い半導体チップの回路基板への
実装を行なうことができる。
As described above, in the method of mounting a semiconductor chip according to the present invention, the anisotropic conductive adhesive is heated and included in the adhesive before placing the semiconductor chip on the circuit board. After the volatile components are blown off, the semiconductor chip is mounted and thermocompression-bonded, which can suppress the generation of bubbles when the anisotropic conductive adhesive is cured. The chip can be mounted on a circuit board.

【0058】また、半導体チップを熱圧着する際に、回
路基板と半導体チップの熱膨張係数の違いによる伸びの
差をなくすために、回路基板を下面側から加熱しながら
半導体チップを熱圧着することにより、異方性導電接着
剤の加熱硬化が終了して回路基板と半導体チップの温度
が室温に戻ったときに熱歪みのない良好な接続状態を得
ることができる。これらの両方を実施することによっ
て、一層信頼性の高い半導体チップのの回路基板への実
装を実現することができる。
When the semiconductor chip is thermocompression-bonded, the semiconductor chip is thermocompression-bonded while the circuit board is heated from the lower side in order to eliminate a difference in elongation due to a difference in thermal expansion coefficient between the circuit board and the semiconductor chip. Thereby, when the heat curing of the anisotropic conductive adhesive is completed and the temperature of the circuit board and the semiconductor chip returns to room temperature, a good connection state without thermal distortion can be obtained. By carrying out both of these, it is possible to realize mounting of a more reliable semiconductor chip on a circuit board.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明による半導体チップの実装方法の第1
の実施形態の各工程をを示す図6と同様な断面図であ
る。
FIG. 1 shows a first embodiment of a semiconductor chip mounting method according to the present invention.
FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating each step of the embodiment.

【図2】この発明の第1の実施形態を実施した場合に異
方性導電接着剤に発生する気泡の状態を示す平面図であ
る。
FIG. 2 is a plan view showing a state of bubbles generated in the anisotropic conductive adhesive when the first embodiment of the present invention is carried out.

【図3】従来の実装方法でのサンプルとこの発明の第1
の実施形態による実装方法でのサンプルによる信頼性試
験における接続抵抗値の経時変化を示す線図である。
FIG. 3 shows a sample of a conventional mounting method and a first example of the present invention.
FIG. 10 is a diagram showing a change over time of a connection resistance value in a reliability test using a sample in the mounting method according to the embodiment.

【図4】この発明による半導体チップの実装方法の第2
の実施形態の各工程をを示す図6と同様な断面図であ
る。
FIG. 4 shows a second embodiment of the semiconductor chip mounting method according to the present invention.
FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating each step of the embodiment.

【図5】この発明による半導体チップの実装方法を適用
する液晶表示装置の平面図である。
FIG. 5 is a plan view of a liquid crystal display device to which the semiconductor chip mounting method according to the present invention is applied.

【図6】図5のA−A線に沿う部分的な拡大断面図であ
る。
FIG. 6 is a partially enlarged sectional view taken along line AA of FIG. 5;

【図7】従来の半導体チップの実装方法の各工程を示す
図6と同様な断面図である。
FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating each step of a conventional semiconductor chip mounting method.

【図8】従来の半導体チップの実装方法を実施した場合
に異方性導電接着剤に発生する気泡の状態を示す平面図
である。
FIG. 8 is a plan view showing a state of bubbles generated in an anisotropic conductive adhesive when a conventional semiconductor chip mounting method is performed.

【図9】ホウケイ酸系のガラス基板と半導体チップの温
度に対する熱膨張量を示す線図である。
FIG. 9 is a diagram showing a thermal expansion amount with respect to a temperature of a borosilicate glass substrate and a semiconductor chip.

【図10】ホウケイ酸系のガラス基板の各温度における
250℃の半導体チップとの熱歪み量を示す線図であ
る。
FIG. 10 is a diagram showing the amount of thermal distortion between a borosilicate glass substrate and a semiconductor chip at 250 ° C. at each temperature.

【図11】異方性導電接着剤の一例である異方性導電フ
ィルムの断面図である。
FIG. 11 is a cross-sectional view of an anisotropic conductive film which is an example of an anisotropic conductive adhesive.

【図12】図11に示した異方性導電フィルム中に混入
されている導電粒子を拡大して一部を切り欠いて示す斜
視図である。
FIG. 12 is a perspective view showing an enlarged conductive particle mixed in the anisotropic conductive film shown in FIG.

【符号の説明】[Explanation of symbols]

11:第1の基板 12:第2の基板(基板) 13:半導体チップ 14:突起電極 15:配線パターン 16:余白部 18:異方性導電接着剤 18a:導電粒子 19:加熱加圧治具 20:加熱治具 21:気泡 180:異方性導電フィルム 11: First substrate 12: Second substrate (substrate) 13: Semiconductor chip 14: Projecting electrode 15: Wiring pattern 16: Margin 18: Anisotropic conductive adhesive 18a: Conductive particles 19: Heating and pressing jig 20: heating jig 21: air bubble 180: anisotropic conductive film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 突起電極を設けた半導体チップを配線パ
ターンを形成した回路基板に実装する半導体チップの実
装方法であって、 前記回路基板上に異方性導電接着剤を配置する工程と、 その異方性導電接着を配置した回路基板を該異方性導電
接着剤の硬化温度より低い温度で仮加熱する工程と、 前記半導体チップの突起電極を前記回路基板上の配線パ
ターンと位置合わせして、前記半導体チップを前記回路
基板に配置する工程と、 該半導体チップを該回路基板に加圧しながら加熱して前
記異方性導電接着剤を硬化させる工程とを有することを
特徴とする半導体チップの実装方法。
1. A method for mounting a semiconductor chip provided with protruding electrodes on a circuit board on which a wiring pattern is formed, the method comprising: disposing an anisotropic conductive adhesive on the circuit board; Temporarily heating the circuit board on which the anisotropic conductive adhesive is arranged at a temperature lower than the curing temperature of the anisotropic conductive adhesive; and aligning the protruding electrodes of the semiconductor chip with the wiring pattern on the circuit board. Placing the semiconductor chip on the circuit board; and heating the semiconductor chip while applying pressure to the circuit board to cure the anisotropic conductive adhesive. Implementation method.
【請求項2】 突起電極を設けた半導体チップを配線パ
ターンを形成した回路基板に実装する半導体チップの実
装方法であって、 前記回路基板上に異方性導電接着剤を配置する工程と、 前記半導体チップの突起電極を前記回路基板上の配線パ
ターンと位置合わせして、前記半導体チップを前記回路
基板に配置する工程と、 該半導体チップを該回路基板に加圧しながら加熱すると
共に、その回路基板を前記半導体チップを配置した面と
反対側の面から、前記半導体チップに対する加熱温度よ
り低い温度で加熱して前記異方性導電接着剤を硬化させ
る工程とを有することを特徴とする半導体チップの実装
方法。
2. A method of mounting a semiconductor chip provided with a protruding electrode on a circuit board having a wiring pattern formed thereon, the method comprising: disposing an anisotropic conductive adhesive on the circuit board; Aligning the projecting electrodes of the semiconductor chip with the wiring pattern on the circuit board, and arranging the semiconductor chip on the circuit board; heating the semiconductor chip while pressing the circuit board; Heating the anisotropic conductive adhesive from a surface opposite to the surface on which the semiconductor chip is arranged, at a temperature lower than the heating temperature for the semiconductor chip, to cure the anisotropic conductive adhesive. Implementation method.
【請求項3】 請求項1記載の半導体チップの実装方法
において、 前記異方性導電接着剤を硬化させる工程で、前記半導体
チップを前記回路基板に加圧しながら加熱すると共に、
その回路基板を前記半導体チップを配置した面と反対側
の面から、前記半導体チップに対する加熱温度より低い
温度で加熱することを特徴とする半導体チップの実装方
法。
3. The method of mounting a semiconductor chip according to claim 1, wherein in the step of curing the anisotropic conductive adhesive, the semiconductor chip is heated while being pressed against the circuit board,
A method of mounting a semiconductor chip, comprising heating the circuit board from a surface opposite to a surface on which the semiconductor chip is arranged at a temperature lower than a heating temperature for the semiconductor chip.
JP12200598A 1997-05-09 1998-05-01 Mounting method for semiconductor chip Pending JPH1187429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12200598A JPH1187429A (en) 1997-05-09 1998-05-01 Mounting method for semiconductor chip

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP11921697 1997-05-09
JP19086897 1997-07-16
JP9-190868 1997-07-16
JP9-119216 1997-07-16
JP12200598A JPH1187429A (en) 1997-05-09 1998-05-01 Mounting method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH1187429A true JPH1187429A (en) 1999-03-30

Family

ID=27313762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12200598A Pending JPH1187429A (en) 1997-05-09 1998-05-01 Mounting method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH1187429A (en)

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JP2001133801A (en) * 1999-11-04 2001-05-18 Seiko Epson Corp Method of mounting parts and method of producing electro-optic device
JP2002280716A (en) * 2001-03-19 2002-09-27 Pioneer Electronic Corp Electronic part mounting method and bonded body
JP2004356529A (en) * 2003-05-30 2004-12-16 Renesas Technology Corp Semiconductor device and method for manufacturing the semiconductor device
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JP2009177122A (en) * 2007-12-25 2009-08-06 Hitachi Chem Co Ltd Method for manufacturing thin bonded assembly, and thin bonded assembly
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100551515B1 (en) * 1999-04-26 2006-02-13 소니 케미카루 가부시키가이샤 Packaging method
JP2001133801A (en) * 1999-11-04 2001-05-18 Seiko Epson Corp Method of mounting parts and method of producing electro-optic device
JP2002280716A (en) * 2001-03-19 2002-09-27 Pioneer Electronic Corp Electronic part mounting method and bonded body
KR100978697B1 (en) * 2002-04-30 2010-08-30 토레 엔지니어링 가부시키가이샤 Bonding method and bonding device
JP2004356529A (en) * 2003-05-30 2004-12-16 Renesas Technology Corp Semiconductor device and method for manufacturing the semiconductor device
JP2008166488A (en) * 2006-12-28 2008-07-17 Matsushita Electric Ind Co Ltd Connection method for electronic component
US9015932B2 (en) 2006-12-28 2015-04-28 Panasonic Corporation Connecting method of electronic component
JP2008205045A (en) * 2007-02-16 2008-09-04 Sanyo Electric Co Ltd Manufacturing method of solar cell module
JP2009177122A (en) * 2007-12-25 2009-08-06 Hitachi Chem Co Ltd Method for manufacturing thin bonded assembly, and thin bonded assembly
JP2011199184A (en) * 2010-03-23 2011-10-06 Fujifilm Corp Substrate mounting device and substrate mounting method
JP2014063965A (en) * 2012-09-24 2014-04-10 Fujitsu Frontech Ltd Ic chip joint method
JP2016058581A (en) * 2014-09-10 2016-04-21 日立化成株式会社 Semiconductor device manufacturing method

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