JPH06224256A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06224256A JPH06224256A JP2600693A JP2600693A JPH06224256A JP H06224256 A JPH06224256 A JP H06224256A JP 2600693 A JP2600693 A JP 2600693A JP 2600693 A JP2600693 A JP 2600693A JP H06224256 A JPH06224256 A JP H06224256A
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- semiconductor device
- electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置と基板との接
続を行う構造に関するもので、液晶表示装置への駆動半
導体装置の実装や、エレクトロルミネセンス（ＥＬ）表
示装置への駆動半導体装置の実装や、発光ダイオード
（ＬＥＤ）シャッタ−への駆動半導体装置の実装に適用
される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for connecting a semiconductor device and a substrate, and mounting a driving semiconductor device on a liquid crystal display device or a driving semiconductor device on an electroluminescence (EL) display device. It is applied to mounting and mounting of a driving semiconductor device on a light emitting diode (LED) shutter.
【０００２】[0002]
【従来の技術】液晶表示装置への半導体装置の実装手段
としては、プリント印刷基板の上に半導体装置を実装
し、ガラスからなる液晶基板との間をフレキシブル印刷
基板（以下ＦＰＣと称す）を用いて接続する方法や、ヒ
−トシ−ルを用いて接続する方法（以下ＣＯＢと称す）
や、ＦＰＣ上に半導体装置を実装し、ＦＰＣと液晶基板
とを接続する方法（以下ＣＯＦと称す）や、あるいは直
接液晶基板に半導体装置を実装する、いわゆるチップオ
ングラス（以下ＣＯＧと称す）法が挙げられる。2. Description of the Related Art As a means for mounting a semiconductor device on a liquid crystal display device, a semiconductor device is mounted on a printed circuit board, and a flexible printed circuit board (hereinafter referred to as FPC) is used between the semiconductor device and a liquid crystal substrate made of glass. Connection method or a connection method using a heat seal (hereinafter referred to as COB)
Or a method of mounting a semiconductor device on an FPC and connecting the FPC and a liquid crystal substrate (hereinafter referred to as COF), or a so-called chip-on-glass (hereinafter referred to as COG) method of directly mounting the semiconductor device on the liquid crystal substrate. Is mentioned.
【０００３】ＣＯＢ法においては、半導体装置の実装工
程の他に、ＦＰＣ−液晶基板間接続とＦＰＣ−プリント
印刷基板間接続との２工程が必要である。このため、Ｆ
ＰＣ−液晶基板間接続のみで実装を行うことが可能なＣ
ＯＦ方式が、主流になりつつある。In the COB method, in addition to the step of mounting the semiconductor device, two steps of connection between the FPC-liquid crystal substrate and connection between the FPC-printed printed board are required. Therefore, F
C can be mounted only by connecting the PC and liquid crystal board
The OF method is becoming mainstream.
【０００４】しかしながら、ＣＯＦ方式を用いた接続に
おいても、ＦＰＣ−液晶基板間の接続ピッチは１００μ
ｍ程度までで、それ以下の接続ピッチが必要な場合は、
半導体装置全面実装が可能なＣＯＧ法が用いられる。However, even in the connection using the COF method, the connection pitch between the FPC and the liquid crystal substrate is 100 μm.
If you need a connection pitch of up to m or less,
The COG method is used, which allows the entire surface of a semiconductor device to be mounted.
【０００５】以下、図４と図５を用いて、半導体装置を
直接基板上に実装する前述のＣＯＧ法を説明する。図４
は半導体装置に設ける突起電極を示す断面図であり、図
５はＣＯＧ法を用いて接続する半導体装置と基板との実
装構造を示す断面図である。The above-mentioned COG method for directly mounting a semiconductor device on a substrate will be described below with reference to FIGS. 4 and 5. Figure 4
FIG. 5 is a cross-sectional view showing a bump electrode provided in a semiconductor device, and FIG. 5 is a cross-sectional view showing a mounting structure of a semiconductor device and a substrate which are connected using the COG method.
【０００６】図４に示すように、半導体装置１１の素子
形成面に設けたアルミニウムからなる接続パッド１２を
開口露出するように保護膜１３を形成する。さらに接続
パッド１２の上に、この接続パッド１２との接着、拡散
防止のため共通電極膜１４を形成する。As shown in FIG. 4, a protective film 13 is formed so that the connection pad 12 made of aluminum provided on the element formation surface of the semiconductor device 11 is exposed. Further, a common electrode film 14 is formed on the connection pad 12 for adhesion to the connection pad 12 and prevention of diffusion.
【０００７】さらに突起電極１５を、メッキ法や真空蒸
着法で銅や金などの金属を用いて形成する。この突起電
極１５は、実装密度を向上させるため半導体素子形成領
域上にも形成する。Further, the protruding electrode 15 is formed by using a metal such as copper or gold by a plating method or a vacuum evaporation method. The bump electrode 15 is also formed on the semiconductor element formation region in order to improve the mounting density.
【０００８】つぎに突起電極１５を形成した半導体装置
１１と、基板１６に配置した接続電極１７との接続方法
を、図５を用いて説明する。Next, a method of connecting the semiconductor device 11 having the protruding electrodes 15 and the connecting electrodes 17 arranged on the substrate 16 will be described with reference to FIG.
【０００９】図５に示すように、半導体装置１１の突起
電極１５の先端部に、エポキシ系の接着剤に導電粒を混
入した導電性接着剤１８をディップ法や印刷法で塗布す
る。As shown in FIG. 5, a conductive adhesive 18 prepared by mixing conductive particles in an epoxy adhesive is applied to the tip of the protruding electrode 15 of the semiconductor device 11 by a dipping method or a printing method.
【００１０】その後、双眼顕微鏡を用いて、半導体装置
１１と基板１６との位置合わせを行い、ガラスからなる
基板１６に配置した接続電極１７と突起電極１５とを接
続する。After that, the semiconductor device 11 and the substrate 16 are aligned using a binocular microscope, and the connection electrodes 17 and the protruding electrodes 15 arranged on the substrate 16 made of glass are connected.
【００１１】接続電極１７は酸化インジウムスズ（以下
ＩＴＯと称す）などの透明導電膜で構成する。The connection electrode 17 is composed of a transparent conductive film such as indium tin oxide (hereinafter referred to as ITO).
【００１２】さらに熱処理を行い導電性接着剤１８を硬
化させ、導電性接着剤１８の溶剤成分を蒸発させる。こ
のことにより、導電粒１９と突起電極１５、導電粒１９
と接続電極１７、および導電粒１９どうしで良好な電気
的接続が得られる。Further, heat treatment is performed to cure the conductive adhesive 18, and the solvent component of the conductive adhesive 18 is evaporated. As a result, the conductive particles 19, the protruding electrodes 15, and the conductive particles 19 are formed.
Good electrical connection can be obtained between the connection electrode 17, and the conductive particles 19.
【００１３】また、導電性接着剤１８の体積収縮によ
る、半導体装置１１と基板１６の間の引っ張り応力によ
って接続を安定化させる接着力が発生し、電気的接続性
も向上する。Further, the volume contraction of the conductive adhesive 18 causes an adhesive force to stabilize the connection due to the tensile stress between the semiconductor device 11 and the substrate 16, and the electrical connectivity is also improved.
【００１４】その後、半導体装置１１と基板１６のすき
間にエポキシ系などの有機系材料からなる封止樹脂２０
を流し込み、熱処理を行い封止樹脂２０を硬化させる。After that, a sealing resin 20 made of an organic material such as epoxy is provided in the gap between the semiconductor device 11 and the substrate 16.
Is poured and heat treatment is performed to cure the sealing resin 20.
【００１５】[0015]
【発明が解決しようとする課題】発明が解決しようとす
る課題を、図３を用いて説明する。図３は、基板１６上
に半導体装置１１とＦＰＣ１とを、ＣＯＧ法を用いて接
続した状態を横から見た断面図である。Problems to be solved by the invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of a state in which the semiconductor device 11 and the FPC 1 are connected to each other on the substrate 16 using the COG method, as viewed from the side.
【００１６】半導体装置１１には、通常１００〜４００
個の接続パッドが設けられるが、そのうち、１０〜２０
個が入力信号と入力電源用で、残りが出力信号用であ
る。The semiconductor device 11 is usually 100-400.
10 connection pads are provided, of which 10 to 20 are provided.
One is for the input signal and the input power supply, and the other is for the output signal.
【００１７】出力信号用の出力接続パッド上に設けられ
た出力突起電極１０は、基板１６に設けられた出力接続
電極７と導電性接着剤１８とを介して接続されている
が、同時に、入力信号や入力電源用の入力接続パッド上
に設けた入力突起電極３も、基板１６上の入力接続電極
２１と接続される。The output projection electrode 10 provided on the output connection pad for the output signal is connected to the output connection electrode 7 provided on the substrate 16 via the conductive adhesive 18, but at the same time, the input is made. The input projecting electrodes 3 provided on the input connection pads for signals and input power are also connected to the input connection electrodes 21 on the substrate 16.
【００１８】ＦＰＣ１を、熱可塑性樹脂シ−トや熱硬化
性樹脂シ−トに導電粒を混入した異方導電性シ−ト６を
用いて、入力接続電極２１の外周部にあたるＦＰＣ接続
部と接続する。The FPC 1 is connected to the FPC connecting portion corresponding to the outer peripheral portion of the input connecting electrode 21 by using an anisotropic conductive sheet 6 in which conductive particles are mixed in a thermoplastic resin sheet or a thermosetting resin sheet. Connecting.
【００１９】ＦＰＣ１上に配線された金属配線２の抵抗
値は１オ−ム以下と小さいが、入力接続電極２１は抵抗
の高いＩＴＯで形成されているので、入力抵抗が１００
オ−ム以上になってしまう。Although the resistance value of the metal wiring 2 wired on the FPC 1 is as small as 1 ohm or less, since the input connection electrode 21 is made of ITO having a high resistance, the input resistance is 100.
It will be more than home.
【００２０】したがって、半導体装置１１へ入力する電
源電圧が安定せず、表示画像により電源電圧が変動し、
表示パタ−ン以外の表示が影響を受ける、いわゆるクロ
スト−ク現象が発生しやすくなってしまう。Therefore, the power supply voltage input to the semiconductor device 11 is not stable, and the power supply voltage varies depending on the displayed image.
A so-called crosstalk phenomenon is likely to occur in which displays other than the display pattern are affected.
【００２１】この課題を解決するため、本発明の目的
は、高密度実装が可能なＣＯＧ法での入力接続抵抗を数
オ−ム以下に小さくし、クロスト−ク現象を抑えること
ができる半導体装置の接続構造を提供することにある。In order to solve this problem, an object of the present invention is to reduce the input connection resistance in the COG method capable of high-density mounting to several ohms or less, and to suppress the crosstalk phenomenon. To provide the connection structure of.
【００２２】[0022]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置は、下記記載の構成を採用す
る。In order to achieve the above object, the semiconductor device of the present invention adopts the structure described below.
【００２３】本発明の半導体装置は、金属配線を有する
フレキシブル印刷基板と、入力突起電極と出力突起電極
とを有する半導体装置と、出力接続電極を有する基板
と、出力突起電極と出力接続電極とを接続する導電性接
着剤と、フレキシブル印刷基板と半導体装置とを固定す
る接着剤と、入力突起電極と金属配線とを接続する金属
細線とを備えることを特徴とする。The semiconductor device of the present invention includes a flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, an output protruding electrode and an output connecting electrode. It is characterized by comprising a conductive adhesive for connection, an adhesive for fixing the flexible printed circuit board and the semiconductor device, and a thin metal wire for connecting the input protruding electrode and the metal wiring.
【００２４】本発明の半導体装置は、金属配線を有する
フレキシブル印刷基板と、入力接続パッドと出力接続パ
ッド上の出力突起電極とを有する半導体装置と、出力接
続電極を有する基板と、出力突起電極と出力接続電極と
を接続する導電性接着剤と、フレキシブル印刷基板と半
導体装置とを固定する接着剤と、入力突起電極と金属配
線とを接続する金属細線とを備えることを特徴とする。The semiconductor device of the present invention is a semiconductor device having a flexible printed board having metal wiring, an input connection pad and an output protrusion electrode on the output connection pad, a substrate having an output connection electrode, and an output protrusion electrode. It is characterized by comprising a conductive adhesive for connecting the output connection electrode, an adhesive for fixing the flexible printed board and the semiconductor device, and a fine metal wire for connecting the input protruding electrode and the metal wiring.
【００２５】本発明の半導体装置は、金属配線を有する
フレキシブル印刷基板と、入力突起電極と出力突起電極
とを有する半導体装置と、出力接続電極を有する基板
と、出力突起電極と出力接続電極とを接続する導電性接
着剤と、入力突起電極と金属配線とを接続する異方導電
性シ−トとを備えることを特徴とする。The semiconductor device of the present invention comprises a flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, an output protruding electrode and an output connecting electrode. A conductive adhesive for connection and an anisotropic conductive sheet for connecting the input protruding electrode and the metal wiring are provided.
【００２６】本発明の半導体装置は、金属配線を有する
フレキシブル印刷基板と、入力突起電極と出力突起電極
とを有する半導体装置と、出力接続電極を有する基板
と、出力突起電極と出力接続電極とを接続する導電性接
着剤を備え、入力突起電極と金属配線との接続は金属共
晶を用いて行うことを特徴とする。The semiconductor device of the present invention comprises a flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, an output protruding electrode and an output connecting electrode. A conductive adhesive for connection is provided, and the connection between the input protruding electrode and the metal wiring is performed by using a metal eutectic.
【００２７】[0027]
【作用】本発明は、半導体装置の出力接続パッド上の出
力突起電極を直接、基板上に配置した出力接続電極と接
続し、半導体装置の入力接続パッドまたは入力突起電極
をワイヤ−ボンディング法により形成する金属細線や、
異方導電性シ−トや、金属同士の金属共晶を用いてフレ
キシブル印刷基板上の金属配線と接続する構造を採用す
る。この結果、半導体装置への入力接続抵抗を小さく
し、入力する電源電圧を安定化することで、クロスト−
ク現象を抑えることができる。According to the present invention, the output projection electrode on the output connection pad of the semiconductor device is directly connected to the output connection electrode arranged on the substrate, and the input connection pad or the input projection electrode of the semiconductor device is formed by the wire bonding method. Thin metal wires,
An anisotropic conductive sheet or a metal eutectic of metals is used to connect to the metal wiring on the flexible printed board. As a result, by reducing the input connection resistance to the semiconductor device and stabilizing the input power supply voltage,
The black phenomenon can be suppressed.
【００２８】また、出力突起電極と基板上の出力接続電
極との接続に、導電性接着剤や、異方導電性シ−トや、
異方導電性接着剤や、光硬化性接着剤を用いることで、
高密度の出力接続電極と接続できる。A conductive adhesive, an anisotropic conductive sheet, or an electrically conductive adhesive is used for connecting the output protruding electrode and the output connecting electrode on the substrate.
By using an anisotropic conductive adhesive or a photo-curable adhesive,
Can be connected to high-density output connection electrodes.
【００２９】ＣＯＧ法では、半導体装置への入力抵抗と
しては、半導体装置の入力接続パッド−基板の入力接続
電極間の接続抵抗と、入力接続電極の入力突起電極接続
部−ＦＰＣ接続部までの配線抵抗と、入力接続電極のＦ
ＰＣ接続部−ＦＰＣの金属配線間の接続抵抗との、加算
された抵抗値となる。In the COG method, as the input resistance to the semiconductor device, the connection resistance between the input connection pad of the semiconductor device and the input connection electrode of the substrate, and the wiring from the input projection electrode connection part of the input connection electrode to the FPC connection part Resistance and F of input connection electrode
The resistance value is the sum of the connection resistance between the PC connection part and the metal wiring of the FPC.
【００３０】半導体装置の入力接続パッド−基板の入力
接続電極間の接続抵抗と、ＦＰＣ接続部−ＦＰＣの金属
配線との間の接続抵抗とは、通常数オ−ム以下にするこ
とができる。The connection resistance between the input connection pad of the semiconductor device and the input connection electrode of the substrate and the connection resistance between the FPC connection portion and the metal wiring of the FPC can be usually set to several ohms or less.
【００３１】しかしながら、入力接続電極の入力突起電
極接続部−ＦＰＣ接続部間の配線抵抗は、透明導電膜の
ように比抵抗が大きな材料を使用する場合、数十〜数百
オ−ムと大きな抵抗値となり、入力抵抗も大きくなって
しまう。However, the wiring resistance between the input protruding electrode connection portion and the FPC connection portion of the input connection electrode is as large as several tens to several hundreds ohms when a material having a large specific resistance such as a transparent conductive film is used. It becomes a resistance value and the input resistance also becomes large.
【００３２】そこで、半導体装置の入力接続パッドとＦ
ＰＣの金属配線間を、金属細線や異方導電性シ−トなど
の、比抵抗の小さい材料で接続することで、入力抵抗を
数オ−ム以下に下げることができる。Therefore, the input connection pad of the semiconductor device and the F
The input resistance can be reduced to several ohms or less by connecting the metal wirings of the PC with a material having a small specific resistance such as a metal thin wire or an anisotropic conductive sheet.
【００３３】さらに、クロスト−ク現象はいくつかの要
因によって発生するが、その一因として、液晶パネルの
走査電極電圧の変動が挙げられる。Further, the crosstalk phenomenon occurs due to several factors, one of which is the fluctuation of the scanning electrode voltage of the liquid crystal panel.
【００３４】単純マトリクス液晶パネルは、１ライン毎
に選択してゆく走査電極と、デ−タ信号を印加する信号
電極とから構成される。The simple matrix liquid crystal panel is composed of scanning electrodes which are selected line by line and signal electrodes which apply data signals.
【００３５】この走査電極は、選択期間に高電圧の選択
電圧が印加され、非選択期間には比較的低電圧の非選択
電圧が印加される。非選択期間は通常、選択期間の１０
０〜５００倍となり、わずかな変動でも液晶に印加され
る実効電圧が変化し、クロスト−ク現象が発生してしま
う。A high voltage selection voltage is applied to the scan electrodes during the selection period, and a relatively low voltage non-selection voltage is applied during the non-selection period. The non-selection period is usually 10 of the selection period.
It becomes 0 to 500 times, and even a slight change changes the effective voltage applied to the liquid crystal, causing a crosstalk phenomenon.
【００３６】したがって、走査電極用半導体装置の入力
接続抵抗を小さくし、非選択電圧を安定化することによ
り、クロスト−ク現象を低減することができる。Therefore, the crosstalk phenomenon can be reduced by reducing the input connection resistance of the scan electrode semiconductor device and stabilizing the non-selection voltage.
【００３７】[0037]
【実施例】以下、本発明の半導体装置の接続構造におけ
る実施例を、図面を用いて説明する。Embodiments of the semiconductor device connection structure according to the present invention will be described below with reference to the drawings.
【００３８】[0038]
【実施例１】まず、本発明による第１の実施例を図面に
基づいて説明する。図１は本発明で用いる半導体装置の
接続構造を示す断面図である。First Embodiment First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a connection structure of a semiconductor device used in the present invention.
【００３９】図１に示すように、半導体装置１１の出力
接続パッド上に形成される出力突起電極１０が、導電性
接着剤１８を用いて基板１６上に設ける出力接続電極７
と接続される。As shown in FIG. 1, the output projection electrode 10 formed on the output connection pad of the semiconductor device 11 is provided on the substrate 16 by using the conductive adhesive 18.
Connected with.
【００４０】またさらに入力接続パッド上に形成される
入力突起電極３は、ＦＰＣ１上の金属配線２と、ワイヤ
−ボンデイング法により形成する金属細線４を用いて接
続してある。Further, the input protruding electrode 3 formed on the input connection pad is connected to the metal wiring 2 on the FPC 1 by using the metal thin wire 4 formed by the wire-bonding method.
【００４１】したがって、半導体装置１１の入力突起電
極３と、ＦＰＣ１上の金属配線２との間の接続抵抗値
は、１オ−ム以下と小さくなる。Therefore, the connection resistance value between the input protruding electrode 3 of the semiconductor device 11 and the metal wiring 2 on the FPC 1 is as small as 1 ohm or less.
【００４２】つぎに以上説明した半導体装置と基板との
接続構造を得るための製造方法を、図面を用いて説明す
る。図６は本発明で用いる半導体装置を示す断面図であ
る。Next, a manufacturing method for obtaining the connection structure between the semiconductor device and the substrate described above will be described with reference to the drawings. FIG. 6 is a sectional view showing a semiconductor device used in the present invention.
【００４３】図６に示すように、半導体装置１１には、
アルミニウムからなる１２０個の出力接続パッド９と１
０個の入力接続パッド８とを設ける。As shown in FIG. 6, the semiconductor device 11 includes
120 output connection pads 9 and 1 made of aluminum
Zero input connection pads 8 are provided.
【００４４】半導体装置１１の素子形成表面に設けたア
ルミニウムからなる入力接続パッド８と出力接続パッド
９を含む全面に、保護膜１３を形成する。この保護膜１
３は一般的に燐を含有したシリコン酸化膜、あるいは窒
化シリコン膜などの無機絶縁膜や、ポリイミド樹脂など
の有機絶縁膜や、これらの積層構造を用いる。保護膜１
３の膜厚は１〜５μｍである。A protective film 13 is formed on the entire surface including the input connection pad 8 and the output connection pad 9 made of aluminum provided on the element formation surface of the semiconductor device 11. This protective film 1
3 generally uses a silicon oxide film containing phosphorus, an inorganic insulating film such as a silicon nitride film, an organic insulating film such as a polyimide resin, or a laminated structure of these. Protective film 1
The film thickness of 3 is 1 to 5 μm.
【００４５】その後、所定のマスクを用いて露光現像処
理を行なうフォトソリグラフィーとエッチングにより出
力接続パッド９と入力接続パッド８とが露出するよう
に、保護膜１３を開口する。Thereafter, the protective film 13 is opened so that the output connection pad 9 and the input connection pad 8 are exposed by photolithography and etching in which exposure and development processing is performed using a predetermined mask.
【００４６】さらに半導体装置１１の全面にアルミニウ
ム，クロム，銅，ニッケル，チタンなどの金属多層膜を
共通電極膜１４として、それぞれ０．１〜１０μｍの厚
さでスパッタリング法や真空蒸着法などの方法で形成す
る。Further, a metal multi-layer film of aluminum, chromium, copper, nickel, titanium or the like is used as the common electrode film 14 on the entire surface of the semiconductor device 11 and the thickness is 0.1 to 10 μm. To form.
【００４７】つぎに半導体装置１１の上に形成した共通
電極膜１４の全面に、感光性樹脂からなるメッキレジス
ト（図示せず）を厚さ１〜１０μｍで、回転塗布法によ
り形成する。その後、所定のマスクを用いて露光現像処
理を行なうフォトリソグラフィーにより、入力接続パッ
ド８と出力接続パッド９上に開口部を有するメッキレジ
ストを設ける。Then, a plating resist (not shown) made of a photosensitive resin is formed on the entire surface of the common electrode film 14 formed on the semiconductor device 11 to a thickness of 1 to 10 μm by a spin coating method. Then, a plating resist having openings is provided on the input connection pad 8 and the output connection pad 9 by photolithography in which exposure and development processing is performed using a predetermined mask.
【００４８】その後、銅や金（Ａｕ）などの金属からな
る出力突起電極１０と入力突起電極３とをメッキ法にて
形成し、さらにその後、不用になったメッキレジストを
除去する。After that, the output projecting electrode 10 and the input projecting electrode 3 made of a metal such as copper or gold (Au) are formed by a plating method, and thereafter, the unnecessary plating resist is removed.
【００４９】さらに入力突起電極３と出力突起電極１０
とをエッチングのマスクとして、不用な共通電極膜１４
を除去し、入力突起電極３と出力突起電極１０の下部に
のみ共通電極膜１４を残すように形成する。Further, the input protruding electrode 3 and the output protruding electrode 10
Unnecessary common electrode film 14 by using and as an etching mask.
Is removed, and the common electrode film 14 is formed so as to remain only under the input protruding electrode 3 and the output protruding electrode 10.
【００５０】出力突起電極１０の形状は直径５０〜２０
０μｍの円形が好ましく、これに対して入力突起電極３
の形状は直径２００〜５００μｍの円形、または長方形
が好ましい。しかしながら、出力突起電極１０の形状と
入力突起電極３の形状とは、同一形状で同一の大きさで
もかまわない。The output projection electrode 10 has a diameter of 50 to 20.
A circular shape of 0 μm is preferable, whereas the input protruding electrode 3
The shape is preferably a circle having a diameter of 200 to 500 μm or a rectangle. However, the shape of the output protruding electrode 10 and the shape of the input protruding electrode 3 may be the same shape and the same size.
【００５１】つぎに、半導体装置１１とフレキシブル印
刷基板（ＦＰＣ）１との接続方法を図１を用いて説明す
る。Next, a method of connecting the semiconductor device 11 and the flexible printed circuit (FPC) 1 will be described with reference to FIG.
【００５２】ＦＰＣ１に半導体装置１１を、エポキシ系
接着剤からなる接着剤５を用いて固定し、温度１００〜
１５０℃で熱硬化させる。ここで接着剤５としては、導
電性接着剤を用いる方が、半導体装置１１の静電気破壊
を防止することができ、好ましい。The semiconductor device 11 is fixed to the FPC 1 by using the adhesive 5 made of an epoxy adhesive, and the temperature is set to 100 to 100 ° C.
Heat cure at 150 ° C. Here, it is preferable to use a conductive adhesive as the adhesive 5 because it is possible to prevent electrostatic breakdown of the semiconductor device 11.
【００５３】つぎに、金属細線４を、ワイヤ−ボンディ
ング法を用いて、入力突起電極３とＦＰＣ１上の金属配
線２との間に接続する。Next, the thin metal wire 4 is connected between the input protruding electrode 3 and the metal wiring 2 on the FPC 1 by the wire bonding method.
【００５４】このワイヤーボンディング処理の際、金属
細線４が半導体装置１１のあまり下部まで延びないよう
に、ワイヤ−ボンディングの条件を設定し、金属細線４
の形状制御を行う。さらにこの状態を保護するために、
図１には図示していないが、半導体装置１１の周辺領域
や、金属配線２の金属細線４接続部周辺領域に、エポキ
シ系の封止樹脂を流して硬化させることが好ましい。In this wire bonding process, the wire-bonding conditions are set so that the metal thin wires 4 do not extend too much below the semiconductor device 11.
Shape control. To further protect this condition,
Although not shown in FIG. 1, it is preferable to flow an epoxy-based encapsulation resin to the peripheral region of the semiconductor device 11 and the peripheral region of the metal wire 4 connection portion of the metal wiring 2 to cure it.
【００５５】つぎに、半導体装置と基板との接続方法
を、図７を用いて説明する。図７は実施例１で用いる半
導体装置の出力突起電極と、基板の出力接続電極との接
続方法を示す断面図である。Next, a method of connecting the semiconductor device and the substrate will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a method of connecting the output protruding electrode of the semiconductor device used in Example 1 and the output connecting electrode of the substrate.
【００５６】ＦＰＣ１を接着剤５を用いて固着した半導
体装置１１の出力突起電極１０の先端部に、エポキシ系
接着剤に金（Ａｕ）やパラジウムの導電粒を混入した導
電性接着剤１８を、ディップ法や印刷法を用いて形成す
る。At the tip of the output bump electrode 10 of the semiconductor device 11 to which the FPC 1 is fixed with the adhesive 5, a conductive adhesive 18 obtained by mixing conductive particles of gold (Au) or palladium in an epoxy-based adhesive, It is formed using a dipping method or a printing method.
【００５７】その後、双眼顕微鏡を用いて、ガラスから
なる基板１６に配置した出力接続電極７と、半導体装置
１１に設けた出力突起電極１０とを位置合わせする。After that, the output connecting electrode 7 arranged on the glass substrate 16 and the output protruding electrode 10 provided on the semiconductor device 11 are aligned with each other using a binocular microscope.
【００５８】そして半導体装置１１を加圧して、基板１
６に仮接続した状態で導電性接着剤１８を、温度１００
〜２００℃で硬化させる。Then, the semiconductor device 11 is pressed to press the substrate 1
6 is temporarily connected to the conductive adhesive 18 at a temperature of 100.
Cure at ~ 200 ° C.
【００５９】最後に、半導体装置１１と基板１６との間
にエポキシ系や、ゴム系などの有機材料からなる封止樹
脂２０を注入し、温度１００〜１５０℃で硬化させる。Finally, a sealing resin 20 made of an organic material such as epoxy or rubber is injected between the semiconductor device 11 and the substrate 16 and cured at a temperature of 100 to 150 ° C.
【００６０】図１では、入力突起電極３上には、導電性
接着剤が形成されていないが、転写印刷法を用いて導電
性接着剤を形成する場合には、入力突起電極３上にも導
電性接着剤が形成されてしまうが、この入力突起電極３
上に導電性接着剤が形成されていても、なんら問題はな
い。In FIG. 1, the conductive adhesive is not formed on the input protruding electrode 3, but when the conductive adhesive is formed by the transfer printing method, it is also formed on the input protruding electrode 3. Although the conductive adhesive is formed, this input protruding electrode 3
There is no problem even if a conductive adhesive is formed on it.
【００６１】またさらに、半導体装置１１に固着するＦ
ＰＣ１が小型で軽量な場合は、仮接続した状態で加圧を
やめて熱硬化を行うことができる。しかしながら、ＦＰ
Ｃ１がある程度の大きさになった場合は、加圧固定治具
に挟み、ＦＰＣ１の重さで傾かないように加圧しなが
ら、熱硬化する方が好ましい。Furthermore, F which adheres to the semiconductor device 11
When the PC 1 is small and lightweight, the pressure can be stopped and the thermosetting can be performed in the temporarily connected state. However, FP
When C1 has reached a certain size, it is preferable to sandwich it between pressure fixing jigs and heat cure while applying pressure so as not to tilt with the weight of FPC1.
【００６２】なお、実施例１では、図６に示すように、
半導体装置１１の入力接続パッド８上に入力突起電極３
を形成した。しかしながら、入力接続パッド８上には突
起電極を形成せず、保護膜１３の開口部のみ設け、直接
アルミニウムからなる入力接続パッド８と、ＦＰＣ１上
の金属配線２とを金属細線４を用いて接続しても、なん
ら問題は無い。In the first embodiment, as shown in FIG.
The input protruding electrode 3 is formed on the input connection pad 8 of the semiconductor device 11.
Was formed. However, the protruding electrode is not formed on the input connection pad 8, only the opening portion of the protective film 13 is provided, and the input connection pad 8 made of aluminum is directly connected to the metal wiring 2 on the FPC 1 by using the metal thin wire 4. However, there is no problem.
【００６３】画面サイズが対角４インチの単純マトリク
ス方式液晶パネルに、信号電極用半導体装置はＣＯＧ法
で接続し、走査電極用半導体装置を本発明の構造で接続
したところ、従来の全ての半導体装置をＣＯＧ法で接続
した液晶パネルと比較して、クロスト−クが少ない良好
な表示画像が得られた。When a signal electrode semiconductor device was connected by a COG method and a scanning electrode semiconductor device was connected by the structure of the present invention to a simple matrix type liquid crystal panel having a diagonal size of 4 inches, all conventional semiconductors were obtained. A good display image with less crosstalk was obtained as compared with a liquid crystal panel in which the device was connected by the COG method.
【００６４】[0064]
【実施例２】つぎに、本発明による第２の実施例を図面
に基づいて説明する。図２は実施例２における半導体装
置の接続構造を示す断面図である。Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a sectional view showing a semiconductor device connection structure according to the second embodiment.
【００６５】図２に示すように、半導体装置１１の出力
接続パッド上に形成した出力突起電極１０は、導電性接
着剤１８を用いて、基板１６上の出力接続電極７と接続
される。As shown in FIG. 2, the output bump electrode 10 formed on the output connection pad of the semiconductor device 11 is connected to the output connection electrode 7 on the substrate 16 by using the conductive adhesive 18.
【００６６】また入力接続パッド上に形成した入力突起
電極３は、ＦＰＣ１上の金属配線２と、熱可塑性樹脂シ
−トや熱硬化性樹脂シ−トに導電粒を混入した異方導電
性シ−ト６を用いて接続する。The input projecting electrode 3 formed on the input connection pad is made up of the metal wiring 2 on the FPC 1 and the anisotropic conductive sheet in which conductive particles are mixed in the thermoplastic resin sheet or the thermosetting resin sheet. -Connect using point 6.
【００６７】したがって、半導体装置１１の入力接続パ
ッドとＦＰＣ１間の接続抵抗は、１オ−ム以下と小さく
なる。この結果、表示装置のクロスト−クを低減するこ
とができる。Therefore, the connection resistance between the input connection pad of the semiconductor device 11 and the FPC 1 is as small as 1 ohm or less. As a result, the crosstalk of the display device can be reduced.
【００６８】つぎに、以上説明した半導体装置と基板と
の接続構造を得るための製造方法を図６と図８を用いて
説明する。図６は突起電極を形成した半導体装置を示す
断面図であり、図８は実施例２で用いる半導体装置の出
力突起電極の接続方法を示す断面図である。Next, a manufacturing method for obtaining the above-described connection structure between the semiconductor device and the substrate will be described with reference to FIGS. 6 and 8. FIG. 6 is a cross-sectional view showing a semiconductor device having a bump electrode formed thereon, and FIG. 8 is a cross-sectional view showing a method of connecting output bump electrodes of the semiconductor device used in the second embodiment.
【００６９】図６に示すように、半導体装置１１には、
アルミニウムからなる１２０個の出力接続パッド９と、
１０個の入力接続パッド８とを形成する。As shown in FIG. 6, the semiconductor device 11 includes:
120 output connection pads 9 made of aluminum,
10 input connection pads 8 are formed.
【００７０】実施例１と同様に、半導体装置１１の入力
接続パッド８と出力接続パッド９上に、共通電極膜１４
を形成後、厚さ１〜１０μｍの入力突起電極３と出力突
起電極１０とをメッキ法で形成する。Similar to the first embodiment, the common electrode film 14 is formed on the input connection pad 8 and the output connection pad 9 of the semiconductor device 11.
After the formation, the input protruding electrode 3 and the output protruding electrode 10 having a thickness of 1 to 10 μm are formed by the plating method.
【００７１】半導体装置１１と、基板１６やＦＰＣ１と
の位置合わせ作業性の点から、出力突起電極１０の形状
としては、直径５０〜２００μｍの円形が好ましく、入
力突起電極３の形状は幅２００〜５００μｍ、長さ５０
０〜２０００μｍの長方形が好ましい。From the viewpoint of aligning workability between the semiconductor device 11 and the substrate 16 or the FPC 1, the output protrusion electrode 10 preferably has a circular shape with a diameter of 50 to 200 μm, and the input protrusion electrode 3 has a width of 200 to 200 μm. 500 μm, length 50
A rectangle of 0 to 2000 μm is preferable.
【００７２】つぎに図８に示すように、半導体装置１１
の出力突起電極１０の先端部に、導電粒１９を混入した
導電性接着剤１８をディップ法や印刷法で形成する。Next, as shown in FIG.
The conductive adhesive 18 mixed with the conductive particles 19 is formed on the tip of the output bump electrode 10 by the dipping method or the printing method.
【００７３】その後、双眼顕微鏡を用いて、基板１６の
出力接続電極７と、半導体装置１１に設けた出力突起電
極１０とを、図２に示すように、入力突起電極３が基板
１６の外部に出るようにして、位置合わせを行う。After that, the output connection electrode 7 of the substrate 16 and the output protruding electrode 10 provided on the semiconductor device 11 are connected to the outside of the substrate 16 by using a binocular microscope as shown in FIG. Position it as it appears.
【００７４】そして半導体装置１１を加圧して、基板１
６に仮接続した状態で、導電性接着剤１８を、温度１０
０〜２００℃で硬化させる。Then, the semiconductor device 11 is pressed to press the substrate 1
6 is temporarily connected to the conductive adhesive 18 at a temperature of 10
Cure at 0-200 ° C.
【００７５】この導電性接着剤１８を硬化させるとき、
加圧固定治具を用いて、半導体装置１１と基板１６とを
挟みながら導電性接着剤１８を熱硬化させると、基板１
６に対する半導体装置１１の位置ずれが少なく、かつ接
続抵抗を低下できるので好ましい。When the conductive adhesive 18 is cured,
When the conductive adhesive 18 is thermally cured while sandwiching the semiconductor device 11 and the substrate 16 using a pressure fixing jig, the substrate 1
6 is preferable because the positional deviation of the semiconductor device 11 with respect to 6 is small and the connection resistance can be reduced.
【００７６】つぎに、半導体装置１１の出力突起電極１
５の周辺領域に、エポキシ系や、ゴム系などの有機材料
からなる封止樹脂を注入し、温度１００〜１５０℃で硬
化させる。Next, the output protruding electrode 1 of the semiconductor device 11
A sealing resin made of an organic material such as epoxy or rubber is injected into the peripheral region of 5 and cured at a temperature of 100 to 150 ° C.
【００７７】この封止樹脂の形成工程では、入力突起電
極３の周辺には封止樹脂がまわり込まないように注意が
必要である。たとえば、あらかじめ耐熱性の良好で、剥
離しても粘着材が残りにくいポリイミド粘着テ−プなど
を、半導体装置１１の入力突起電極３に張り付けておく
と良い。In the step of forming the sealing resin, it is necessary to take care so that the sealing resin does not go around the input protruding electrode 3. For example, a polyimide adhesive tape, which has good heat resistance and does not leave an adhesive material even when peeled off, may be attached to the input protruding electrode 3 of the semiconductor device 11 in advance.
【００７８】つぎに、ＦＰＣ１と半導体装置１１の入力
突起電極３との異方導電性シート６を用いた接続方法に
ついて、図２を用いて説明する。Next, a method of connecting the FPC 1 and the input protruding electrode 3 of the semiconductor device 11 using the anisotropic conductive sheet 6 will be described with reference to FIG.
【００７９】異方導電性シ−ト６とは、厚さ２０〜５０
μｍの熱可塑性樹脂シ−トまたは熱硬化性樹脂シ−ト
に、ハンダ粒や金（Ａｕ）粒を数％混在させたシ−トで
ある。The anisotropic conductive sheet 6 has a thickness of 20 to 50.
This is a sheet in which a solder grain or a gold (Au) grain is mixed by several% in a thermoplastic resin sheet or a thermosetting resin sheet having a thickness of μm.
【００８０】この異方導電性シート６は、電極などで加
圧された部分のみ導電粒がつぶれて導電性が得られ、さ
らに、樹脂が硬化することで、接着力が得られる。In this anisotropically conductive sheet 6, the conductive particles are crushed only in the portion pressed by the electrode or the like to obtain the conductivity, and further, the resin is cured to obtain the adhesive force.
【００８１】異方導電性シート６は厚さ方向のみ導通
し、シ−ト平面方向には導電性が無いため、異方導電性
シ−トと呼ばれる。Since the anisotropically conductive sheet 6 conducts only in the thickness direction and has no conductivity in the sheet plane direction, it is called an anisotropically conductive sheet.
【００８２】本実施例では、異方導電性シート６とし
て、ソニ−ケミカル（株）の熱硬化型異方導電性シ−ト
である商品名 ＣＰ７１３１を使用する。In this example, as the anisotropic conductive sheet 6, a thermosetting anisotropic conductive sheet, trade name CP7131, manufactured by Sony Chemical Co., Ltd. is used.
【００８３】図２に示すように、まずはじめにＦＰＣ１
に異方導電性シ−ト６を、温度９０〜１００℃、圧力５
〜１０ｋｇ／ｃｍ2 、時間５〜１０秒の条件によって仮
接着する。As shown in FIG. 2, first, the FPC1
Anisotropic conductive sheet 6 at a temperature of 90 to 100 ° C. and a pressure of 5
Temporary bonding is performed under the conditions of 10 kg / cm 2 and time of 5 to 10 seconds.
【００８４】半導体装置１１が下側向きで、かつ平行に
配置できるような圧接治具に、半導体装置１１を接続し
た基板１６を設置する。The substrate 16 to which the semiconductor device 11 is connected is placed on a pressing jig which allows the semiconductor device 11 to face downward and be arranged in parallel.
【００８５】その後、ＦＰＣ１の配線電極２と、半導体
装置１１の入力突起電極３との位置合わせを行う。そし
て、ＦＰＣ１側から温度が１７０〜１８０゜Ｃ、圧力が
３０〜５０ｋｇ／ｃｍ2 、時間が１５〜３０秒の条件で
異方導電性シ−ト６を熱圧着して、ＦＰＣ１と半導体装
置１１を接着する。After that, the wiring electrodes 2 of the FPC 1 and the input protruding electrodes 3 of the semiconductor device 11 are aligned with each other. Then, the anisotropic conductive sheet 6 is thermocompression-bonded from the FPC1 side under the conditions of a temperature of 170 to 180 ° C., a pressure of 30 to 50 kg / cm 2 , and a time of 15 to 30 seconds, so that the FPC1 and the semiconductor device 11 are connected. Glue.
【００８６】これにより、金属配線２と入力突起電極３
との間の異方導電性シート６を構成する導電粒がつぶ
れ、金属配線２と入力突起電極３とが接続される。As a result, the metal wiring 2 and the input protruding electrode 3 are formed.
The conductive particles that form the anisotropic conductive sheet 6 between and are crushed, and the metal wiring 2 and the input protruding electrode 3 are connected.
【００８７】最後に図示はしていないが、エポキシ系や
シリコン系樹脂をＦＰＣ１と半導体装置１１との周辺領
域に形成し、ＦＰＣ１や半導体装置１１を保護する。Finally, although not shown, an epoxy resin or a silicon resin is formed in the peripheral region between the FPC 1 and the semiconductor device 11 to protect the FPC 1 and the semiconductor device 11.
【００８８】さらに半導体装置１１とＦＰＣ１との接続
強度を増加するために、半導体装置１１の裏面から保護
粘着テ−プを用いてＦＰＣ１に張り付ける方が好まし
い。Further, in order to increase the connection strength between the semiconductor device 11 and the FPC 1, it is preferable to stick it to the FPC 1 from the back surface of the semiconductor device 11 using a protective adhesive tape.
【００８９】第２の実施例では、半導体装置１１の入力
突起電極３と、ＦＰＣ１の金属配線２との接続におい
て、異方導電性シ−ト６を用いた。しかしながら、入力
突起電極３と金属配線２を直接金属共晶により接続する
ことも可能である。In the second embodiment, the anisotropic conductive sheet 6 is used for the connection between the input protruding electrode 3 of the semiconductor device 11 and the metal wiring 2 of the FPC 1. However, it is also possible to directly connect the input protruding electrode 3 and the metal wiring 2 with a metal eutectic.
【００９０】この金属共晶により入力突起電極３と金属
配線２とを接続する場合、入力突起電極３を金メッキで
作成し、ＦＰＣ１上の金属配線２は、スズの無電解メッ
キを施しておく。When the input protruding electrode 3 and the metal wiring 2 are connected by this metal eutectic, the input protruding electrode 3 is formed by gold plating, and the metal wiring 2 on the FPC 1 is electroless plated with tin.
【００９１】そして入力突起電極３と金属配線２とを、
温度３００〜３５０℃で加圧することで、金−スズ合金
化が起こり、入力突起電極３と金属配線２とを接続する
ことができる。The input protruding electrode 3 and the metal wiring 2 are
By pressurizing at a temperature of 300 to 350 ° C., gold-tin alloying occurs, and the input protruding electrode 3 and the metal wiring 2 can be connected.
【００９２】第２の実施例では、半導体装置１１を基板
１６に接続後、ＦＰＣ１を半導体装置１１に接続した
が、これとは逆手順に、ＦＰＣ１を半導体装置１１の入
力突起電極３と接続後、半導体装置１１の出力突起電極
１０を基板１６の出力接続電極７とを導電性接着剤１８
を用いて接続することも可能である。In the second embodiment, the semiconductor device 11 was connected to the substrate 16 and then the FPC 1 was connected to the semiconductor device 11. However, the FPC 1 was connected to the input protruding electrode 3 of the semiconductor device 11 in the reverse procedure. The output bump electrode 10 of the semiconductor device 11 is connected to the output connection electrode 7 of the substrate 16 by the conductive adhesive 18.
It is also possible to connect using.
【００９３】その場合、導電性接着剤１８の熱硬化中に
ＦＰＣ１が剥がれないように、異方導電性シ−ト６で接
続する方法より、金属共晶接続法を用いて入力突起電極
３と金属配線２とを接続する方が好ましい。In this case, in order to prevent the FPC 1 from peeling off during the thermal curing of the conductive adhesive 18, a metal eutectic connection method is used instead of the method of connecting with the anisotropic conductive sheet 6, so that the FPC 1 is connected to the input protruding electrode 3. It is preferable to connect to the metal wiring 2.
【００９４】以上説明した実施例１および実施例２にお
いては、半導体装置１１の出力突起電極１０と、基板１
６の出力接続電極７とを、導電性接着剤１８を用いて接
続した例で説明を行った。In the first and second embodiments described above, the output bump electrode 10 of the semiconductor device 11 and the substrate 1 are arranged.
The output connection electrode 7 of No. 6 is connected with the conductive adhesive 18 as an example.
【００９５】しかしながら、導電性接着剤１８の代わり
に、異方導電性シ−トや、エポキシ系などの接着剤中に
導電粒あるいは表面に導電処理を施した導電性ビ−ズを
数パ−セント混入した異方導電性接着剤や、エポキシ系
などの接着剤中に外周を薄く絶縁コ−トした導電粒を数
パ−セント混入した異方導電性接着剤を用いて、出力突
起電極１０と出力接続電極７とを接続することも可能で
ある。However, in place of the conductive adhesive 18, a conductive particle or a conductive bead having a surface subjected to a conductive treatment is used in an anisotropic conductive sheet or an adhesive such as an epoxy adhesive. Using the anisotropic conductive adhesive mixed with cents or the anisotropic conductive adhesive mixed with several percent of conductive particles whose outer periphery is thinly coated in an adhesive such as an epoxy-based adhesive, the output projection electrode 10 is used. It is also possible to connect the and the output connection electrode 7.
【００９６】またさらに、導電性接着剤１８を用いる代
わりに、半導体装置１１の出力突起電極１０と、基板１
６の出力接続電極７とを加圧して接続し、加圧したまま
光硬化性接着剤を流し込み、光を照射して硬化させて、
出力突起電極１０と出力接続電極７とを接続することも
可能である。Furthermore, instead of using the conductive adhesive 18, the output bump electrode 10 of the semiconductor device 11 and the substrate 1 are used.
The output connection electrode 7 of 6 is pressed and connected, and the photocurable adhesive is poured under pressure and irradiated with light to be cured,
It is also possible to connect the output protruding electrode 10 and the output connection electrode 7.
【００９７】[0097]
【発明の効果】以上の説明で明らかなように、本発明の
半導体装置の接続構造では、ＣＯＧ法の特徴である半導
体装置の出力接続パッドと基板の出力接続電極の接続を
高密度で実現しながら、半導体装置への入力抵抗を数オ
−ム以下で接続でき、入力電源電圧が安定することによ
り、表示装置のクロスト−ク現象を低減することができ
る。As is apparent from the above description, in the semiconductor device connection structure of the present invention, the connection between the output connection pad of the semiconductor device and the output connection electrode of the substrate, which is a feature of the COG method, is realized with high density. However, since the input resistance to the semiconductor device can be connected within a few ohms and the input power supply voltage is stabilized, the crosstalk phenomenon of the display device can be reduced.
【００９８】またさらに、従来ＣＯＧ法では、入力抵抗
を低減するために小型液晶パネルでも、シ−ト抵抗が１
０〜２０オ−ムの低抵抗ＩＴＯを使用していたが、本発
明の接続構造ではシ−ト抵抗１００オ−ム程度のＩＴＯ
でも使用可能なため、低コスト化が可能である。Furthermore, in the conventional COG method, even in a small liquid crystal panel, the sheet resistance is reduced to 1 in order to reduce the input resistance.
Although low resistance ITO of 0 to 20 ohms was used, ITO having a sheet resistance of about 100 ohms was used in the connection structure of the present invention.
However, since it can be used, the cost can be reduced.
【００９９】さらに、ＣＯＧ法では従来必要であった入
力接続電極のＦＰＣの接続部に相当する２〜３ｍｍの基
板スペ−スが不用になる。このため、基板外形の小型化
を達成することが実現し、それにより１枚の基板からの
取り個数増加による低コスト化を図ることが可能とな
る。Further, in the COG method, the substrate space of 2 to 3 mm corresponding to the FPC connection portion of the input connection electrode, which has been conventionally required, becomes unnecessary. For this reason, it is possible to achieve the miniaturization of the outer shape of the substrate, and thereby it is possible to reduce the cost by increasing the number of substrates taken from one substrate.
【図１】本発明の第１の実施例における半導体装置を示
す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例における半導体装置を示
す断面図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】従来例における半導体装置を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a semiconductor device in a conventional example.
【図４】従来例における半導体装置を示す断面図であ
る。FIG. 4 is a cross-sectional view showing a semiconductor device in a conventional example.
【図５】従来例における半導体装置と基板との接続構造
を示す断面図である。FIG. 5 is a cross-sectional view showing a connection structure between a semiconductor device and a substrate in a conventional example.
【図６】本発明の実施例における半導体装置に設ける突
起電極を示す断面図である。FIG. 6 is a cross-sectional view showing a protruding electrode provided in a semiconductor device according to an example of the present invention.
【図７】本発明の第１の実施例における半導体装置の出
力突起電極と基板の出力接続電極との実装構造を示す断
面図である。FIG. 7 is a cross-sectional view showing a mounting structure of the output projecting electrode of the semiconductor device and the output connecting electrode of the substrate in the first embodiment of the present invention.
【図８】本発明の第２の実施例における半導体装置の出
力突起電極と基板の出力接続電極との実装構造を示す断
面図である。FIG. 8 is a cross-sectional view showing a mounting structure of an output projecting electrode of a semiconductor device and an output connecting electrode of a substrate according to a second embodiment of the present invention.
１ フレキシブル印刷基板（ＦＰＣ） ２ 金属配線 ３ 入力突起電極 ４ 金属細線 ６ 異方導電性シ−ト ７ 出力接続電極 １０ 出力突起電極 １１ 半導体装置 １６ 基板 １８ 導電性接着剤 DESCRIPTION OF SYMBOLS 1 Flexible printed circuit board (FPC) 2 Metal wiring 3 Input protruding electrode 4 Metal thin wire 6 Anisotropic conductive sheet 7 Output connecting electrode 10 Output protruding electrode 11 Semiconductor device 16 Substrate 18 Conductive adhesive
Claims (7)
と、入力突起電極と出力突起電極とを有する半導体装置
と、出力接続電極を有する基板と、出力突起電極と出力
接続電極とを接続する導電性接着剤と、フレキシブル印
刷基板と半導体装置とを固定する接着剤と、入力突起電
極と金属配線とを接続する金属細線とを備えることを特
徴とする半導体装置。1. A flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, and a conductive adhesive connecting the output protruding electrode and the output connecting electrode. A semiconductor device comprising: an agent, an adhesive for fixing the flexible printed circuit board and the semiconductor device, and a thin metal wire connecting the input protruding electrode and the metal wiring.
と、入力接続パッドと出力接続パッド上の出力突起電極
とを有する半導体装置と、出力接続電極を有する基板
と、出力突起電極と出力接続電極とを接続する導電性接
着剤と、フレキシブル印刷基板と半導体装置とを固定す
る接着剤と、入力突起電極と金属配線とを接続する金属
細線とを備えることを特徴とする半導体装置。2. A flexible printed board having metal wiring, a semiconductor device having an input connection pad and an output protruding electrode on the output connection pad, a substrate having an output connecting electrode, an output protruding electrode and an output connecting electrode. A semiconductor device comprising: a conductive adhesive for connection; an adhesive for fixing a flexible printed circuit board and a semiconductor device; and a thin metal wire for connecting an input protruding electrode and a metal wiring.
と、入力突起電極と出力突起電極とを有する半導体装置
と、出力接続電極を有する基板と、出力突起電極と出力
接続電極とを接続する導電性接着剤と、入力突起電極と
金属配線とを接続する異方導電性シ−トとを備えること
を特徴とする半導体装置。3. A flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, and a conductive adhesive connecting the output protruding electrode and the output connecting electrode. A semiconductor device comprising an agent and an anisotropic conductive sheet for connecting the input protruding electrode and the metal wiring.
と、入力突起電極と出力突起電極とを有する半導体装置
と、出力接続電極を有する基板と、出力突起電極と出力
接続電極とを接続する導電性接着剤を備え、入力突起電
極と金属配線との接続は金属共晶を用いて行うことを特
徴とする半導体装置。4. A flexible printed board having metal wiring, a semiconductor device having an input protruding electrode and an output protruding electrode, a substrate having an output connecting electrode, and a conductive adhesive connecting the output protruding electrode and the output connecting electrode. A semiconductor device comprising an agent, wherein a metal eutectic is used to connect the input protruding electrode and the metal wiring.
は、異方導電性シ−トを用いて行うことを特徴とする請
求項１、請求項２、請求項３、あるいは請求項４に記載
の半導体装置。5. The anisotropic conductive sheet is used to connect the output projection electrode and the output connection electrode, and the output projection electrode and the output connection electrode are connected by an anisotropic conductive sheet. The semiconductor device described.
は、異方導電性接着剤を用いて行うことを特徴とする請
求項１、請求項２、請求項３、あるいは請求項４に記載
の半導体装置。6. The connection between the output projection electrode and the output connection electrode is performed by using an anisotropic conductive adhesive, claim 1, claim 2, claim 3, or claim 4. Semiconductor device.
は、光硬化性接着剤を用いて行うことを特徴とする請求
項１、請求項２、請求項３、あるいは請求項４に記載の
半導体装置。7. The connection between the output projection electrode and the output connection electrode is performed by using a photo-curable adhesive, according to claim 1, claim 2, claim 3, or claim 4. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2600693A JP3340779B2 (en) | 1993-01-22 | 1993-01-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2600693A JP3340779B2 (en) | 1993-01-22 | 1993-01-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06224256A true JPH06224256A (en) | 1994-08-12 |
| JP3340779B2 JP3340779B2 (en) | 2002-11-05 |
Family
ID=12181616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2600693A Expired - Fee Related JP3340779B2 (en) | 1993-01-22 | 1993-01-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3340779B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001255551A (en) * | 2000-03-10 | 2001-09-21 | Seiko Epson Corp | Liquid crystal device and its manufacturing method |
| JP2005301056A (en) * | 2004-04-14 | 2005-10-27 | Hitachi Displays Ltd | Display apparatus and manufacturing method for same |
| JP2007081093A (en) * | 2005-09-14 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102396760B1 (en) * | 2015-04-08 | 2022-05-11 | 삼성디스플레이 주식회사 | Display device |
| KR102391249B1 (en) * | 2015-05-28 | 2022-04-28 | 삼성디스플레이 주식회사 | Display device |
-
1993
- 1993-01-22 JP JP2600693A patent/JP3340779B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001255551A (en) * | 2000-03-10 | 2001-09-21 | Seiko Epson Corp | Liquid crystal device and its manufacturing method |
| JP2005301056A (en) * | 2004-04-14 | 2005-10-27 | Hitachi Displays Ltd | Display apparatus and manufacturing method for same |
| US7948080B2 (en) | 2004-04-14 | 2011-05-24 | Hitachi Displays, Ltd. | Display device and manufacturing method of the same |
| JP2007081093A (en) * | 2005-09-14 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3340779B2 (en) | 2002-11-05 |
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