JPH0567058B2 - - Google Patents

Info

Publication number
JPH0567058B2
JPH0567058B2 JP13396687A JP13396687A JPH0567058B2 JP H0567058 B2 JPH0567058 B2 JP H0567058B2 JP 13396687 A JP13396687 A JP 13396687A JP 13396687 A JP13396687 A JP 13396687A JP H0567058 B2 JPH0567058 B2 JP H0567058B2
Authority
JP
Japan
Prior art keywords
chip
wiring board
rubber
resin
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13396687A
Other languages
Japanese (ja)
Other versions
JPS63299242A (en
Inventor
Takumi Suda
Akio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Priority to JP13396687A priority Critical patent/JPS63299242A/en
Publication of JPS63299242A publication Critical patent/JPS63299242A/en
Publication of JPH0567058B2 publication Critical patent/JPH0567058B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【発明の詳现な説明】 産業䞊の利甚分野 本発明は簡単な構造でありながら信頌性が高
く、薄型化が可胜であり、しかも安䟡に半導䜓集
積回路以䞋ICずいうチツプずガラス基板ず
を接続するこずが可胜な半導䜓装眮の接続方法に
関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention has a simple structure, high reliability, can be made thin, and is inexpensive. The present invention relates to a method for connecting a semiconductor device that can connect a semiconductor device to a semiconductor device.

埓来の技術ずその問題点 近幎ドツトマトリクスLCD、ドツトマトリク
スPDP等の平面デむスプレむは、䟋えばLCD−
TV、パ゜コン甚デむスプレむずしお実甚商品化
されおいるが、衚瀺すべき情報量の増加にずもな
぀お、80、桁×25桁640×400ドツトずいう、
埓来よりデむスプレむずしお甚いられおいる
CRTに匹敵する衚瀺胜力を持぀た倧型のものが
商品化されるに至぀おいる。こうした倧型デむス
プレむに぀いおはシリコヌンゎムにカヌボンブラ
ツクを配合・分散した導電性シリコヌンゎムず絶
瞁性シリコヌンゎムずを亀互に積局茉眮したいわ
ゆるれブラタむプのを䜿甚しお、デむスプレむを
駆動するためのICを搭茉したプリント配線基板
を接続する方法があるが、これには接続ピツチを
小さくするず䜍眮合わせや接続抵抗に支障がある
ために、ある皋床以䞊の小型化は䞍可胜であり、
さらにはそうしたコネクタは圧瞮状態で保持しな
ければならないので、デむスプレむデバむスが倧
型化した堎合には保持機構党䜓を倧型堅牢なもの
にしなければならず、軜量化・薄型化は望めない
ずいう䞍利がある。
(Prior art and its problems) In recent years, flat displays such as dot matrix LCDs and dot matrix PDPs have been
It has been commercialized as a display for TVs and personal computers, but as the amount of information to be displayed has increased, the number of displays has increased to 80 digits x 25 digits (640 x 400 dots).
Traditionally used as a display
Large-sized devices with display capabilities comparable to CRTs have been commercialized. For such large displays, we use a so-called zebra-type material, which is made by alternately laminating conductive silicone rubber and insulating silicone rubber, which are silicone rubber mixed with and dispersed with carbon black, and equipped with an IC to drive the display. There is a method of connecting printed wiring boards that have been made smaller, but since reducing the connection pitch causes problems with alignment and connection resistance, it is impossible to reduce the size beyond a certain level.
Furthermore, since such connectors must be held in a compressed state, if the display device becomes larger, the entire holding mechanism must be large and robust, which is disadvantageous in that it cannot be expected to be lighter or thinner. .

これに察しお、䜎融点の熱可塑性暹脂䞭に金属
粉、黒鉛粉、炭玠繊維等のような導線性成分を配
合・分散させた異方導電性ヒヌトコネクタを䜿甚
するこずにより、䞊䟋のれブラタむプコネクタの
䞍利を解決しようずする詊みもあるが、これを䜿
甚した接続は熱可塑性暹脂が高枩時䟋えば70
℃には接着力が極床に䜎䞋するし、たたこうし
た匱点を補うためには接続郚分を圧瞮保持する機
構を远加する必芁があるなど充分な性胜を有する
ものはなく、さらにはここに䜿甚されおいる導電
性成分ずしおは数10Όの盎埄を有するものを䜿
甚する必芁があり、これらがランダムに混合され
おいるものであるこずから、埮小ピツチにおいお
は、隣接する電極同志の絶瞁性が損なわれお暪導
通による䞍良をひきおこす䞍利があり、接続ピツ
チは0.2mmが限界ずいわれおいる。
In contrast, by using an anisotropic conductive heat connector in which conductive components such as metal powder, graphite powder, carbon fiber, etc. are blended and dispersed in a low-melting thermoplastic resin, the zebra Although some attempts have been made to overcome the disadvantages of type connectors, connections using these types of
℃), the adhesion strength is extremely reduced, and to compensate for these weaknesses, it is necessary to add a mechanism to compress and hold the connected parts. It is necessary to use conductive components with a diameter of several tens of micrometers, and since these components are randomly mixed, the insulation between adjacent electrodes may be impaired in minute pitches. This has the disadvantage of causing defects due to lateral conduction, and the connection pitch is said to be limited to 0.2mm.

たた、この接続に぀いおは第図に瀺したよう
に、ICチツプ䞊のボンデむング・パツド
ず長尺のポリむミドフむルムに銅箔を
匵り付け、これを゚チチングしお配線基板ず接続
するための導線を圢成したTAB方匏も知られお
いる。これは導線がICチツプや配線基板ず䞀括
しお䜍眮合せされるために䜍眮決め粟床が高く、
か぀接続に芁する䜜業時間が短いずいう利点があ
るほか、ICチツプずそれが接続される配線基板
ずの熱膚匵率の差違によるストレスをこの導線
が吞収するずいう利䟿性があるが、その反面、予
めICチツプのボンデむング・パツドにめ぀きな
どによ぀お突起状電極バンプを蚭けるか、も
しくは導線のICチツプず接続する郚分を゚ツチ
ング等によ぀お凞状郚を圢成しなければならず、
ICチツプの補品歩留たりを䜎䞋させるなどコス
トアツプは免れない。さらに、TAB−ICのアり
タヌリヌドをガラス基板にボンデむングしようず
する堎合には、ガラス基板のITO膜パタヌンを
Cr、Ni、Au等の金属でめ぀きしおボンデむング
可胜なものずする必芁があり、コスト的に満足の
いくものにはならない。
Regarding this connection, as shown in FIG.
A TAB method is also known in which a copper foil 14 is attached to a long polyimide film 13 and etched to form a conductive wire for connection to a wiring board. This has high positioning accuracy because the conductor wires are aligned with the IC chip and wiring board all at once.
In addition to having the advantage of shortening the work time required for connection, this conductor 7 also reduces the stress caused by the difference in thermal expansion coefficient between the IC chip and the wiring board to which it is connected.
However, on the other hand, it is necessary to provide protruding electrodes (bumps) on the bonding pad of the IC chip in advance by plating, or to etch the part of the conductor that connects to the IC chip. Therefore, a convex portion must be formed,
It is inevitable that costs will increase, such as by lowering the product yield of IC chips. Furthermore, when bonding the outer leads of TAB-IC to a glass substrate, the ITO film pattern on the glass substrate must be
It is necessary to make it bondable by plating with metal such as Cr, Ni, Au, etc., which is not satisfactory in terms of cost.

なお、以䞊のような方法ではICチツプの他に
パツケヌゞや導線などのスペヌスが必芁であり、
電子機噚を小型・軜量の物ずするには至らなか぀
たこずから、第図に瀺したようにICチツプ
のボンデむング・パツドの䞊に半田合金に
よるバンプを蚭けお、配線基板䞊の電極
ず電気的接続をしお実装面積をICチツプの
倧きさずほが等しくしたフリツプチツプ法が提案
されおいるが、この方法では半田バンプの数が倚
くなるずその特性や圢状にばら぀きが生じ、た
た、配線基板の平面床の良吊によ぀お接合匷床も
䞍均䞀になるし、これに぀いおは䞊蚘したように
配線基板ずICチツプの熱膚匵率の差によ぀お生
ずるストレスが半田バンプを砎壊するおそれがあ
り、電気的に信頌性のある接続ずは蚀いがたいず
いう䞍利があり、たた、ガラス基板に接続するた
めには前蚘した様なめ぀き凊理が必芁であり、小
型軜量化ずコストダりンを䞡立させるこずは困難
である。
Note that the above method requires space for the package, conductors, etc. in addition to the IC chip.
Since it was not possible to make electronic equipment small and lightweight, the IC chip 1 was developed as shown in Figure 4.
A flip-chip method has been proposed in which bumps 15 made of solder alloy are provided on bonding pads 12 of 1 and electrically connected to electrodes 17 on a wiring board 16 so that the mounting area is approximately equal to the size of an IC chip. However, with this method, as the number of solder bumps increases, their characteristics and shapes vary, and the bonding strength also becomes uneven depending on the flatness of the wiring board. There is a disadvantage that the stress caused by the difference in thermal expansion coefficient between the board and the IC chip may destroy the solder bumps, making it difficult to say that the connection is electrically reliable. In order to achieve this, the above-mentioned plating process is required, and it is difficult to achieve both size reduction and cost reduction.

さらにガラス基板䞊にICチツプを盎接実装す
る方法ずしお、䟋えばポリむミドフむルムなどの
プラスチツクフむルムにICチツプのボンデむン
グ・パツドに合わせた穎を明け、この䞭にカヌボ
ンブラツクを添加した導電性゚ラストマヌを充填
しお䜜぀た導電性ゎムコネクタをガラス基板ず
ICチツプの間に眮いお䜍眮合せをしたのち、バ
ネ性を持぀た抌え金具で固定する方法が提案され
おいるが、これにはプラスチツクフむルムにフア
むンピツチで小埄の穎を明けるのが難しく、打ち
抜き金型等も非垞に高䟡なものずなるずいう䞍利
があるために、このガラス基板䞊ぞのICチツプ
の盎接実装法は未だに満足すべきものが確立され
おいない。
Furthermore, as a method for directly mounting an IC chip on a glass substrate, for example, holes are made in a plastic film such as polyimide film to match the bonding pads of the IC chip, and the holes are filled with a conductive elastomer containing carbon black. The conductive rubber connector we made was connected to a glass substrate.
A method has been proposed in which the chips are placed between the IC chips, aligned, and then fixed with a spring-loaded presser metal fitting. Because of the disadvantage that the mold etc. are very expensive, a satisfactory method of directly mounting IC chips on a glass substrate has not yet been established.

そのため、本発明者らはICチツプのボンデむ
ング・パツドず配線基板の電極ずを匟性を有する
導電性突状䜓ゎムバンプを介しお接続しおな
る半導䜓装眮を提案し特願昭61−299639号明现
曞参照、これによればICチツプず配線基板ずの
接続が簡単で䜜業時間が短瞮されるにもかかわら
ず、高い信頌正で薄型化が達成されるけれども、
これに぀いおはそのゎムパツドの圢成がICチツ
プの衚面に硬化埌にゎム匟性を瀺すようになる導
電性ゎム組成物を含有する導電性むンクを塗垃し
たのち、この䞊にボンデむング・パツドの配眮ず
同様の開口郚を有するニツケル板、ステンレス板
等の金属板からなるマスク板をボンデむング・パ
ツドに䜍眮合せしお重ね、぀いでこのマスク板の
開口郚をキセノンランプ、ハロゲンランプなどで
スポツト加熱するか、この開口郚に氎銀ランプか
らの玫倖光をスポツト照射しおこの開口郚に面し
た導電性むンクを局を硬化させ、぀ぎにこのマス
ク板を取り倖しおボンデむング・パツドず接しお
いない郚分の未硬化導電性むンク局を溶剀を甚い
お溶剀陀去するか、あるいはICチツプの衚面に
䜍眮合せしお重ねたマスク板開口郚に䞊蚘した導
電性むンクをスクリヌン印刷し、マスク板を取り
倖しお導電性むンクを硬化たたは也燥するずいう
方法で䜜られるので、これが工業的にかなりの困
難を䌎うずいう䞍利がある。すなわちこれに䜿甚
するスクリヌン版に぀いおは印刷されたゎムバン
プが±5Ό皋床の高床な䜍眮粟床を必芁ずする
こずず、その高さを20〜50Όずしなければなら
ないために、ニツケル板や、ステンレス板に゚ツ
チング法で所定䜍眮に穎を明けおパタヌニングし
た物を䜿甚するのが奜適ずされおいるが、これを
利甚したスクリヌン版では、ICチツプに察しお
高粟床に䜍眮合わせするこずが困難であるこずが
わかる。぀たり、このスクリヌン版が前蚘した様
な金属板を䜿甚するため被印刷物であるICチツ
プのボンデむング・パツドを透かし芋お確認しな
がら䜍眮合わせするこずができず、さらに、スク
リヌン印刷を実行するためには、被印刷物である
ICチツプずスクリヌン版ずの間に少なくずも
mm皋床のクリアランスを蚭ける必芁があるが、ク
リアランスのある状態で䜍眮合わせが完党にでき
たずしおも、スキヌゞがある䞀定の印圧でこのク
リアランスに盞圓するだけスクリヌン版を匕き䌞
ばしながら印刷されるために、スクリヌン版の匕
き䌞ばされた状態を再珟できるわけではなく、そ
の䜍眮合わせは䞍充分なもので、この方法によれ
ば䞊蚘したような±5Ό皋床の高床な印刷物を
埗るこずは困難ず蚀わざるを埗ない。
Therefore, the present inventors proposed a semiconductor device in which the bonding pads of an IC chip and the electrodes of a wiring board are connected via elastic conductive protrusions (rubber bumps) (Japanese Patent Application No. 61-299639). According to this method, the connection between the IC chip and the wiring board is easy and the working time is shortened, and a thinner structure is achieved with high reliability.
In this case, the rubber pads are formed by applying a conductive ink containing a conductive rubber composition that exhibits rubber elasticity after curing to the surface of the IC chip, and then forming an opening similar to the arrangement of the bonding pad on the surface of the IC chip. A mask plate made of a metal plate, such as a nickel plate or a stainless steel plate, is aligned and overlapped with the bonding pad, and then the openings of this mask plate are spot-heated with a xenon lamp, halogen lamp, etc., or the openings are The conductive ink layer facing this opening is cured by spot irradiation with ultraviolet light from a mercury lamp, and then the mask plate is removed and the uncured conductive ink layer is exposed to the area not in contact with the bonding pad. Either use a solvent to remove the conductive ink, or screen print the conductive ink described above on the opening of the mask plate aligned and stacked on the surface of the IC chip, remove the mask plate, and cure or dry the conductive ink. Since it is produced by this method, it has the disadvantage of being industrially quite difficult. In other words, for the screen plate used for this, the printed rubber bumps require a high degree of positional accuracy of about ±5 Όm, and the height must be 20 to 50 Όm, so we used nickel or stainless steel plates. It is said that it is preferable to use a screen plate that has been patterned by drilling holes at predetermined positions using the etching method, but it is difficult to align the screen plate with high precision with respect to the IC chip using this method. I understand. In other words, since this screen plate uses a metal plate like the one described above, it is not possible to align the bonding pads of the IC chip to be printed by looking through them, and furthermore, in order to perform screen printing, is the substrate to be printed
At least 1 unit between the IC chip and the screen version
It is necessary to provide a clearance of about mm, but even if the alignment is completed with the clearance, the squeegee will print while stretching the screen plate by the amount equivalent to this clearance with a certain printing pressure. However, it is not possible to reproduce the stretched state of the screen plate, and the alignment is insufficient, so it must be said that it is difficult to obtain high-quality printed matter of about ±5 Όm as described above using this method. I don't get it.

発明の構成 本発明はこの匟性を有する導電性突状䜓を䜿甚
するICチツプのボンデむング・パツドず配線基
板ずの接続方法の改良に関するものであり、これ
は易剥離性フむルム䞊に導電性むンク局を印刷
し、これを半導䜓集積回路チツプの入出力端子た
たは配線基板の電極に圓接加熱しおこの導電性む
ンク局を匟性を有する導電性突状䜓ずしお半導䜓
集積回路の入出力端子たたは配線基板の電極䞊に
転写したのち易剥離性フむルムを剥離し、぀いで
これに配線基板の電極たたは半導䜓集積回路の入
出力端子を圓接し、加熱するこずを特城ずするも
のである。
(Structure of the Invention) The present invention relates to an improvement in a method for connecting an IC chip bonding pad and a wiring board using this elastic conductive protrusion. An ink layer is printed, and it is brought into contact with an input/output terminal of a semiconductor integrated circuit chip or an electrode of a wiring board and heated, and the conductive ink layer is used as an elastic conductive protrusion to be applied to an input/output terminal of a semiconductor integrated circuit or an electrode of a wiring board. After being transferred onto the electrodes of the wiring board, the easily peelable film is peeled off, and then the electrodes of the wiring board or the input/output terminals of the semiconductor integrated circuit are brought into contact with the film and heated.

すなわち、本発明者らは半導䜓集積回路チツプ
の出入力端子ず配線基板の電極ずを匟性を有する
導電性突状䜓以䞋これをゎムバンプず略蚘す
るで接続する方法における前蚘した䞍利を解決
する方法に぀いお皮々怜蚎した結果、ポリ゚チレ
ン暹脂、ポリプロピレン暹脂などのような易剥離
性フむルム䞊にICチツプのボンデむング・パツ
ドたたは配線基板䞊の電極の配眮ず同様の開口郚
を化孊゚ツチング法によ぀お開口させた金属板の
開口郚に硬化したずきにゎム状匟性䜓を瀺す導電
性むンキを泚入しお易剥離性フむルムのボデむン
グ・パツドたたは電極の配眮ず同様の䜍眮に導電
性むンキ局を蚭けたのち、これをICチツプたた
は配線基板䞊に圓接し、この裏偎からホツトプレ
スするずこの導電性むンク局が硬化しおゎムバン
プになるず共に、これがICチツプたたは配線基
板䞊に転写されるので、これから易剥離性フむル
ムを剥離し、぀いでICチツプず配線基板ずを圓
接し加熱するずこのゎムバンプが溶解しおICチ
ツプたたは配線基板に接着䞀䜓化されるのでこの
ゎムバンプを介しおICチツプず配線基板ずが電
気的に完党に接觊されたものになるずいうこずを
芋出し、こゝに䜿甚する易剥離性フむルム、導電
性むンキの組成物などに぀いおの研究を進めお本
発明を完成させた。
That is, the present inventors solved the above-mentioned disadvantages in the method of connecting input/output terminals of a semiconductor integrated circuit chip and electrodes of a wiring board using elastic conductive protrusions (hereinafter referred to as rubber bumps). As a result of various studies on methods, we found that openings similar to the bonding pads of IC chips or electrodes on wiring boards were created on easily peelable films such as polyethylene resin and polypropylene resin using a chemical etching method. After injecting a conductive ink that exhibits a rubber-like elastic body when cured into the opening of the metal plate, a conductive ink layer is provided at the same position as the bodying pad or electrode of the easily peelable film. When this is brought into contact with an IC chip or wiring board and hot pressed from the back side, this conductive ink layer hardens and becomes a rubber bump, and this is transferred onto the IC chip or wiring board, so that an easily peelable film is formed. When the IC chip and wiring board are peeled off and then brought into contact with each other and heated, this rubber bump melts and is bonded and integrated with the IC chip or wiring board, so that the IC chip and wiring board are completely electrically connected via this rubber bump. The present invention was completed by conducting research on the composition of the easily peelable film and conductive ink to be used in this process.

以䞋これを添付の図面にもずづいお説明する
が、第図は本発明の方法によりICチツプに
ゎムバンプを圢成させたICチツプず配線基板ず
の接続を瀺す瞊断面図、第図は本発明の方法
により配線基板にゎムバンプを圢成させた配線基
板ずICチツプず接続を瀺す瞊断面図を瀺したも
のである。第図におけるICチツプにはそ
の衚面に存圚するボンデむング・パツドに䞊蚘
の方法でゎムバンプが接着䞀䜓化されおおり、
これが配線基板の電極ず接觊されおおり、これ
らが封止甚暹脂で封止されお半導䜓装眮ずされ
るのであるが、第図ではこのゎムバンプが
配線基板の䞊に接着䞀䜓化されおこれがICチ
ツプのボンデむング・パツドず接觊させられ
おいる。
This will be explained below based on the attached drawings. FIG. 1a is a longitudinal cross-sectional view showing the connection between an IC chip and a wiring board in which rubber bumps are formed on the IC chip by the method of the present invention, and FIG. 1 is a longitudinal cross-sectional view showing the connection between an IC chip and a wiring board in which rubber bumps are formed on the wiring board by the method of the present invention. In the IC chip 1 shown in FIG. 1a, a rubber bump 3 is bonded and integrated with a bonding pad 2 existing on the surface thereof by the method described above.
This is in contact with the electrodes of the wiring board 4, and these are sealed with a sealing resin 6 to form a semiconductor device. In FIG. This is brought into contact with the bonding pad 2 of the IC chip 1.

なお、このゎムバンプの易剥離性フむルムぞ
の蚭眮方法は䟋えば第図に瀺したように易剥離
性フむルムを金属性保持枠に緊匵しお接着さ
せたのち、このフむルム䞊にICチツプのボンデ
むング・パツドたたは配線基板䞊の電極の配眮ず
同じ䜍眮に化孊゚ツチングで開口郚を蚭けたニツ
ケル、ステンレスなどで補造した金属プレヌトを
蚭け、この開口郚に導電性むンクを泚入しおこの
フむルム䞊に導電性むンク局を蚭けたのち、ホツ
トプレスするようにすればよい。
The method for installing the rubber bumps 3 on the easily peelable film is, for example, as shown in FIG. A metal plate made of nickel, stainless steel, etc. is provided with openings made by chemical etching at the same positions as the bonding pads or electrodes on the wiring board, and conductive ink is injected into the openings to coat the film. After providing a conductive ink layer on the surface, hot pressing may be performed.

本発明の方法で䜿甚される半導䜓集積回路チツ
プは埓来公知のボンデむング・パツドを蚭けた
ICチツプずすればよく、この配線基板も公知の
ものでよく、これはフリツプチツプ方匏、TAB
方匏など埓来のチツプオンボヌド法によ぀おは接
続するこずが䞍可胜であるLCDのようなガラス
基板であ぀おもよいが、銅匵゚ポキシ暹脂積局
板、銅匵ポリむミド暹脂積局板、銅匵ポリむミド
暹脂フルムなどのような埓来甚いられおいる配線
基板でもよい。
The semiconductor integrated circuit chip used in the method of the present invention is provided with conventionally known bonding pads.
It may be an IC chip, and this wiring board may also be a known one, such as a flip-chip method, a TAB
Glass substrates such as LCDs, which cannot be connected using conventional chip-on-board methods, may be used, but copper-clad epoxy resin laminates, copper-clad polyimide resin laminates, copper-clad polyimide A conventionally used wiring board such as a resin film may be used.

たた、本発明の方法で䜿甚されるゎムバンプを
圢成する導電性むンクは匟性のある導電性ゎム局
を圢成するず共に、加熱時にICチツプたたは配
線基板に接着䞀䜓化されるこずが必芁ずされるの
で、゚チ゚ン−酢酞ビニル共重合暹脂EVA、
゚チレン−アクリル酞゚チル共重合暹脂
EEA、アむオノマヌ暹脂、スチレン−ブタゞ
゚ン共重合暹脂、酢酞ビニル暹脂、アクリル暹
脂、ポリ゚ステル暹脂、塩化ビニル暹脂などの熱
可塑性暹脂、ステヌゞ状態にある可撓性゚ポキ
シ暹脂、シリコヌンゎムなどの熱可塑性暹脂、合
成ゎムなどがあげられ、これらは金、銀、銅、ニ
ツケルなどの金属粉たたはこれらの合金粉、ケツ
チ゚ンブラツク、グラフアむトなどのカヌボン系
の導電粉、あるいは衚面を金やニツケルなどで金
属め぀きしたガラスビヌズなどを導電性付䞎剀ず
しお10〜60容量添加したものから䜜られたもの
ずすればよいが、これに曎に公知の有機過酞化
物、酞無氎物、アミンなどの硬化剀、たたこれら
のゎム成分をプラスチツク、金属、ガラス等に接
着するためのプラむマヌ組成物、玫倖増感剀、光
開始剀、老化防止剀、酞化防止剀などを添加した
ものずするのが奜たしい。
Furthermore, the conductive ink forming the rubber bumps used in the method of the present invention forms an elastic conductive rubber layer and is required to be adhesively integrated with the IC chip or wiring board when heated. , ethene-vinyl acetate copolymer resin (EVA),
Thermoplastic resins such as ethylene-ethyl acrylate copolymer resin (EEA), ionomer resin, styrene-butadiene copolymer resin, vinyl acetate resin, acrylic resin, polyester resin, vinyl chloride resin, flexible epoxy in B-stage state These include resins, thermoplastic resins such as silicone rubber, synthetic rubbers, etc. These include metal powders such as gold, silver, copper, and nickel, or powders of their alloys, carbon-based conductive powders such as ketschen black, graphite, etc. Alternatively, it may be made of glass beads whose surface is plated with gold or nickel, etc., to which 10 to 60% by volume is added as a conductivity imparting agent, and in addition, known organic peroxides, Addition of curing agents such as acid anhydrides and amines, primer compositions for adhering these rubber components to plastics, metals, glass, etc., ultraviolet sensitizers, photoinitiators, anti-aging agents, antioxidants, etc. It is preferable that the

たた、この易剥離性の暹脂フむルムに぀いおは
ポリ゚チレン暹脂、ポリプロピレン暹脂、ポリり
レタン暹脂、゚ポキシ暹脂、テフロン暹脂のほ
か、特に寞法倉化の少ないものずしおポリアリレ
ヌト暹脂やポリむミド暹脂などを䜿甚すればよ
い。
Further, for this easily peelable resin film, in addition to polyethylene resin, polypropylene resin, polyurethane resin, epoxy resin, and Teflon resin, polyarylate resin and polyimide resin may be used as those having particularly little dimensional change.

本発明の方法は䞊蚘したようにICチツプたた
は配線基板にICチツプのボンデむング・パツド
たた電極の䜍眮に察応する䜍眮に導電性むンク局
を蚭けた易剥離性フむルムを圓接し、これを硬化
させおゎムバンプを䜜぀たのちに易剥離性フむル
ムを剥離し、぀いでこれをICチツプたたは配線
基板に接着䞀䜓化させるものであるが、この堎合
に易剥離性フむルムずしお透明なものを䜿甚すれ
ばICチツプず容易に䜍眮合わせをするこずがで
きるばかりか、この方法によればスクリヌン印刷
のようにクリアランスを蚭ける必芁がないので
ICチツプのボンデむング・パツドず高い粟床で
䜍眮合わせをするこずができ、これをスクリヌン
版の劂く金属補保持枠に緊匵しお接着した物
を䜿甚すれば、バンプ圢成の際のゎム状導電性暹
脂をキナアヌするずき、たたこの導電性ゎムバン
プをICチツプに転写するずきなどに加えられる
熱ストレスによるこの易剥離性フむルムの寞法倉
化を極小に抑えるこずができる。たた、この様な
易剥離性フむルムであればその寞法倉化が䜎く抑
えられおいるので倚数回繰り返しお䜿甚するこず
も可胜であり、コストダりンに寄䞎するこずは疑
いもない。
As described above, the method of the present invention involves contacting an IC chip or a wiring board with an easily peelable film provided with a conductive ink layer at positions corresponding to the bonding pads or electrodes of the IC chip, and curing the film. After making the rubber bumps, the easily peelable film is peeled off, and then the film is bonded and integrated with the IC chip or wiring board. Not only can alignment be done easily, but this method also eliminates the need for clearance unlike screen printing.
It is possible to align with the bonding pad of the IC chip with high precision, and if you use something like a screen plate that is glued under tension to the metal holding frame 10, it is possible to use a rubber-like conductive pad when forming bumps. Dimensional changes in this easily peelable film due to heat stress applied when curing the resin or transferring the conductive rubber bumps to an IC chip can be minimized. Further, since such an easily peelable film can suppress dimensional changes to a low level, it can be used repeatedly many times, which undoubtedly contributes to cost reduction.

なお、このようにしお埗られた半導䜓装眮は、
パツケヌゞレスであるために占有面積がICチツ
プのサむズず等しくなるのでこの方法を䜿甚した
電子郚品は小型化するこずができるし、埓来のチ
ツプオンボヌド方匏では、実装・ボンデむングす
る前にICの怜査・スクリヌニングをするこずが
できなか぀たが、この方法によれば適切な圧力を
加えれば倖郚回路ず容易に導通するこずができる
ので、怜査スクリヌニングを簡䟿に行うこずが出
来るずいう利䟿性が䞎えられる。たた、導電性ゎ
ムバンプがゎム匟性を有しおいるので、ICチツ
プずガラス基板ずの熱膚匵係数が敎合しおいなく
おも、バンプがそのストレスを吞収し導電路が砎
壊されるこずがないために高い信頌性が埗られ、
たたガラス基板が平面性の劣るものであ぀おも、
ゎム匟性によ぀おこれに远埓させるこずもでき、
さらにこの接続法によれば、極めお簡単な構成で
あるので安䟡に補造するこずができるずいう有利
性が䞎えられる。
Note that the semiconductor device obtained in this way is
Because it is packageless, the area it occupies is equal to the size of the IC chip, so electronic components using this method can be made smaller.・Although it was not possible to perform screening, this method provides the convenience of easily conducting inspection screening because it is possible to easily establish continuity with an external circuit by applying appropriate pressure. In addition, since the conductive rubber bumps have rubber elasticity, even if the thermal expansion coefficients of the IC chip and the glass substrate do not match, the bumps absorb the stress and the conductive paths are not destroyed. High reliability is obtained,
Furthermore, even if the glass substrate has poor flatness,
This can also be followed by rubber elasticity,
Furthermore, this connection method has the advantage that it has an extremely simple configuration and can be manufactured at low cost.

぀ぎに本発明の実斜䟋をあげるが、䟋䞭の郚は
重量郚を瀺したものである。
Next, examples of the present invention will be given, and parts in the examples indicate parts by weight.

実斜䟋 厚さ50Όのポリむミドフむルム・カプトン
タむプ200V〔東レ・デナポン(æ ª)補商品名〕をスク
リヌン版甚アルミニりム補枠に10Kgcm2で緊匵接
着したのち、この面にニツケル版にICチツプの
ボンデむング・パツドず同様の穎を化孊゚ツチン
グ法で開孔したスクリヌン版を蚭け、こゝにスチ
レン−゚チレン−ブタゞ゚ン−スチレン共重合䜓
暹脂・クレむトン−G1657〔シ゚ル化孊(æ ª)補商品
名〕60郚、粘着性付䞎剀ずしおのテンペルプノ
ヌル共重合暹脂・YSポリスタヌT115〔安原油脂
工業(æ ª)補商品名〕40郚、老化防止剀ずしおのアミ
ン−ケトン系暹脂・ノクラツクAW−〔倧内新
興化孊工業(æ ª)補商品名〕郚を適圓量のトル゚ン
に溶解したのち、350メツシナ以䞋のニツケル粉
700郚、カヌボンブラツク・ケツチ゚ンブラツク
EC〔ラむオンアクゟ(æ ª)補商品名〕10郚を加えおら
い朰機で混合し、䞉本ロヌルで混緎りしお埗た導
電性むンクを泚入しおポリむミドフむルム䞊に導
電性むンク局を印刷したのち、これを120℃、30
分で加熱しおこの導電性むンク局を硬化させおゎ
ムバンプずした。
Example: Polyimide film Kapton V with a thickness of 50 ÎŒm
Type 200V [trade name manufactured by Toray DuPont Co., Ltd.] is tension-bonded to the aluminum frame for the screen plate at 10 kg/cm 2 , and then chemically etched holes similar to the bonding pads for IC chips on the nickel plate are made on this surface. A screen plate with holes made by the method was prepared, and 60 parts of styrene-ethylene-butadiene-styrene copolymer resin Kraton-G1657 (trade name, manufactured by Ciel Chemical Co., Ltd.) and tempelphenol as a tackifier were added. Polymer resin - YS Polyster T115 [trade name manufactured by Yasushi Oil Industries Co., Ltd.] 40 parts, amine-ketone resin as an anti-aging agent - Nokrac AW-N [trade name manufactured by Ouchi Shinko Kagaku Kogyo Co., Ltd.] 2 parts After dissolving in an appropriate amount of toluene, make nickel powder of less than 350 mesh
700 copies, carbon black/button black
Add 10 parts of EC (trade name manufactured by Lion Akzo Co., Ltd.), mix in a crusher, knead with three rolls, inject the obtained conductive ink, and print a conductive ink layer on the polyimide film. After that, heat it at 120℃ for 30
The conductive ink layer was cured into a rubber bump by heating for 20 minutes.

぀ぎに、このポリむミドフむルムのゎムバンプ
局をICチツプに接合したずころ、ゎムバンプ局
がICチツプのボンデむング・パツドに接合した
のでこれからポリむミドフむルムを剥離したの
ち、これにガラス基板を重ねガラス基板䞊の電極
郚をゎムバンプ局に接合させ、これに150℃に加
熱されおいる熱板を圧接したずころ、ゎムバンプ
が溶解しおこれがICチツプのボンデむング・パ
ツドに接合䞀䜓化されたので、この半導䜓装眮に
゚ポキシ暹脂・アラルダむトAY101〔日本チバガ
むギヌ(æ ª)補商品名〕および硬化剀・HY950〔同瀟
補商品名〕の混合物を滎䞋しお封止したずころ、
䞊蚘したゎムバンプ局で導電接着がより匷固ずな
぀た半導䜓装眮が埗られた。
Next, when the rubber bump layer of this polyimide film was bonded to the IC chip, the rubber bump layer was bonded to the bonding pad of the IC chip, so after peeling off the polyimide film, a glass substrate was placed on top of this and the electrode section on the glass substrate. When the rubber bump layer was bonded to the rubber bump layer and a hot plate heated to 150℃ was pressed against it, the rubber bump melted and was integrated into the bonding pad of the IC chip. When a mixture of Araldite AY101 [trade name manufactured by Nippon Ciba Geigy Co., Ltd.] and curing agent HY950 [trade name manufactured by the same company] was dropped and sealed,
A semiconductor device was obtained in which the conductive adhesion was made stronger by the rubber bump layer described above.

【図面の簡単な説明】[Brief explanation of the drawing]

第図は本発明の方法で埗られた半導䜓
装眮の瞊断面図、第図は本発明方法における易
剥離性フむルムに導電性むンク局を蚭ける方法を
瀺した瞊断面図、第図、第図は埓来公知の方
法によるICチツプの実装方法の瞊断面図を瀺し
たものである。   ICチツプ、  ボンデ
むング・パツド、  ゎムバンプ、  
配線基板、  電極、  封止甚暹
脂、  易剥離性フむルム、  金属補保持
枠、  ポリむミドフむルム、  銅
箔、  ハンダ合金バンプ。
FIGS. 1a and 1b are longitudinal cross-sectional views of a semiconductor device obtained by the method of the present invention, and FIG. 3 and 4 are longitudinal cross-sectional views of a method of mounting an IC chip using a conventionally known method. 1 , 11 ...IC chip, 2,12...Bonding pad, 3...Rubber bump, 4,6...
Wiring board, 5, 17... Electrode, 6... Sealing resin, 7... Easily peelable film, 8... Metal holding frame, 13... Polyimide film, 14... Copper foil, 15... Solder Alloy bump.

Claims (1)

【特蚱請求の範囲】[Claims]  易剥離性フむルム䞊に導電性むンク局を印刷
し、これを半導䜓集積回路チツプの入出力端子た
たは配線基板の電極に圓接加熱しおこの導電性む
ンク局を匟性を有する導電性突条䜓ずしお半導䜓
集積回路の入出力端子たたは配線基板の電極䞊に
転写したのち易剥離性フむルムを剥離し、぀いで
これに配線基板の電極たたは半導䜓集積回路の入
出力端子を圓接し、加熱するこずを特城ずする半
導䜓装眮の接続方法。
1. A conductive ink layer is printed on an easily peelable film, and this is brought into contact with input/output terminals of a semiconductor integrated circuit chip or electrodes of a wiring board and heated to form an elastic conductive protrusion. The film is transferred onto the input/output terminals of a semiconductor integrated circuit or the electrodes of a wiring board, the easily peelable film is peeled off, and then the electrodes of the wiring board or the input/output terminals of the semiconductor integrated circuit are brought into contact with the film and heated. A method for connecting semiconductor devices.
JP13396687A 1987-05-29 1987-05-29 Connection of semiconductor device Granted JPS63299242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13396687A JPS63299242A (en) 1987-05-29 1987-05-29 Connection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13396687A JPS63299242A (en) 1987-05-29 1987-05-29 Connection of semiconductor device

Publications (2)

Publication Number Publication Date
JPS63299242A JPS63299242A (en) 1988-12-06
JPH0567058B2 true JPH0567058B2 (en) 1993-09-24

Family

ID=15117245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13396687A Granted JPS63299242A (en) 1987-05-29 1987-05-29 Connection of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63299242A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666355B2 (en) * 1988-12-16 1994-08-24 束䞋電噚産業株匏䌚瀟 Semiconductor device mounting body and mounting method thereof
JPH02185050A (en) * 1989-01-12 1990-07-19 Matsushita Electric Ind Co Ltd Mounting method for semiconductor device
CN102379021B (en) 2009-02-04 2015-07-22 信越聚合物株匏䌚瀟 Capacitance-type input switch

Also Published As

Publication number Publication date
JPS63299242A (en) 1988-12-06

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