JP2793899B2 - Bonding and curing method of resin adhesive - Google Patents

Bonding and curing method of resin adhesive

Info

Publication number
JP2793899B2
JP2793899B2 JP25655090A JP25655090A JP2793899B2 JP 2793899 B2 JP2793899 B2 JP 2793899B2 JP 25655090 A JP25655090 A JP 25655090A JP 25655090 A JP25655090 A JP 25655090A JP 2793899 B2 JP2793899 B2 JP 2793899B2
Authority
JP
Japan
Prior art keywords
adhesive
bonding
resin adhesive
lead frame
insulating sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25655090A
Other languages
Japanese (ja)
Other versions
JPH04133460A (en
Inventor
欽哉 大井川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP25655090A priority Critical patent/JP2793899B2/en
Publication of JPH04133460A publication Critical patent/JPH04133460A/en
Application granted granted Critical
Publication of JP2793899B2 publication Critical patent/JP2793899B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/278Post-treatment of the layer connector
    • H01L2224/27848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、特に所謂、リードフレーム型半導体におい
て半導体チップをリードフレームに実装するために使用
する絶縁シートの接着方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for bonding an insulating sheet used for mounting a semiconductor chip on a lead frame in a so-called lead frame type semiconductor.

〔従来の技術〕[Conventional technology]

半導体装置において、リードフレームを用いて半導体
を実装する際に、中央部に半導体チップ用の開口部が形
成されると共にその表面に導電線パターンが形成された
絶縁シートが使用される。この絶縁シートは、ポリイミ
ドフィルム等の絶縁性フィルムの片面に銅等の金属箔を
張り合わせ又は無電解鍍金等により金属層を形成して成
るその金属表面にレジストを塗布し、更にマスクを用い
て露光することにより焼成し、次いで前記半導体チップ
のための開口部を開設すべく絶縁シートをエッチング等
により開孔せしめ、最後に切断成形されるものである。
第2図及び第3図はかかる絶縁シートを用いて成る従来
のリードフレーム型半導体の構成例を示しているが、図
中、1は半導体チップ2をその中央部に載置するように
なっているアイランド部1aと該アイランド部1aの周囲に
櫛状に配列された多数のアウターリード部1bとから成る
リードフレーム、3はアイランド部1aに載置された半導
体チップ2を所定位置に固定する導電性ペースト、4は
中央部に開口部4aが開設されていてその表面に導電線パ
ターン5が形成された絶縁性フィルムで成る絶縁シー
ト、6は導電線パターン5上に形成された鍍金層、7は
絶縁シート4をアイランド部1aに固定せしめる接着剤、
8は半導体チップ及び導電線パターン5の一端部を接続
するインナーワイヤ8aと該導電線パターン5の他端部及
びアウターリード部1bを接続するアウターワイヤ8bから
成る複数のボンディングワイヤである。そして、絶縁シ
ート4を使用して半導体チップ2を実装するに際して、
先づ、絶縁シート4を接着すべきアイランド部1aの上表
面にエポキシ系,ポリイミド系又はアクリル系樹脂製の
接着剤7を塗布して該絶縁シート4を接着し、次いで絶
縁シート4の開口部4a内に導電性ペースト3を塗布して
この開口部4aを介して半導体チップ2を挿入・載置す
る。ここで、接着剤7は熱硬化性樹脂であるため加熱処
理によって硬化し、これにより絶縁シート4はアイラン
ド部1a上に接着せしめられるが、接着剤7の加熱処理に
おける推奨硬化条件は100℃/1時間,150℃/1時間及び250
℃/1時間の温度条件が設定されていた。アイランド部1a
上に半導体チップ2及び絶縁シート4等が接着される
と、導電線パターン5を介して半導体チップ2及びアウ
ターリード部1bを接続すべくインナーワイヤ8a及びアウ
ターワイヤ8bのワイヤボンディングが行なわれ、これに
よりリードフレーム型半導体が完成する。
In a semiconductor device, when a semiconductor is mounted using a lead frame, an insulating sheet having an opening for a semiconductor chip formed in a central portion and a conductive line pattern formed on the surface thereof is used. This insulating sheet is formed by laminating a metal foil such as copper on one side of an insulating film such as a polyimide film or forming a metal layer by electroless plating or the like, applying a resist on the metal surface, and further exposing using a mask. Then, the insulating sheet is opened by etching or the like so as to open an opening for the semiconductor chip, and finally cut and formed.
2 and 3 show a configuration example of a conventional lead frame type semiconductor using such an insulating sheet. In the drawings, reference numeral 1 designates a semiconductor chip 2 mounted on a central portion thereof. The lead frame 3 includes an island portion 1a and a number of outer lead portions 1b arranged in a comb shape around the island portion 1a. A lead frame 3 fixes the semiconductor chip 2 mounted on the island portion 1a at a predetermined position. The conductive paste 4 is an insulating sheet made of an insulating film having an opening 4a opened in the center and a conductive line pattern 5 formed on the surface thereof, 6 is a plating layer formed on the conductive line pattern 5, 7 Is an adhesive for fixing the insulating sheet 4 to the island portion 1a,
Reference numeral 8 denotes a plurality of bonding wires including an inner wire 8a for connecting one end of the semiconductor chip and the conductive wire pattern 5 and an outer wire 8b for connecting the other end of the conductive wire pattern 5 and the outer lead portion 1b. When mounting the semiconductor chip 2 using the insulating sheet 4,
First, an adhesive 7 made of an epoxy, polyimide or acrylic resin is applied to the upper surface of the island portion 1a to which the insulating sheet 4 is to be bonded, and the insulating sheet 4 is bonded. The conductive paste 3 is applied in 4a, and the semiconductor chip 2 is inserted and placed through the opening 4a. Here, since the adhesive 7 is a thermosetting resin, it is cured by heat treatment, whereby the insulating sheet 4 is adhered on the island portion 1a. The recommended curing condition in the heat treatment of the adhesive 7 is 100 ° C. / 1 hour, 150 ° C / 1 hour and 250
A temperature condition of ° C./1 hour was set. Island part 1a
When the semiconductor chip 2 and the insulating sheet 4 are bonded thereon, the inner wire 8a and the outer wire 8b are wire-bonded to connect the semiconductor chip 2 and the outer lead portion 1b via the conductive wire pattern 5. Thereby, the lead frame type semiconductor is completed.

ところで、近年、リードフレームの需要が増すと共に
その用途も極めて多様化してきている。このため、上述
したような実装工程における生産性の向上及び信頼性の
向上に対する要望は益々強くなってきている。
By the way, in recent years, demands for lead frames have been increasing, and the uses thereof have been extremely diversified. For this reason, there is an increasing demand for improvement in productivity and reliability in the mounting process as described above.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、従来行われていた絶縁シート4の接着
方法では、信頼性等の要望が高まっているにも拘わら
ず、これらの要求を十分に満足することはできなかっ
た。即ち、特に接着剤7の加熱処理における推奨硬化条
件によれば、該接着剤7を短時間で接着・硬化させるこ
とはできるが、接着剤7中に第4図に示したような多数
のボイド(空隙)が発生してしまうという問題があっ
た。そして、この発生したボイドは硬化した接着剤7層
の内部でクッションとして作用し、このクッション作用
のためワイヤボンディング時のキャピラリの圧力を逃が
すことになる結果、ワイヤボンディングを適正に行なう
のが困難になっていた。因みにワイヤボンディングの成
功率は高々5%程度に留まった。
However, the conventional method of bonding the insulating sheet 4 has not been able to sufficiently satisfy these demands, although demands for reliability and the like are increasing. In other words, according to the recommended curing conditions especially in the heat treatment of the adhesive 7, the adhesive 7 can be bonded and cured in a short time, but a large number of voids as shown in FIG. There is a problem that (voids) are generated. The generated void acts as a cushion inside the cured adhesive 7 layer, and the cushioning action releases the pressure of the capillary at the time of wire bonding, which makes it difficult to perform wire bonding properly. Had become. Incidentally, the success rate of wire bonding was at most about 5%.

本発明はかかる実情に鑑み、この種のリードフレーム
型半導体において、適正且つ確実にワイヤボンディング
を行い、半導体チップの良好な接続を図り得る樹脂製接
着剤の接着・硬化方法を提供することを目的とする。
In view of such circumstances, an object of the present invention is to provide a method of bonding and curing a resin adhesive capable of performing proper and reliable wire bonding in this type of lead frame type semiconductor and achieving good connection of a semiconductor chip. And

〔課題を解決するための手段〕[Means for solving the problem]

本発明による樹脂製接着剤の接着・硬化方法は、ワイ
ヤボンディングを行なうための導電線パターンが形成さ
れた絶縁シートをアイランド部に接着する際に、硬化し
ていない樹脂製接着剤に対し樹脂製接着剤中の溶剤が該
接着剤層中で気化し得ないように温度条件を複数段階設
定し、上記樹脂製接着剤をそれぞれの上記温度条件で順
次続けて加熱処理を行ない、徐々に溶剤を蒸発させなが
ら上記樹脂製接着剤を硬化させて上記絶縁シートが上記
アイランド部に接着するようにする。
The method for bonding and curing a resinous adhesive according to the present invention is a method for bonding an uncured resinous adhesive to an uncured resinous adhesive when bonding an insulating sheet on which a conductive wire pattern for performing wire bonding is formed to an island portion. A plurality of temperature conditions are set so that the solvent in the adhesive cannot be vaporized in the adhesive layer, and the resin adhesive is sequentially heated at each of the above temperature conditions, and the heat treatment is performed. The resin adhesive is cured while being evaporated, so that the insulating sheet adheres to the island portion.

又、本発明による樹脂製接着剤の接着・硬化方法は、
樹脂製接着剤をそれ自体が硬化しないような温度で予備
加熱することにより、含有する溶剤の一部を蒸発させて
おき、予備加熱されて含有する溶剤の量が減少した上記
樹脂製接着剤を絶縁シートおよび上記アイランド部に介
在させ、その後所定の加熱処理を施して接着・硬化させ
るようになっている。
Also, the method for bonding and curing the resin adhesive according to the present invention is as follows.
By preheating the resin adhesive at a temperature such that the resin adhesive itself does not cure, a part of the contained solvent is evaporated, and the preheated resin adhesive in which the amount of the contained solvent is reduced. It is interposed between the insulating sheet and the above-mentioned island portion, and then is subjected to a predetermined heat treatment so as to be adhered and cured.

〔作用〕[Action]

本発明によれば、先づ、接着剤を硬化させる際の加熱
処理時に接着剤中の溶剤が、接着剤中で気化しないよう
に温度条件を設定して、これにより接着剤を徐々に硬化
させることができ、この結果、ボイドの発生をなくする
ことができる。そして、ボイドの発生をなくしたことに
より、ワイヤボンディング時のキャピラリの圧力を均一
にして適正なワイヤボンディングを行なうことができ
る。
According to the present invention, first, the solvent in the adhesive during the heat treatment when curing the adhesive, the temperature conditions are set so as not to evaporate in the adhesive, thereby gradually curing the adhesive. As a result, the generation of voids can be eliminated. Then, by eliminating the generation of voids, it is possible to make the pressure of the capillary uniform during wire bonding and perform appropriate wire bonding.

又、本発明によれば、接着剤を予備加熱することによ
り、接着剤中の溶剤の量を予め減少させておき、従っ
て、この場合にもボイドの発生をなくすることができ
る。
Further, according to the present invention, by preheating the adhesive, the amount of the solvent in the adhesive is reduced in advance, and thus, even in this case, generation of voids can be eliminated.

〔実施例〕〔Example〕

以下、第1図に基づき、従来例と同一の部材には同一
の符号を用いて本発明による樹脂製接着剤の接着・硬化
方法の第一実施例を説明する。ここで先づ、本発明方法
を適用すべきリードフレーム型半導体は基本的に第2図
及び第3図に示した従来例のものと同一構成であるもの
とし、従って、絶縁シート4は接着剤7によりリードフ
レーム1のアイランド部1aに接着せしめられる。
Hereinafter, a first embodiment of a method for bonding and curing a resin adhesive according to the present invention will be described with reference to FIG. Here, first, the lead frame type semiconductor to which the method of the present invention is applied has basically the same configuration as that of the conventional example shown in FIGS. 2 and 3, and therefore, the insulating sheet 4 is made of an adhesive. 7 adheres to the island portion 1a of the lead frame 1.

アイランド部1aの所定位置に接着剤7としてのエポキ
シ系樹脂が塗布され、この上に導電線パターン5が形成
されている絶縁シート4は敷設されるが、この後行う接
着剤7に対する加熱処理の温度条件は次のように設定さ
れる。即ち、110℃/18時間,130℃/3時間,150℃/2時間,2
00℃/1時間及び250℃/1時間の夫々の条件で順次続けて
加熱処理が行なわれ、これにより接着剤7は接着・硬化
する。そして、この後に従来例の場合と同様にワイヤボ
ンディングが行なわれる。
An epoxy resin as an adhesive 7 is applied to a predetermined position of the island portion 1a, and an insulating sheet 4 on which a conductive wire pattern 5 is formed is laid thereon. Temperature conditions are set as follows. That is, 110 ° C / 18 hours, 130 ° C / 3 hours, 150 ° C / 2 hours, 2
Heat treatment is sequentially performed under the conditions of 00 ° C./1 hour and 250 ° C./1 hour, whereby the adhesive 7 is bonded and cured. Thereafter, wire bonding is performed in the same manner as in the conventional example.

本発明方法は上記のように構成されており、つまり、
接着剤7の加熱処理の温度条件は、加熱温度が徐々に上
昇するように設定されている。これにより、加熱の際に
接着剤7中で発生する溶剤の蒸気量は、溶剤の接着剤7
中を透過する量を越えないように調整され、従って、溶
剤蒸気が接着剤7中でボイドとなって急激に成長するこ
とはできず、この結果、第1図に示したように、接着剤
7が接着・硬化した状態においてボイドの発生は全くな
い。そして、前記インナーワイヤ8a及びアウターワイヤ
8bのワイヤボンディングを行なう際、上記のようにボイ
ドをなくした接着剤7に対してキャピラリの圧力を均一
にすることができ、これにより適正且つ確実にワイヤボ
ンディングが行なわれる。因みに、ワイヤボンディング
の成功率は95%に達し、従来例の場合の5%に比べて格
段に向上しており、そして、ワイヤボンディング工程の
作業効率を著しく改善することができる。
The method of the present invention is configured as described above, that is,
The temperature condition of the heat treatment of the adhesive 7 is set so that the heating temperature gradually increases. As a result, the amount of vapor of the solvent generated in the adhesive 7 at the time of heating is reduced by the adhesive 7 of the solvent.
It is adjusted so as not to exceed the amount that passes through the inside, so that the solvent vapor cannot be rapidly grown as a void in the adhesive 7, and as a result, as shown in FIG. In the state where No. 7 is bonded and cured, no void is generated. Then, the inner wire 8a and the outer wire
When performing the wire bonding of 8b, the pressure of the capillary can be made uniform with respect to the adhesive 7 having no voids as described above, whereby the wire bonding can be performed properly and reliably. Incidentally, the success rate of wire bonding has reached 95%, which is much higher than that of the conventional example of 5%, and the work efficiency of the wire bonding process can be remarkably improved.

次に、本発明による樹脂製接着剤の接着・硬化方法の
第二実施例を説明する。この第二実施例では、例えばエ
ポキシ系樹脂で成る接着剤7は先づ別に例えば110℃/1
時間の温度条件で予備加熱される。そして、かかる予備
加熱された接着剤7はリードフレーム1のアイランド部
1aに塗布され、ここに絶縁シート4を敷設後に該接着剤
7の接着・硬化を行なうが、このときの加熱処理の温度
条件は150℃/1時間及び250℃/1時間に設定される。
Next, a second embodiment of the method for bonding and curing a resin adhesive according to the present invention will be described. In the second embodiment, for example, an adhesive 7 made of, for example, an epoxy
It is preheated under the temperature condition of time. Then, the preheated adhesive 7 is applied to the island portion of the lead frame 1.
The adhesive 7 is applied and cured after the insulating sheet 4 is laid thereon. The temperature conditions of the heat treatment at this time are set to 150 ° C./1 hour and 250 ° C./1 hour.

この第二実施例においては、接着剤7を予備加熱する
ことによって該接着剤7が含有する溶剤の一部を蒸発せ
しめておくことにより、接着剤7中の溶剤の量を減少さ
せることができる。これにより、接着剤7の加熱処理時
にボイドの発生をなくすることができ、従って、第一実
施例の場合と同様に適正なワイヤボンディングを実現す
る。
In the second embodiment, the amount of the solvent in the adhesive 7 can be reduced by evaporating a part of the solvent contained in the adhesive 7 by preheating the adhesive 7. . Thus, the generation of voids during the heat treatment of the adhesive 7 can be eliminated, and accordingly, appropriate wire bonding can be realized as in the case of the first embodiment.

尚、上記各実施例における接着剤7の加熱処理時の温
度条件は用いる接着剤7の材料種類やそれに含まれる溶
剤の含有率などに応じて適宜設定することができ、前述
した具体的数値例に限定されるものではない。
The temperature conditions during the heat treatment of the adhesive 7 in each of the above embodiments can be appropriately set according to the material type of the adhesive 7 to be used, the content of the solvent contained therein, and the like. It is not limited to.

〔発明の効果〕〔The invention's effect〕

上述したように本発明方法によれば、接着剤の加熱処
理時の温度条件を接着剤が徐々に硬化するように設定
し、又は接着剤を予備加熱して溶剤含有率を減少させる
ことにより、接着剤中のボイドの発生をなくして適正且
つ確実なワイヤボンディングを保証する。そして、ワイ
ヤボンディングの作業効率を18〜19倍にまで改善するこ
とができ、生産性を向上すると共に製品の高い信頼性が
得られる。
According to the method of the present invention as described above, the temperature conditions during the heat treatment of the adhesive are set such that the adhesive gradually cures, or by preheating the adhesive to reduce the solvent content, Eliminating the occurrence of voids in the adhesive ensures proper and reliable wire bonding. And the work efficiency of wire bonding can be improved to 18 to 19 times, thereby improving the productivity and obtaining high reliability of the product.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明方法を適用したリードフレーム型半導体
において本発明に係る接着剤の接着・硬化状態を示す部
分縦断面図、第2図及び第3図は従来のリードフレーム
型半導体の平面図及び縦断面図、第4図は従来のリード
フレーム型半導体における接着剤の接着・硬化状態を示
す部分縦断面図である。 1……リードフレーム、2……半導体チップ、3……導
電性ペースト、4……絶縁シート、5……導電線パター
ン、6……鍍金層、7……接着剤、8……ボンディング
ワイヤ。
FIG. 1 is a partial longitudinal sectional view showing a state of bonding and curing of an adhesive according to the present invention in a lead frame type semiconductor to which the method of the present invention is applied, and FIGS. 2 and 3 are plan views of a conventional lead frame type semiconductor. FIG. 4 is a partial longitudinal sectional view showing a state of bonding and curing of an adhesive in a conventional lead frame type semiconductor. DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... Semiconductor chip, 3 ... Conductive paste, 4 ... Insulating sheet, 5 ... Conductive wire pattern, 6 ... Plating layer, 7 ... Adhesive, 8 ... Bonding wire.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】リードフレームのアイランド部に半導体チ
ップを載置・固定し、該半導体チップと上記リードフレ
ームのアウターリード部とをワイヤボンディングにより
接続するようにしたリードフレーム型半導体において、
上記ワイヤボンディングを行なうための導電線パターン
が形成された絶縁シートを上記アイランド部に接着する
際に、硬化していない樹脂製接着剤に対し樹脂製接着剤
中の溶剤が該接着剤層中で気化し得ないように温度条件
を複数段階設定し、上記樹脂製接着剤をそれぞれの上記
温度条件で順次続けて加熱処理を行ない、徐々に溶剤を
蒸発させながら上記樹脂製接着剤を硬化させて上記絶縁
シートが上記アイランド部に接着するようにしたことを
特徴とする樹脂製接着剤の接着・硬化方法。
A lead frame type semiconductor in which a semiconductor chip is mounted and fixed on an island portion of a lead frame, and the semiconductor chip and an outer lead portion of the lead frame are connected by wire bonding.
When bonding the insulating sheet on which the conductive wire pattern for performing the wire bonding is formed to the island portion, a solvent in the resin adhesive is applied to the uncured resin adhesive in the adhesive layer. A plurality of temperature conditions are set so as not to be vaporized, the resin adhesive is subjected to a heat treatment sequentially at each of the above temperature conditions, and the resin adhesive is cured while gradually evaporating the solvent. A method for bonding and curing a resin adhesive, wherein the insulating sheet is bonded to the island portion.
【請求項2】請求項(1)に記載のリードフレーム型半
導体において、上記樹脂製接着剤をそれ自体が硬化しな
いような温度で予備加熱することにより、含有する溶剤
の一部を蒸発させておき、予備加熱されて含有する溶剤
の量が減少した上記樹脂製接着剤を絶縁シートおよび上
記アイランド部に介在させ、その後所定の加熱処理を施
して接着・硬化させるようにしたことを特徴とする樹脂
製接着剤の接着・硬化方法。
2. The lead frame type semiconductor according to claim 1, wherein the resin adhesive is preheated at a temperature at which the resin adhesive itself does not cure, thereby evaporating a part of the contained solvent. The pre-heated resin adhesive having a reduced amount of solvent contained is interposed between the insulating sheet and the island portion, and then subjected to a predetermined heat treatment to be adhered and cured. A method for bonding and curing resin adhesives.
JP25655090A 1990-09-26 1990-09-26 Bonding and curing method of resin adhesive Expired - Fee Related JP2793899B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25655090A JP2793899B2 (en) 1990-09-26 1990-09-26 Bonding and curing method of resin adhesive

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25655090A JP2793899B2 (en) 1990-09-26 1990-09-26 Bonding and curing method of resin adhesive

Publications (2)

Publication Number Publication Date
JPH04133460A JPH04133460A (en) 1992-05-07
JP2793899B2 true JP2793899B2 (en) 1998-09-03

Family

ID=17294200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25655090A Expired - Fee Related JP2793899B2 (en) 1990-09-26 1990-09-26 Bonding and curing method of resin adhesive

Country Status (1)

Country Link
JP (1) JP2793899B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2809945B2 (en) * 1992-11-05 1998-10-15 株式会社東芝 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622628A (en) * 1985-06-28 1987-01-08 Toshiba Corp Semiconductor device
JPS6436034A (en) * 1987-07-31 1989-02-07 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH04133460A (en) 1992-05-07

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