JP2978862B2 - LOC semiconductor device and method of manufacturing the same - Google Patents
LOC semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2978862B2 JP2978862B2 JP29694697A JP29694697A JP2978862B2 JP 2978862 B2 JP2978862 B2 JP 2978862B2 JP 29694697 A JP29694697 A JP 29694697A JP 29694697 A JP29694697 A JP 29694697A JP 2978862 B2 JP2978862 B2 JP 2978862B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating member
- adhesive
- semiconductor device
- loc
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Compositions Of Macromolecular Compounds (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＬＯＣ（ Lead On
Chip ）型構造を有する半導体装置及びその製造方法に
関する。The present invention relates to a LOC (Lead On)
And a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来のＬＯＣ型構造を有する半導体装置
においては、図２に示すように、リードフレームのイン
ナリード２に予め熱可塑性または熱硬化性接着剤（図で
は熱硬化性接着剤として示してある。）６を塗布し硬化
させてポリイミド等の絶縁テープ４を貼り付けてあり、
絶縁テープの他方の側に熱可塑性または熱硬化性接着剤
（図では熱硬化性接着剤として示してある。）６により
チップ３を配置する。その後、固着するために熱処理を
行い熱可塑性または熱硬化性接着剤６を硬化させてい
た。2. Description of the Related Art In a conventional semiconductor device having a LOC type structure, as shown in FIG. 2, a thermoplastic or thermosetting adhesive (shown as a thermosetting adhesive in the figure) is previously attached to an inner lead 2 of a lead frame. 6) is applied and cured, and an insulating tape 4 such as polyimide is attached.
The chip 3 is arranged on the other side of the insulating tape with a thermoplastic or thermosetting adhesive (shown as a thermosetting adhesive in the figure) 6. After that, a heat treatment was performed to fix the thermoplastic or thermosetting adhesive 6.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ＬＯＣ型構造を有する半導体装置では、ワイヤボンディ
ング時にＥオープン（ボンディングワイヤがインナリー
ドと接続できないこと）が発生する場合があった。その
理由は、チップ配置後硬化のために熱処理がされると、
インナリード側の接着剤が軟化しインナリード加工歪み
が解放される為インナリードが変形するからである。However, in the semiconductor device having the above-mentioned LOC type structure, E-opening (the bonding wire cannot be connected to the inner lead) may occur at the time of wire bonding. The reason is that when heat treatment is performed for curing after chip placement,
This is because the inner lead is deformed because the adhesive on the inner lead side is softened and the inner lead processing distortion is released.
【０００４】発明の目的は、ＬＯＣ構造リードフレーム
にチップ搭載後熱処理をする半導体装置のボンディング
時のリード側オープン不良を防止することにある。An object of the present invention is to prevent a lead-side open defect at the time of bonding of a semiconductor device which is subjected to a heat treatment after mounting a chip on a LOC structure lead frame.
【０００５】[0005]
【課題を解決するための手段】本発明のＬＯＣ型半導体
装置は、半導体チップ上に絶縁部材を介してリードフレ
ームのインナーリードが配置され、該半導体チップと該
絶縁部材、該絶縁部材と該インナーリードがそれぞれ接
着剤により貼り付けられているＬＯＣ型半導体装置にお
いて、前記絶縁部材と前記インナーリードとを貼り付け
る接着剤として、熱硬化性あるいは熱可塑性の接着剤を
用い、かつ前記半導体チップと前記絶縁部材とを貼り付
ける接着剤として、紫外線硬化性接着剤を用いたことを
特徴とする。According to the LOC type semiconductor device of the present invention, inner leads of a lead frame are arranged on a semiconductor chip via an insulating member, and the semiconductor chip, the insulating member, the insulating member and the inner member are provided. In the LOC semiconductor device in which the leads are respectively attached by an adhesive, the insulating member and the inner lead are attached.
Thermosetting or thermoplastic adhesives
Used, and as an adhesive paste and the insulating member and the semiconductor chip, characterized by using a UV curable adhesive.
【０００６】また本発明のＬＯＣ型半導体装置の製造方
法は、リードフレームのインナーリード側に熱硬化性あ
るいは熱可塑性の接着剤を介して絶縁部材を貼り付け、
該絶縁部材と該絶縁部材上の紫外線硬化性接着剤を介し
て半導体チップとを接合し紫外線にて該紫外線硬化性接
着剤を硬化させることを特徴とする。[0006] Production method of LOC type semiconductor device of the present invention may also thermosetting Oh the inner over leads of the lead frame
Or paste the insulating member via a thermoplastic adhesive,
Via the insulating member and an ultraviolet-curable adhesive on the insulating member
And bonding the semiconductor chip to the semiconductor chip and curing the ultraviolet-curable adhesive with ultraviolet light.
【０００７】本発明は、ＬＯＣ構造リードフレームでチ
ップを固着する側の絶縁テープ等の絶縁部材の面に紫外
線（以下ＵＶという）硬化性接着剤を使用するものであ
り、チップ搭載時に熱処理はせずＵＶ照射により固着を
行なう。According to the present invention, an ultraviolet ray (hereinafter referred to as UV) curable adhesive is used on the surface of an insulating member such as an insulating tape on the side to which a chip is fixed with a LOC structure lead frame. First, fix by UV irradiation.
【０００８】本発明においては、チップ搭載後ＵＶ照射
にて半導体チップと絶縁部材とを固着するので、チップ
搭載後熱処理を必要とせず、インナリードと絶縁部材と
を貼り付けている接着剤が軟化しない。よってインテリ
ードが変形することなくボンディング時のＥオープンを
防止できる。In the present invention, since the semiconductor chip and the insulating member are fixed by UV irradiation after mounting the chip, no heat treatment is required after mounting the chip, and the adhesive bonding the inner lead and the insulating member is softened. do not do. Therefore, E-opening during bonding can be prevented without deformation of the interlead.
【０００９】インナーリードと絶縁部材とを貼り付ける
接着剤としては、従来と同様に熱可塑性または熱硬化性
接着剤を用いる。 [0009] As an adhesive paste inner over leads and the insulating member, as in the prior art using a thermoplastic or thermosetting adhesive.
【００１０】[0010]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。図１は本発明のＬＯ
Ｃ型半導体装置の一実施形態を示す断面図である。図１
に示すように、本発明の好適な実施形態は、ＬＯＣ用リ
ードフレームのインナーリード２に接合しているポリイ
ミドテープ等の絶縁テープ（絶縁部材）４のインナリー
ド固定側の接着剤は熱硬化性樹脂６を使用し、絶縁テー
プ４の反対側のチップを接着する側の接着剤はＵＶ硬化
性樹脂５を使用する。また、チップ搭載後はＵＶを照射
し固着する。チップ搭載後接着剤には熱が加わらないた
めインナリードは接着剤に固定され、インナリードが変
形することはない。Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the LO of the present invention.
FIG. 3 is a cross-sectional view illustrating one embodiment of a C-type semiconductor device. FIG.
As shown in FIG. 1, the adhesive of the insulating tape (insulating member) 4 such as a polyimide tape bonded to the inner lead 2 of the LOC lead frame is fixed on the inner lead fixing side by a thermosetting resin. The resin 6 is used, and the UV-curable resin 5 is used as the adhesive on the side to which the chip opposite to the insulating tape 4 is bonded. After mounting the chip, it is fixed by irradiating UV. After the chip is mounted, no heat is applied to the adhesive, so that the inner leads are fixed to the adhesive and the inner leads are not deformed.
【００１１】次に上記ＬＯＣ型半導体装置の製造方法に
ついて説明する。Next, a method of manufacturing the LOC semiconductor device will be described.
【００１２】まず、ＬＯＣ用リードフレームのインナー
リード２に、予め両面に接着剤を塗布したポリイミドテ
ープ４を貼り付けておく、その時リードフレームのイン
ナーリード２側に熱硬化性接着剤６の方を貼り付ける。First, a polyimide tape 4 coated with an adhesive on both sides in advance is attached to the inner lead 2 of the LOC lead frame. At this time, the thermosetting adhesive 6 is applied to the inner lead 2 side of the lead frame. paste.
【００１３】半導体チップ３はポリイミドテープ４のＵ
Ｖ硬化性接着剤５の方と接合させる。その後、ＵＶ硬化
性接着剤５をＵＶ照射にてチップとリードフレームを固
定させる。このとき、熱硬化性接着剤の様に熱処理時の
不純物がリード表面に付着すること及びインナリード変
形が発生することがないため、ボンディングは良好にで
きる。The semiconductor chip 3 is made of U of the polyimide tape 4
It is bonded to the V-curable adhesive 5. Thereafter, the chip and the lead frame are fixed by UV irradiation with the UV-curable adhesive 5. At this time, bonding can be performed well because impurities such as a thermosetting adhesive during heat treatment do not adhere to the lead surface and inner lead deformation does not occur.
【００１４】[0014]
【発明の効果】本発明によれば、インナリードが変形せ
ず、ボンディング時のＥオープン不良防止が可能とな
る。その理由は、チップと接着する接着剤にＵＶ硬化性
樹脂を使用するために熱処理によるインナリード変形を
防止できるためである。According to the present invention, the inner lead is not deformed, and the E-open defect at the time of bonding can be prevented. The reason is that the inner lead deformation due to heat treatment can be prevented because a UV-curable resin is used as an adhesive for bonding to the chip.
【図１】本発明のＬＯＣ型半導体装置の一実施形態を示
す断面図である。FIG. 1 is a sectional view showing one embodiment of a LOC semiconductor device of the present invention.
【図２】従来のＬＯＣ型半導体装置の断面図である。FIG. 2 is a cross-sectional view of a conventional LOC semiconductor device.
１ ボンディングワイヤ ２ インナリード ３ チップ ４ ポリイミド ５ ＵＶ硬化性接着剤 ６ 熱硬化性接着剤 DESCRIPTION OF SYMBOLS 1 Bonding wire 2 Inner lead 3 Chip 4 Polyimide 5 UV curable adhesive 6 Thermosetting adhesive
Claims (4)
ドフレームのインナーリードが配置され、該半導体チッ
プと該絶縁部材、該絶縁部材と該インナーリードがそれ
ぞれ接着剤により貼り付けられているＬＯＣ型半導体装
置において、前記絶縁部材と前記インナーリードとを貼り付ける接着
剤として、熱硬化性あるいは熱可塑性の接着剤を用い、
かつ前記 半導体チップと前記絶縁部材とを貼り付ける接
着剤として、紫外線硬化性接着剤を用いたことを特徴と
するＬＯＣ型半導体装置。1. An LOC type wherein an inner lead of a lead frame is disposed on a semiconductor chip via an insulating member, and the semiconductor chip and the insulating member, and the insulating member and the inner lead are respectively adhered by an adhesive. In a semiconductor device, an adhesive for adhering the insulating member and the inner lead
Using a thermosetting or thermoplastic adhesive,
And as an adhesive paste and the insulating member and the semiconductor chip, LOC type semiconductor device characterized by using a UV curable adhesive.
ることを特徴とする請求項１に記載のＬＯＣ型半導体装
置。 2. The LOC semiconductor device according to claim 1 , wherein said insulating member is a polyimide tape.
硬化性あるいは熱可塑性の接着剤を介して絶縁部材を貼
り付け、該絶縁部材と該絶縁部材上の紫外線硬化性接着
剤を介して半導体チップとを接合し紫外線にて該紫外線
硬化性接着剤を硬化させることを特徴とするＬＯＣ型半
導体装置の製造方法。 3. A heat inner over leads of the lead frame
An insulating member is attached via a curable or thermoplastic adhesive, and the insulating member and an ultraviolet-curable adhesive on the insulating member
A method for manufacturing a LOC type semiconductor device, comprising bonding a semiconductor chip via an agent and curing the ultraviolet curable adhesive with ultraviolet rays.
ことを特徴とする請求項３に記載のＬＯＣ型半導体装置
の製造方法。 4. The process for producing LOC type semiconductor device according to claim 3, wherein said insulating member is a polyimide tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29694697A JP2978862B2 (en) | 1997-10-29 | 1997-10-29 | LOC semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29694697A JP2978862B2 (en) | 1997-10-29 | 1997-10-29 | LOC semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135704A JPH11135704A (en) | 1999-05-21 |
| JP2978862B2 true JP2978862B2 (en) | 1999-11-15 |
Family
ID=17840236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29694697A Expired - Fee Related JP2978862B2 (en) | 1997-10-29 | 1997-10-29 | LOC semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2978862B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1094518A1 (en) * | 1999-09-30 | 2001-04-25 | Ming-Tung Shen | Semiconductor device comprising a lead frame and method for fabricating the same |
| JP2003037344A (en) * | 2001-07-25 | 2003-02-07 | Sanyo Electric Co Ltd | Circuit device and its manufacturing method |
| KR100652517B1 (en) | 2004-03-23 | 2006-12-01 | 삼성전자주식회사 | semiconductor package having leads directly attached to chip, manufacturing method and apparatus thereof |
-
1997
- 1997-10-29 JP JP29694697A patent/JP2978862B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11135704A (en) | 1999-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2978862B2 (en) | LOC semiconductor device and method of manufacturing the same | |
| JP2806348B2 (en) | Semiconductor device mounting structure and method of manufacturing the same | |
| JPH1050918A (en) | Lead-on-chip semiconductor package having discontinuous adhesive layer formed by applying liq. adhesive on lead frame and manufacture thereof | |
| JPS59231825A (en) | Semiconductor device | |
| JP3381563B2 (en) | Method for manufacturing semiconductor device | |
| JPS62281360A (en) | Manufacture of semiconductor device | |
| JPH0794539A (en) | Semiconductor device | |
| KR950010013Y1 (en) | Lead on chip package | |
| JPH0595010A (en) | Semiconductor device | |
| JP3216314B2 (en) | Semiconductor device, method of manufacturing the same, and semiconductor device manufacturing apparatus | |
| JPH11289040A (en) | Lead frame and semiconductor device using the same | |
| JPH10340914A (en) | Manufacture of semiconductor device | |
| KR20020089492A (en) | Pre-application of die attach material to wafer back | |
| JPH0366152A (en) | Semiconductor integrated circuit module | |
| JP3422099B2 (en) | Adhesive and method for manufacturing lead frame for semiconductor device using the same | |
| JP2793899B2 (en) | Bonding and curing method of resin adhesive | |
| JP3235456B2 (en) | Chip mounting method | |
| JPH06252194A (en) | Semiconductor device | |
| JP3525965B2 (en) | Lead frame, method of manufacturing the same, and semiconductor element package using the same | |
| JPH11135539A (en) | Semiconductor device and its manufacture | |
| JPH07283265A (en) | Heater device for bonding | |
| JPH0621111A (en) | Semiconductor device and manufacture thereof | |
| JPH09139394A (en) | Semiconductor device | |
| JPH10321749A (en) | Sealing method of package for solid-state image-pickup device | |
| JPH0945845A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |