JP2903697B2 - Semiconductor device manufacturing method and semiconductor device manufacturing apparatus - Google Patents
Semiconductor device manufacturing method and semiconductor device manufacturing apparatusInfo
- Publication number
- JP2903697B2 JP2903697B2 JP2300885A JP30088590A JP2903697B2 JP 2903697 B2 JP2903697 B2 JP 2903697B2 JP 2300885 A JP2300885 A JP 2300885A JP 30088590 A JP30088590 A JP 30088590A JP 2903697 B2 JP2903697 B2 JP 2903697B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- manufacturing
- semiconductor
- jig
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法及び半導体装置の製
造装置に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device.
従来、半導体装置の製造方法に関しては、特開昭61−
97143号公報に記載され、第２図に示されるような方法
が知られていた。第２図において、６の半導体素子の能
動面上に形成された電極４上に形成された金属突起３
は、それに相対するように１の基板上に形成された配線
パターン２との間に、電気的接続を発現させる時に、10
の加圧用治具によって加圧を行い、絶縁樹脂５を金属突
起３と配線パターン２との間から排除し、絶縁樹脂５の
硬化メカニズムに従った方法のエネルギーを加え、半導
体素子と基板の電気的接続を保ったまま、機械的にもこ
れらを保持させる。Conventionally, a method of manufacturing a semiconductor device is disclosed in
No. 97143, a method as shown in FIG. 2 has been known. In FIG. 2, a metal projection 3 formed on an electrode 4 formed on an active surface of a semiconductor device 6
When electrical connection is developed between the wiring pattern 2 formed on one substrate so as to face it,
Pressure is applied by the pressing jig described above, the insulating resin 5 is removed from between the metal protrusion 3 and the wiring pattern 2, and energy is applied by a method according to a curing mechanism of the insulating resin 5 to apply electric power to the semiconductor element and the substrate. These are also held mechanically while maintaining the proper connection.
しかし、従来の方法では一つの半導体素子の接続を完
了させるために、一つの加圧用治具を用いるため、複数
個の半導体素子を接続するために、複数個の加圧用治具
を同時に用いるか、１個づつ複数回の加圧操作によって
接続を行わねばならず、接続用装置の構造が複雑になっ
たり、半導体装置の生産効率が低下するという問題点を
有していた。However, in the conventional method, one pressing jig is used to complete the connection of one semiconductor element, and therefore, a plurality of pressing jigs are simultaneously used to connect a plurality of semiconductor elements. The connection must be performed by a plurality of pressurizing operations one by one, and the structure of the connection device becomes complicated, and the production efficiency of the semiconductor device is reduced.
そこで、本発明の半導体装置の製造方法では、複数の
半導体素子と基板の接続を行う時でも、簡略な接続装置
で、かつ半導体装置の生産効率が低下しないような製造
方法を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device of the present invention, in which a simple connection device is used and the production efficiency of a semiconductor device is not reduced even when a plurality of semiconductor elements are connected to a substrate. And
上記課題を解決するため、本発明の半導体装置の製造
方法は、基板上に複数の半導体素子を圧着用治具によっ
て加圧とともに加熱して圧着する半導体装置の製造方法
であって、 前記複数の半導体素子を前記圧着治具によって一括圧
着することを特徴とする。In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are heated and pressed together with a pressure by a pressing jig on a substrate; The semiconductor device is characterized in that the semiconductor elements are collectively crimped by the crimping jig.
また、本発明の半導体装置の製造装置は、基板上に複
数の半導体素子を圧着用治具によって加圧とともに加熱
して圧着する半導体装置の製造装置であって、 前記複数の半導体素子を前記圧着治具によって一括圧
着することを特徴とする。Further, the apparatus for manufacturing a semiconductor device of the present invention is an apparatus for manufacturing a semiconductor device, in which a plurality of semiconductor elements are pressed and heated by a pressing jig and pressed on a substrate, and the plurality of semiconductor elements are pressed by the pressing. It is characterized in that it is collectively pressed by a jig.
また、本発明の半導体装置の製造方法は、基板上に複
数の半導体素子を圧着用治具によって加圧とともに加熱
して圧着する半導体装置の製造方法であって、 前記圧着用治具と前記複数の半導体素子との間に各々
の半導体素子の厚さバラツキを吸収するシートを載置し
て、前記複数の半導体素子を前記圧着治具により一括圧
着することを特徴とする。Further, the method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are pressed and heated and pressed by a pressing jig on a substrate, the method comprising: A sheet for absorbing the thickness variation of each semiconductor element is placed between the semiconductor elements and the plurality of semiconductor elements are collectively crimped by the crimping jig.
本発明では、半導体素子と基板とを加圧する際に、複
数個、同時に加圧する方法としたので、１個づつ半導体
素子と基板を加圧する方法と比較して、同じ個数の半導
体素子を加圧する時間が短くて済み、生産性が向上す
る。According to the present invention, when the semiconductor element and the substrate are pressed, a plurality of the semiconductor elements are pressed at the same time. Therefore, compared with the method of pressing the semiconductor element and the substrate one by one, the same number of the semiconductor elements are pressed. Time is short, and productivity is improved.
以下に、本発明の実施例を図を用いて、詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は、本発明による半導体装置の製造方法を示し
た断面図である。第１図において、１は基板であり、少
なくとも表面が絶縁物で形成されており、ガラス、セラ
ミクス、ホウロウ、ガラスエポキシ等であることが多
い。その上に、２の配線パターンが形成されている。配
線パターンは、金、銀、クロム、ニッケル等の金属か、
ITO等の金属酸化物を蒸着、スパッタ、メッキ等で形成
し、フォト〜エッチング工程で目的のパターンにパター
ニングされることが多い。６は半導体素子であり、能動
面は基板側と対向して載置されている。半導体素子６の
能動素子形成面上には、Ti−Pd、Cr等で蒸着、スパッタ
等の方法を用いて電極４が形成され、その上にAu、ハン
ダ等の金属突起３が電気メッキ、リフロー等で形成され
ている。１の基板上に形成されている配線パターン２
は、３の金属突起に１部が相対するように形成されてお
り、３の金属突起により、半導体素子６上の電極４と、
基板１上の配線パターン２とは電気的な接続が得られて
いる。５は絶縁樹脂であって、加熱あるいは光等の外部
エネルギーによって硬化あるいは接着力を発現するメカ
ニズムを持っており、半導体素子６上の金属突起３と基
板１上の配線パターン２を半導体素子６の上から８の一
括圧着治具で加圧することによって、間に存在する絶縁
樹脂５を押しのけ、電気的な導通がはかられた時に、前
述の外部エネルギーを加え、絶縁樹脂５を硬化又は接着
させることで、電気的接続と、機械的接続を同時に保持
させ続ける。この時、第１図中に示すように、複数個の
半導体素子を、同時に、８の一括圧着用治具を用いて加
圧を行う。こうすることで、同時に複数個の半導体素子
の導通、接続保持をはかるのである。さらに、半導体素
子６の厚さのバラツキ、３の金属突起の高さのバラツ
キ、基板１や、一括圧着治具８の平坦度のバラツキを吸
収するために、半導体素子６と、一括圧着用治具８の間
にテフロンシート７を載置しても良い。テフロンシート
に限らず、ポリイミドのシート、シリコンゴムシートで
もかまわない。一括圧着用治具は、平坦性にすぐれるよ
うに、ステンレス、CBN、SiN等の金属や、セラミクスで
形成されることが多い。５の絶縁樹脂の硬化又は接着に
熱エネルギーを要する場合等は、一括圧着用治具の中に
ヒーターのような発熱源を入れ、治具を加圧と同時に加
熱用として用いても良い。前述の接着によって電気的・
機械的保持を行う方式でなく、例えば、金属突起がハン
ダ等で形成され、配線パターンがニッケル等で形成さ
れ、金属共晶で電気的・機械的保持を行う場合でも、手
順は前述と同様の方式でかまわない。また、絶縁樹脂５
中に、導電性を有する物質を存在させ、さらに接続信頼
性を向上させる場合や、導電性を有する物質を金属突起
のかわりに存在させる場合も手順は同様である。FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 denotes a substrate, at least a surface of which is formed of an insulator, and is often made of glass, ceramics, enamel, glass epoxy, or the like. On top of that, two wiring patterns are formed. The wiring pattern is a metal such as gold, silver, chrome, nickel, etc.
In many cases, a metal oxide such as ITO is formed by vapor deposition, sputtering, plating, or the like, and is patterned into a target pattern in a photo-etching process. Reference numeral 6 denotes a semiconductor element, the active surface of which is placed facing the substrate side. An electrode 4 is formed on the active element forming surface of the semiconductor element 6 by using a method such as vapor deposition or sputtering of Ti-Pd, Cr, or the like, and a metal projection 3 such as Au or solder is electroplated or reflowed thereon. And so on. Wiring pattern 2 formed on one substrate
Are formed so that a part thereof is opposed to the three metal projections.
Electrical connection with the wiring pattern 2 on the substrate 1 is obtained. Numeral 5 denotes an insulating resin, which has a mechanism of hardening or developing an adhesive force by external energy such as heating or light, and connects the metal protrusion 3 on the semiconductor element 6 and the wiring pattern 2 on the substrate 1 to the semiconductor element 6. By pressurizing with the collective pressure bonding jig 8 from the top, the existing insulating resin 5 is pushed away, and when electric conduction is established, the above-described external energy is applied to cure or adhere the insulating resin 5. As a result, the electrical connection and the mechanical connection are simultaneously maintained. At this time, as shown in FIG. 1, a plurality of semiconductor elements are simultaneously pressed by using eight jigs for collective pressure bonding. By doing so, conduction and connection holding of a plurality of semiconductor elements are simultaneously performed. Further, in order to absorb the variation in the thickness of the semiconductor element 6, the variation in the height of the three metal projections, and the variation in the flatness of the substrate 1 and the package crimping jig 8, the semiconductor device 6 and the package crimping jig are absorbed. The Teflon sheet 7 may be placed between the tools 8. Not limited to the Teflon sheet, a polyimide sheet or a silicone rubber sheet may be used. The jig for collective pressure bonding is often formed of a metal such as stainless steel, CBN, SiN, or ceramics so as to have excellent flatness. In the case where thermal energy is required for curing or bonding the insulating resin of No. 5, a heat source such as a heater may be placed in a jig for collective pressure bonding, and the jig may be used for heating simultaneously with pressurization. The electric and
Instead of the method of performing mechanical holding, for example, even when the metal projection is formed of solder or the like, the wiring pattern is formed of nickel or the like, and the electrical and mechanical holding is performed by metal eutectic, the procedure is the same as described above. It does not matter in the method. Also, the insulating resin 5
The procedure is the same in the case where a conductive material is present therein to further improve the connection reliability, or in the case where a conductive material is present instead of the metal protrusion.
また、一括圧着用治具を取付ける装置は、従来の加圧
用治具を複数取付けて生産効率を上げる必要が無いた
め、簡略化された構造で済ますこともできる。In addition, the apparatus for mounting the jig for collective crimping does not have to increase the production efficiency by mounting a plurality of conventional jigs for pressing, so that a simplified structure can be achieved.
以上、説明したように、本発明の半導体装置の製造方
法では、複数個の半導体素子を基板に同時に加圧する方
法としたので、加圧に要する製造装置が簡略化されるた
め、製造装置に対する投資が少くて済み、また、装置の
保守も簡略化されるという効果を有する。さらに、複数
個の半導体素子の接続を完了するのが少い回数の加圧で
済むので、特に半導体素子の個数が多い半導体装置で
は、生産効率が著しく向上するという効果をも有する。As described above, in the method of manufacturing a semiconductor device according to the present invention, a method in which a plurality of semiconductor elements are simultaneously pressed onto a substrate is employed. And the maintenance of the apparatus is simplified. Further, since the connection of a plurality of semiconductor elements can be completed with a small number of pressurizations, there is also an effect that the production efficiency is remarkably improved particularly in a semiconductor device having a large number of semiconductor elements.
第１図は、本発明による半導体装置の製造方法を示す断
面図であり、第２図は従来の半導体装置の製造方法を示
す断面図である。 １……基板 ２……配線パターン ３……金属突起 ４……電極 ５……絶縁樹脂 ６……半導体素子 ７……テフロンシート ８……一括圧着用治具 10……加圧用治具FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a method for manufacturing a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Wiring pattern 3 ... Metal projection 4 ... Electrode 5 ... Insulating resin 6 ... Semiconductor element 7 ... Teflon sheet 8 ... Jig for pressure bonding 10 ... Jig for pressing
Claims (3)
よって加圧とともに加熱して圧着する半導体装置の製造
方法であって、 前記複数の半導体素子を前記圧着治具によって一括圧着
することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are pressurized and heated by a pressing jig on a substrate by pressing and heating, wherein the plurality of semiconductor elements are collectively pressed by the pressing jig. A method for manufacturing a semiconductor device, comprising:
よって加圧とともに加熱して圧着する半導体装置の製造
装置であって、 前記複数の半導体素子を前記圧着治具によって一括圧着
することを特徴とする半導体装置の製造装置。2. An apparatus for manufacturing a semiconductor device, wherein a plurality of semiconductor elements are heated and pressed together with pressure by a pressing jig on a substrate, wherein the plurality of semiconductor elements are collectively pressed by the pressing jig. An apparatus for manufacturing a semiconductor device, comprising:
よって加圧とともに加熱して圧着する半導体装置の製造
方法であって、 前記圧着用治具と前記複数の半導体素子との間に各々の
半導体素子の厚さバラツキを吸収するシートを載置し
て、前記複数の半導体素子を前記圧着治具により一括圧
着することを特徴とする半導体装置の製造方法。3. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are pressed and heated on a substrate by pressing with a crimping jig, and wherein a plurality of semiconductor elements are provided between the crimping jig and the plurality of semiconductor elements. A method of manufacturing a semiconductor device, comprising: mounting a sheet that absorbs variations in thickness of each semiconductor element, and pressing the plurality of semiconductor elements at once by the pressing jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2300885A JP2903697B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2300885A JP2903697B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171949A JPH04171949A (en) | 1992-06-19 |
| JP2903697B2 true JP2903697B2 (en) | 1999-06-07 |
Family
ID=17890294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2300885A Expired - Fee Related JP2903697B2 (en) | 1990-11-06 | 1990-11-06 | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903697B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011228620A (en) * | 2010-03-31 | 2011-11-10 | Sumitomo Bakelite Co Ltd | Method of manufacturing electronic device and manufacturing apparatus of the same |
| KR101853151B1 (en) | 2010-10-07 | 2018-04-27 | 데쿠세리아루즈 가부시키가이샤 | Buffering film for multichip mounting |
| CN111261531A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming integrated circuit package |
| US11121089B2 (en) | 2018-11-30 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60235821D1 (en) * | 2001-09-12 | 2010-05-12 | Nikkiso Co Ltd | METHOD AND PRESS FOR ASSEMBLING A CIRCUIT |
| JP2007281264A (en) * | 2006-04-10 | 2007-10-25 | Elpida Memory Inc | Method of manufacturing semiconductor device |
| CN102859674A (en) * | 2010-04-23 | 2013-01-02 | 住友电木株式会社 | Device and method for producing electronic device, and pair of compressed members thereof |
-
1990
- 1990-11-06 JP JP2300885A patent/JP2903697B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011228620A (en) * | 2010-03-31 | 2011-11-10 | Sumitomo Bakelite Co Ltd | Method of manufacturing electronic device and manufacturing apparatus of the same |
| KR101853151B1 (en) | 2010-10-07 | 2018-04-27 | 데쿠세리아루즈 가부시키가이샤 | Buffering film for multichip mounting |
| CN111261531A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming integrated circuit package |
| US11121089B2 (en) | 2018-11-30 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
| CN111261531B (en) * | 2018-11-30 | 2021-12-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming integrated circuit package |
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| Publication number | Publication date |
|---|---|
| JPH04171949A (en) | 1992-06-19 |
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