JPH0519306B2 - - Google Patents

Info

Publication number
JPH0519306B2
JPH0519306B2 JP63024219A JP2421988A JPH0519306B2 JP H0519306 B2 JPH0519306 B2 JP H0519306B2 JP 63024219 A JP63024219 A JP 63024219A JP 2421988 A JP2421988 A JP 2421988A JP H0519306 B2 JPH0519306 B2 JP H0519306B2
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
wiring board
conductor wiring
pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63024219A
Other languages
Japanese (ja)
Other versions
JPH01199440A (en
Inventor
Tomohiko Suzuki
Izumi Okamoto
Shinsuke Nakamoto
Masayoshi Mihata
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63024219A priority Critical patent/JPH01199440A/en
Publication of JPH01199440A publication Critical patent/JPH01199440A/en
Publication of JPH0519306B2 publication Critical patent/JPH0519306B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H01L2224/75102—Vacuum chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/8309—Vacuum
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、各種電子機器に利用される半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device used in various electronic devices.

従来の技術 従来の技術を第２図ａ〜ｃとともに説明する。
まず第２図ａに示すように、セラミツク、ガラ
ス、ガラスエポキシ等よりなる配線基板１の導体
配線２を有する面に絶縁性の樹脂５を塗布する。
導体配線２はCr−Au，Al，Cu，ito等であり、
樹脂５は熱硬化型又は紫外線硬化型のエポキシ、
シリコーン、アクリル等である。次に第２図ｂに
示すように半導体素子３の電極４と導体配線２と
を一致させ半導体素子３に加圧し、配線基板１に
押し当てる。電極４はAl，Au，Cu等である。こ
の時、導体配線２上の樹脂５は周囲に押し出さ
れ、半導体素子３の電極４と導体配線２は電気的
に接触する。次に半導体素子３を加圧した状態で
上部より紫外線８を照射することにより、半導体
素子３周縁の樹脂５を硬化させ仮固定する。更に
第２図ｃに示すように半導体素子３をFe，Al等
よりなる加圧治具９にて加圧しながら加熱するこ
とにより、樹脂５全体を硬化させ、この時半導体
素子３の電極４の導体配線２は樹脂５の接着力に
より電気的接続がなされ、同時に半導体素子３を
配線基板１に固着することができる。Prior Art The conventional technology will be explained with reference to FIGS. 2a to 2c.
First, as shown in FIG. 2a, an insulating resin 5 is applied to a surface of a wiring board 1 made of ceramic, glass, glass epoxy, etc., on which conductor wiring 2 is provided.
The conductor wiring 2 is made of Cr-Au, Al, Cu, ito, etc.
Resin 5 is thermosetting or ultraviolet curing epoxy,
Silicone, acrylic, etc. Next, as shown in FIG. 2b, the electrodes 4 of the semiconductor element 3 and the conductor wiring 2 are brought into alignment, and pressure is applied to the semiconductor element 3 to press it against the wiring board 1. The electrode 4 is made of Al, Au, Cu, etc. At this time, the resin 5 on the conductor wiring 2 is pushed out to the periphery, and the electrode 4 of the semiconductor element 3 and the conductor wiring 2 are brought into electrical contact. Next, by irradiating the semiconductor element 3 with ultraviolet rays 8 from above under pressure, the resin 5 around the semiconductor element 3 is cured and temporarily fixed. Furthermore, as shown in FIG. 2c, the entire resin 5 is cured by heating the semiconductor element 3 while pressurizing it with a pressure jig 9 made of Fe, Al, etc., and at this time, the entire resin 5 is cured. The conductor wiring 2 is electrically connected by the adhesive force of the resin 5, and at the same time, the semiconductor element 3 can be fixed to the wiring board 1.

発明が解決しようとする課題 以上のように従来の技術では、半導体素子３の
電極４を配線基板１の導体配線２に直接接触させ
る方法であるため、多端子、狭ピツチの半導体素
子３のパツケージングに有利な方法であるが半導
体素子３を加圧しながら熱硬化する時において、
高温時にいつたん樹脂５の接着力が低下するた
め、配線基板１上に仮固定された複数個の半導体
素子３全てに対し均等に加圧し、電気的に接触し
た状態を保持する必要がある。そのため加圧を治
具化すると、全ての半導体素子３をひずみ等が生
じないようにするため、治具９は第２図ｃに示す
ごとく大がかりなものとなる。よつて熱容量が大
きくなることより、熱硬化時での昇温時間及び冷
却時間も長くなり生産性が悪くなる。Problems to be Solved by the Invention As described above, in the conventional technology, the electrodes 4 of the semiconductor element 3 are brought into direct contact with the conductor wiring 2 of the wiring board 1, so the package of the multi-terminal, narrow-pitch semiconductor element 3 is When thermally curing the semiconductor element 3 while applying pressure, it is an advantageous method for
Since the adhesive force of the resin 5 gradually decreases at high temperatures, it is necessary to apply pressure evenly to all of the plurality of semiconductor elements 3 temporarily fixed on the wiring board 1 to maintain electrical contact. Therefore, if a jig is used for pressurizing, the jig 9 will be large-scale as shown in FIG. 2c in order to prevent all semiconductor elements 3 from being strained. As the heat capacity increases, the heating time and cooling time during thermosetting also become longer, resulting in poor productivity.

課題を解決するための手段 上記課題を解決するために本発明は、半導体素
子固着用の樹脂を熱硬化する際、真空包装装置を
用いることにより、工法を簡易化し複数個の半導
体素子全てを同時に均一に加圧する方法としたも
のである。Means for Solving the Problems In order to solve the above problems, the present invention simplifies the method by using a vacuum packaging device when thermosetting the resin for fixing semiconductor elements, and all the semiconductor elements can be packaged at the same time. This method applies pressure evenly.

作 用 上記方法により真空包装状態で作用する大気圧
の力で半導体素子を加圧することができ量産性に
優れ、半導体素子にひずみを与えることがなくな
る。Effect: The above method allows the semiconductor element to be pressurized by the force of atmospheric pressure acting in a vacuum packaged state, resulting in excellent mass productivity and no distortion being imparted to the semiconductor element.

実施例 以下、本発明の一実施例を第１図ａ〜ｃととも
に説明する。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1a to 1c.

まず第１図ａに示すように、セラミツク、ガラ
ス、エポキシ等よりなる配線基板１１の後に半導
体素子１３を固着する部分に（導体配線１２上を
含んで）エポキシ、シリコーン、アクリル等より
なる絶縁性樹脂１５を塗布する。導体配線１２は
Cr−Au，Al，ito等よりなる。次に第１図ｂに示
すように、半導体素子１３の突起状の電極１４と
導体配線１２を一致させ半導体素子１３を配線基
板１１に加圧ツール１６により加圧する。電極１
４はAl，Au，Cu等である。この時、導体配線１
２上の樹脂１５は周囲に押し出され、上部より紫
外線１８を照射することによつて半導体素子１３
の周縁部の樹脂１５を硬化させ仮固定する。上記
の方法で複数個の半導体素子１３が仮固定された
配線基板１１を第１図ｃに示すように、ナイロ
ン、ポリプロピレン等からなる真空袋１７に入
れ、真空包装し、複数個の半導体素子１３全てに
大気圧による均等な圧力を加える。この状態のま
ま加熱することによつて樹脂１５全体を硬化さ
せ、その接着力により半導体素子１３の電極１４
と導体配線１２の電気的接続と半導体素子１３の
機械的保持が完了される。 First, as shown in FIG. 1A, an insulating film made of epoxy, silicone, acrylic, etc. is applied to the part (including the top of the conductor wiring 12) to which the semiconductor element 13 is fixed after the wiring board 11 made of ceramic, glass, epoxy, etc. Apply resin 15. The conductor wiring 12
Made of Cr-Au, Al, ito, etc. Next, as shown in FIG. 1B, the protruding electrodes 14 of the semiconductor element 13 and the conductor wiring 12 are brought into alignment, and the semiconductor element 13 is pressed against the wiring board 11 by the pressing tool 16. Electrode 1
4 is Al, Au, Cu, etc. At this time, conductor wiring 1
The resin 15 on the semiconductor element 13 is pushed out to the surrounding area, and the semiconductor element 13 is irradiated with ultraviolet rays 18 from above.
The resin 15 on the peripheral edge of is cured and temporarily fixed. The wiring board 11 to which a plurality of semiconductor elements 13 are temporarily fixed by the above method is placed in a vacuum bag 17 made of nylon, polypropylene, etc., as shown in FIG. Apply equal atmospheric pressure to everything. By heating the resin 15 in this state, the entire resin 15 is cured, and its adhesive strength causes the electrode 14 of the semiconductor element 13 to harden.
The electrical connection of the conductor wiring 12 and the mechanical holding of the semiconductor element 13 are completed.

なお、真空包装後に圧力容器等に入れ、大気圧
以上もしくは以下の圧力を加えることが可能なの
も明らかである。 It is also obvious that after vacuum packaging, it can be placed in a pressure vessel or the like and a pressure of above or below atmospheric pressure can be applied.

発明の効果 本発明の効果を以下に示す。Effect of the invention The effects of the present invention are shown below.

(1) 複数個の半導体素子を簡易に加圧することが
できるため、量産性に優れる。また、大気圧を
利用するため、圧力が均等に加わり、半導体素
子に与えるひずみをなくすることができ、高品
質を得ることができる。(1) Since multiple semiconductor elements can be easily pressurized, mass productivity is excellent. Furthermore, since atmospheric pressure is used, the pressure is applied evenly, eliminating strain on the semiconductor elements and providing high quality.

(2) 真空包装材の熱容量が小さいため、熱硬化時
の昇温時間、冷却時間を短かくでき、生産性が
向上する。(2) Since the heat capacity of the vacuum packaging material is small, the heating time and cooling time during thermosetting can be shortened, improving productivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ〜ｃは、本発明の半導体装置の製造方
法の一実施例を示す各工程の断面図、第２図ａ〜
ｃは従来の技術を示す各工程の断面図である。 １１……配線基板、１２……導体配線、１３…
…半導体素子、１４……半導体素子の電極、１５
……絶縁性の樹脂、１６……加圧ツール、１７…
…真空袋、１８……紫外線。 FIGS. 1a to 1c are cross-sectional views of each step showing an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS.
c is a cross-sectional view of each process showing a conventional technique. 11... Wiring board, 12... Conductor wiring, 13...
...Semiconductor element, 14... Electrode of semiconductor element, 15
...Insulating resin, 16...Pressure tool, 17...
...Vacuum bag, 18...Ultraviolet light.

Claims (1)

【特許請求の範囲】 １ 導体配線を有した配線基板上に樹脂により半
導体素子が固着され、かつ前記半導体素子の電極
と前記配線基板の導体配線が圧接させ、前記半導
体素子を前記配線基板に真空包装による気圧を用
いて加圧した状態で前記樹脂の硬化を行なう半導
体装置の製造方法。 ２ 半導体素子が電極が突起電極である請求項１
記載の半導体装置の製造方法。[Scope of Claims] 1. A semiconductor element is fixed with resin on a wiring board having conductor wiring, and electrodes of the semiconductor element and conductor wiring of the wiring board are brought into pressure contact, and the semiconductor element is attached to the wiring board under vacuum. A method for manufacturing a semiconductor device, in which the resin is cured under pressure using air pressure generated by packaging. 2. Claim 1 in which the electrodes of the semiconductor element are protruding electrodes.
A method of manufacturing the semiconductor device described above.
JP63024219A 1988-02-04 1988-02-04 Manufacture of semiconductor device Granted JPH01199440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63024219A JPH01199440A (en) 1988-02-04 1988-02-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63024219A JPH01199440A (en) 1988-02-04 1988-02-04 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPH01199440A JPH01199440A (en) 1989-08-10
JPH0519306B2 true JPH0519306B2 (en) 1993-03-16

Family

ID=12132174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63024219A Granted JPH01199440A (en) 1988-02-04 1988-02-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01199440A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1041694A (en) * 1996-07-25 1998-02-13 Sharp Corp Substrate mounting structure for semiconductor element and its mounting method
JP4513235B2 (en) * 2001-05-31 2010-07-28 ソニー株式会社 Flip chip mounting device
JP4710205B2 (en) * 2001-09-06 2011-06-29 ソニー株式会社 Flip chip mounting method
US7456050B2 (en) * 2003-07-01 2008-11-25 Stmicroelectronics, Inc. System and method for controlling integrated circuit die height and planarity
JP4780023B2 (en) * 2007-04-09 2011-09-28 日立化成工業株式会社 Multi-chip module mounting method

Also Published As

Publication number Publication date
JPH01199440A (en) 1989-08-10

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