JPS63240036A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63240036A JPS63240036A JP7464787A JP7464787A JPS63240036A JP S63240036 A JPS63240036 A JP S63240036A JP 7464787 A JP7464787 A JP 7464787A JP 7464787 A JP7464787 A JP 7464787A JP S63240036 A JPS63240036 A JP S63240036A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- chip
- semiconductor
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000011347 resin Substances 0.000 claims abstract description 30
- 229920005989 resin Polymers 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 4
- 238000001723 curing Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関し、特にメモリーモ
ジュール、ＬＥＤ アレー、イメージセンサ−等の高
密度なマルチチップ実装に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method for manufacturing semiconductor devices, and in particular to high-density multi-chip packaging of memory modules, LED arrays, image sensors, and the like.
従来の技術 従来の技術を第２図とともに説明する。Conventional technology The conventional technology will be explained with reference to FIG.
まず第２図ａに示す様に、ガラス等よりなる配線基板２
１の導体配線２２を有した面の、第１の半導体チップが
搭載される領域に、光硬化性の接続樹脂２３ｆ、塗布す
る。次に第２図すのごとく、Ａｕ等よりなる突起電極２
６を有した、第１の半導体チップ２４を、突起電極２５
と導体配線２２が一致する様に配線基板２１に加圧ツー
ル２６により加圧する。First, as shown in FIG. 2a, a wiring board 2 made of glass or the like.
A photocurable connection resin 23f is applied to the area where the first semiconductor chip is mounted on the surface having the first conductor wiring 22. Next, as shown in Figure 2, a protruding electrode 2 made of Au etc.
6, the first semiconductor chip 24 is connected to the protruding electrode 25.
Pressure is applied to the wiring board 21 using the pressure tool 26 so that the conductor wiring 22 and the conductor wiring 22 are aligned with each other.
次に半導体チップ２４を加圧した状態で配線基板２１の
裏面より第１の半導体チップより十分広い領域に光照射
２７し、接続樹脂２３を硬化し、第２図Ｃに示す様に、
第１の半導体チップ２４を配線基板２１に固着するとと
もに半導体チップ２４の突起電極２６と導体配線２２を
電気的に接続する。次に第２図ｄに示す様に、第１の半
導体チップ２４の接続と同様の方法で第２の半導体チツ
ブ２８を配線基板２１に接続しマルチチップの実装を行
うものである。Next, with the semiconductor chip 24 under pressure, light is irradiated 27 from the back surface of the wiring board 21 to an area sufficiently wider than the first semiconductor chip to harden the connection resin 23, as shown in FIG. 2C.
The first semiconductor chip 24 is fixed to the wiring board 21, and the protruding electrodes 26 of the semiconductor chip 24 and the conductor wiring 22 are electrically connected. Next, as shown in FIG. 2d, the second semiconductor chip 28 is connected to the wiring board 21 in the same manner as the first semiconductor chip 24, thereby performing multi-chip mounting.
発明が解決しようとする問題点 前述した従来の技術では、接続樹脂の硬化時に。The problem that the invention aims to solve In the conventional technology described above, when the connection resin is cured.
半導体チップより十分広い領域に光照射するため。To irradiate light onto a sufficiently wider area than the semiconductor chip.
次に示す問題点がある。There are the following problems.
（１）半導体チップの周囲にはみ出した接続樹脂も硬化
される為、隣接する半導体テップとのギャップ（第２図
ｄの２９）ｆｒ、１Ｈ〜２１１Ｉ１以上にする必要が、
半導体チップの実装密度が低い。(1) Since the connecting resin protruding around the semiconductor chip is also cured, the gap (29 in Fig. 2 d) fr, 1H to 211I1 or more must be made between the adjacent semiconductor tips.
The packaging density of semiconductor chips is low.
（２） （１）の理由により配線基板が大きくなり、
コストの高いものとなる。(2) Due to the reason in (1), the wiring board becomes larger.
The cost will be high.
（３）第１の半導体チップからはみ出た接続樹脂が、隣
接する半導体チップと接続する導体配線に達した場合は
その部分まで硬化される為、そこに接続された半導体チ
ップの接続部は接触抵抗が高く、信頼性が低い。(3) If the connecting resin protruding from the first semiconductor chip reaches the conductor wiring that connects to the adjacent semiconductor chip, it will be hardened to that part, so the connection part of the semiconductor chip connected there will have a contact resistance. is high and reliability is low.
（４） ＬＥＤ プリンターのＬＥＤ アレー等で
は、半導体チップ間を、数十ミクロン以下にする必要が
あり、適用が困難である。(4) LED In LED arrays for printers, etc., the distance between semiconductor chips needs to be several tens of microns or less, making it difficult to apply.
問題点を解決するための手段
本発明は前記問題点を解決するために、接続樹脂に光照
射する時にマスクを用い、半導体チップの周囲にはみ出
した樹脂は硬化しないようにしたものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a mask when irradiating the connecting resin with light so that the resin protruding around the semiconductor chip is not hardened.
すなわち１本発明の半導体装置の製造方法は、第１の主
面に導体配線を有した絶縁性透明基板の半導体素子を設
置する領域に光硬化性絶縁樹脂と塗布する工程と、前記
導体配線と前記半導体素子の電極を一致させかつ前記電
極が前記導体配線に接触するように前記半導体素子を前
記絶縁性透明基板に加圧する工程と、前記半導体素子を
前記絶縁性透明基板に加圧した状態で、前記絶縁性透明
基板の第２の主面工り、マスクを用いて前記半導体素子
の面積以下の領域に光照射し、前記光硬化性絶縁樹脂を
硬化し、前記半導体素子を前記絶縁性透明基板に固着す
ると共に、前記半導体素子の電極と前記導体配線を電気
的に接続する工程を備えてなるものである。In other words, the method for manufacturing a semiconductor device of the present invention includes the steps of: applying a photocurable insulating resin to a region where a semiconductor element is to be installed on an insulating transparent substrate having conductor wiring on a first main surface; Pressing the semiconductor element against the insulating transparent substrate so that the electrodes of the semiconductor element are aligned and the electrodes are in contact with the conductive wiring, and the semiconductor element is pressed against the insulating transparent substrate. , processing the second main surface of the insulating transparent substrate, irradiating light onto an area smaller than or equal to the area of the semiconductor element using a mask, curing the photocurable insulating resin, and converting the semiconductor element into the insulating transparent substrate. The method includes a step of fixing the semiconductor element to the substrate and electrically connecting the electrode of the semiconductor element and the conductor wiring.
作 用
本発明においては、半導体素子の周囲にはみ出した樹脂
は硬化しないため、隣接する半導体素子を非常に狭い間
隔で配線基板に接続できる。Function: In the present invention, since the resin protruding around the semiconductor element does not harden, adjacent semiconductor elements can be connected to the wiring board at very narrow intervals.
実施例 本発明の一実施例を第１図とともに説明する。Example An embodiment of the present invention will be described with reference to FIG.
まず、第１図ａに示す様に、ガラス、エポキシ。First, as shown in Figure 1a, glass and epoxy.
アクリル等よりなる配線基板１の導体配線２を有する面
の後に半導体チップが搭載される領域に光硬化性の接続
樹脂３ｆ、塗布する。導体配線２は。A photocurable connection resin 3f is applied to the area where the semiconductor chip is to be mounted after the surface of the wiring board 1 made of acrylic or the like having the conductor wiring 2. Conductor wiring 2.
Ｉ Ｔｏ 、 Ｃｒ −Ａｕ 、 Ａｌ１等よりなり、
厚みは０．１μｍ〜１ｏＩＩｘｎ程度である。接続樹脂
３は、アクリル、エポキシ、シリコーン等であり導体配
線２が。Consisting of ITo, Cr-Au, Al1, etc.
The thickness is about 0.1 μm to 1oIIxn. The connection resin 3 is made of acrylic, epoxy, silicone, etc., and the conductor wiring 2 is made of acrylic, epoxy, silicone, etc.
ＩＴＯ以外の場合は不透明である為、光硬化と常温硬化
または加熱硬化の併用タイプを用いる。Since materials other than ITO are opaque, a combination of light curing, room temperature curing, or heat curing is used.
接続樹脂３の塗布の方法は、ディスペンス、印刷等を用
いる。この時、接続樹脂３が隣接する半導体チップを接
続する導体配線２′に達してもかまわない。また、本実
施例では、接続する半導体チップ毎に接続樹脂３を塗布
する方法であるが、最初に配線基板１内の半導体チップ
を搭載する領域全部に塗布する方法でもよい。The connection resin 3 is applied by dispensing, printing, or the like. At this time, there is no problem even if the connecting resin 3 reaches the conductor wiring 2' connecting adjacent semiconductor chips. Further, in this embodiment, the connection resin 3 is applied to each semiconductor chip to be connected, but it may be applied to the entire area in the wiring board 1 where the semiconductor chips are to be mounted first.
次に第１図すに示す様に、突起電極６を有した第１の半
導体チップ４を突起電極５と導体配線２が一致する様に
配線基板１に設置し、加圧ツール６に加圧する。突起電
極６は、１０ ｐｍＪ３〜６０μｍロ程度であり、厚み
は１μｍ〜３０μｍ程度である。Next, as shown in FIG. 1, the first semiconductor chip 4 having the protruding electrodes 6 is placed on the wiring board 1 so that the protruding electrodes 5 and the conductor wiring 2 are aligned, and the pressurizing tool 6 is used to apply pressure. . The protruding electrode 6 has a size of about 10 pmJ3 to 60 μm and a thickness of about 1 μm to 30 μm.
材質はＡｕ 、 Ｃｕ 、 Ａ１等を用いる。半導体チ
ップ４の加圧力は６〜１６ｏｆ／電極である。半導体テ
ップ４の加圧時に、導体配線２上にあった接続樹脂３は
周囲に押し出され、突起電極６と導体配線２は電気的に
接触する。また、第１の半導体テップ４の周囲にはみ出
した接続樹脂３は隣接する半導体チップの搭載領域にま
で達する。The material used is Au, Cu, A1, etc. The pressing force of the semiconductor chip 4 is 6 to 16 of/electrode. When the semiconductor tip 4 is pressurized, the connecting resin 3 on the conductor wiring 2 is pushed out to the periphery, and the protruding electrode 6 and the conductor wiring 2 are brought into electrical contact. Further, the connecting resin 3 protruding around the first semiconductor chip 4 reaches the mounting area of the adjacent semiconductor chip.
次に、配線基板１の半導体チップを設置しない面に、第
１の半導体チップ４の周囲にはみ出した接続樹脂３に、
後に照射する光があたらない様なしゃへい部を有したマ
スク７を設置した後、たとえば紫外光８′ｆ、照射し、
第１の半導体チップ４の接続樹脂３を硬化し、第１の半
導体チップ４ｆｒ、配線基板１に固着するとともに第１
の半導体チップ４の突起電極５と導体配線２全電気的に
接続する。Next, on the side of the wiring board 1 on which the semiconductor chip is not installed, the connection resin 3 protruding around the first semiconductor chip 4 is
After installing a mask 7 having a shielding part that prevents the light to be irradiated later, for example, irradiating with ultraviolet light 8'f,
The connecting resin 3 of the first semiconductor chip 4 is cured, the first semiconductor chip 4fr is fixed to the wiring board 1, and the first
The protruding electrodes 5 of the semiconductor chip 4 and the conductor wiring 2 are electrically connected.
この時、第１の半導体チップ４の周囲にはみ出した接続
樹脂３は、マスク７により光を遮閉される為、硬化され
ない。マスク７は、Ｎ１ やステンレス等の金属枚ある
いはフォトマスク等を用いる。At this time, the connecting resin 3 protruding around the first semiconductor chip 4 is not cured because the light is blocked by the mask 7. As the mask 7, a metal sheet such as N1 or stainless steel, a photomask, or the like is used.
光照射の時間は、０．５秒〜５秒程度である。また導体
配線がＣｒ −Ａｕ等の不透明な場合は、光と常温硬化
の併用タイプを用いることにより完全に硬化する。The light irradiation time is about 0.5 seconds to 5 seconds. Further, if the conductor wiring is opaque such as Cr-Au, it can be completely cured by using a combination type of light and room temperature curing.
次に第１図ｄに示す様に、第２の半導体チップ９を、第
１の半導体チップと同様の方法で接続する。この時、第
１の半導体チップ４の周囲にはみ出た接続樹脂３は硬化
していない為、第１の半導体チップ４と第２の半導体チ
ップ９の間隔は従来のように広くする必要がなく、半導
体チップの外形寸法に制約されるだけであり、５μｍ程
度まで小さくすることができる。Next, as shown in FIG. 1d, the second semiconductor chip 9 is connected in the same manner as the first semiconductor chip. At this time, since the connecting resin 3 protruding around the first semiconductor chip 4 has not hardened, there is no need to widen the gap between the first semiconductor chip 4 and the second semiconductor chip 9 as in the conventional case. It is only limited by the external dimensions of the semiconductor chip, and can be reduced to about 5 μm.
発明の効果
本発明では、半導体チップの周囲にはみ出した接続樹脂
は、マスクにより光を遮閉し、硬化しない方法であるた
め、次に示す効果がある。Effects of the Invention In the present invention, since the connecting resin protruding around the semiconductor chip is shielded from light by a mask and is not cured, the following effects can be obtained.
（１） 隣接する半導体チップとの間隔を数μｍ程度
まで小さくすることができる為実装密度が高い。(1) Since the distance between adjacent semiconductor chips can be reduced to about several μm, the packaging density is high.
（２） （１）の理由に工り、配線基板を小さくする
ことができコストが安い。(2) Due to the reason of (1), the wiring board can be made smaller and the cost is lower.
（３）隣接する半導体チップの間隔を狭くすることがで
きる為、半導体チップ間の導体配線長を短くすることが
でき、信号のスピードが速い。(3) Since the distance between adjacent semiconductor chips can be narrowed, the length of conductor wiring between semiconductor chips can be shortened, and the signal speed can be increased.
したがって、メモリーモジュールやコンピュータ用のモ
ジュールに有効である。Therefore, it is effective for memory modules and computer modules.
（４） 半導体チップの間隔全数十ミクロン以下にす
る必要のあるＬＥＤプリンターのＬＥＤアレー等への適
用が可能となり、適用範囲が広い。(4) It can be applied to LED arrays of LED printers, etc., which require the total spacing between semiconductor chips to be several tens of microns or less, and has a wide range of applications.
第１図は本発明の一実施例方法を示す工程断面図、第２
図は従来の方法を示す工程断面図である。
１・・・・・・配線基板、２．２’ ・・・・・・導体
配線、３・・・・・・接続樹脂、４，９・・・・・・半
導体チップ、５，１０・・・・・・突起電極、６・・・
・・・加圧ツール、了・・・・・・マスク、８・・・・
・・光照射。Fig. 1 is a process sectional view showing one embodiment of the method of the present invention;
The figure is a process sectional view showing a conventional method. 1... Wiring board, 2.2'... Conductor wiring, 3... Connection resin, 4, 9... Semiconductor chip, 5, 10... ...Protruding electrode, 6...
...Pressure tool, complete...Mask, 8...
...Light irradiation.
Claims (1)
素子を設置する領域に光硬化性絶縁樹脂を塗布する工程
と、前記導体配線と前記半導体素子の電極を一致させか
つ前記電極が前記導体配線に接触する様に前記半導体素
子を前記絶縁性透明基板に加圧する工程と、前記半導体
素子と前記絶縁性透明基板に加圧した状態で、前記絶縁
性透明基板の第２の主面より、マスクを用いて前記半導
体素子の面積以下の領域に光照射し、前記光硬化性絶縁
樹脂を硬化し、前記半導体素子を前記絶縁性透明基板に
固着すると共に、前記半導体素子の電極と前記導体配線
を電気的に接続する工程を備えてなる半導体装置の製造
方法。a step of applying a photocurable insulating resin to an area where a semiconductor element is to be installed on an insulating transparent substrate having a conductor wiring on a first main surface; and aligning the conductor wiring and the electrode of the semiconductor element, and pressurizing the semiconductor element to the insulating transparent substrate so as to contact the conductor wiring; and applying pressure to the semiconductor element and the insulating transparent substrate, applying pressure to the second main surface of the insulating transparent substrate; Then, using a mask, a region smaller than or equal to the area of the semiconductor element is irradiated with light, the photocurable insulating resin is cured, the semiconductor element is fixed to the insulating transparent substrate, and the electrodes of the semiconductor element and the A method for manufacturing a semiconductor device comprising a step of electrically connecting conductor wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7464787A JPH0656862B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7464787A JPH0656862B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63240036A true JPS63240036A (en) | 1988-10-05 |
| JPH0656862B2 JPH0656862B2 (en) | 1994-07-27 |
Family
ID=13553224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7464787A Expired - Fee Related JPH0656862B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656862B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03159197A (en) * | 1989-11-16 | 1991-07-09 | Matsushita Electric Ind Co Ltd | Bonding device for flip chip |
| JP2015061008A (en) * | 2013-09-20 | 2015-03-30 | パナソニック株式会社 | Bonding device |
-
1987
- 1987-03-27 JP JP7464787A patent/JPH0656862B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03159197A (en) * | 1989-11-16 | 1991-07-09 | Matsushita Electric Ind Co Ltd | Bonding device for flip chip |
| JP2015061008A (en) * | 2013-09-20 | 2015-03-30 | パナソニック株式会社 | Bonding device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0656862B2 (en) | 1994-07-27 |
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