JPH05102343A - Mounting structure of semiconductor device and mounting method of semiconductor device - Google Patents

Mounting structure of semiconductor device and mounting method of semiconductor device

Info

Publication number
JPH05102343A
JPH05102343A JP3260072A JP26007291A JPH05102343A JP H05102343 A JPH05102343 A JP H05102343A JP 3260072 A JP3260072 A JP 3260072A JP 26007291 A JP26007291 A JP 26007291A JP H05102343 A JPH05102343 A JP H05102343A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
glass wiring
semiconductor
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3260072A
Other languages
Japanese (ja)
Inventor
Hidekazu Sato
英一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3260072A priority Critical patent/JPH05102343A/en
Publication of JPH05102343A publication Critical patent/JPH05102343A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a method by which the reliability on the connection is high and which never causes electric conductivity trouble, in case of mounting a semiconductor element on a glass board, with the active face opposite to it. CONSTITUTION:A semiconductor element 1 is loaded on a wiring board 4 where a through hole 9 is opened, and the adhesive for fixing is hardened by heat. Moreover, in case of having used a photosetting adhesive, it can be made the hardening from the rear of the semiconductor device and the hardening from the rear of the glass board. This way, by having opened a through hole, the adhesive can be escaped to outside, so it does not give stress to the connection. Moreover, even if trouble should be found, the semiconductor device could be removed simply from the glass wiring board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子をガラス配
線基板上に実装してなる半導体装置の実装構造及び実装
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure and a mounting method for a semiconductor device in which a semiconductor element is mounted on a glass wiring board.

【0002】[0002]

【従来の技術】近年液晶表示体や、ICメモリーカード
等、一定面積の配線基板内に、複数の半導体素子を高密
度に、かつ薄く実装する需要が高まっている。
2. Description of the Related Art In recent years, there has been an increasing demand for mounting a plurality of semiconductor elements at high density and thinly on a wiring substrate having a constant area such as a liquid crystal display or an IC memory card.

【0003】これらの要望に応えるべき実装方法とし
て、図5に示すごとく半導体素子1の能動面2を、ガラ
ス配線基板4上に配設した配線パターン5上の導電粒子
15を配置した接続部6と対向して配置した後、半導体
素子1の電極3と接続部6を整合して固定用接着剤8を
硬化させ半導体素子1の電極3と、ガラス配線基板4に
配置した配線パターン5の接続部6とを電気的に接続す
る方法が知られている。このようなガラス配線基板4と
半導体素子1との固定には、固定用接着剤8をポッティ
ングあるいは転写印刷等の配置手段により塗布した後、
半導体素子1の電極3と、ガラス配線基板4の接続部6
を整合してガラス配線基板4上に半導体素子1を載置し
て、図6の断面図のごとく、図示しない上下機構を有す
る加熱ツール11を下降して半導体素子裏面12より加
熱、押圧することにより、固定用接着剤8を硬化させた
後再び加熱ツール11を上昇することによって、半導体
素子1の電極3とガラス配線基板4上の配線パターン5
の接続部6との電気的な接続を可能としていた。
As a mounting method to meet these demands, as shown in FIG. 5, the active surface 2 of the semiconductor element 1 is connected to the connection portion 6 in which the conductive particles 15 are arranged on the wiring pattern 5 arranged on the glass wiring board 4. Then, the electrode 3 of the semiconductor element 1 is aligned with the connecting portion 6 and the fixing adhesive 8 is cured to connect the electrode 3 of the semiconductor element 1 to the wiring pattern 5 arranged on the glass wiring board 4. A method for electrically connecting the portion 6 is known. In order to fix the glass wiring board 4 and the semiconductor element 1 to each other as described above, the fixing adhesive 8 is applied by an arrangement means such as potting or transfer printing,
Connection part 6 between electrode 3 of semiconductor element 1 and glass wiring board 4
The semiconductor element 1 is placed on the glass wiring substrate 4 in alignment with each other, and the heating tool 11 having an up / down mechanism (not shown) is lowered to heat and press from the semiconductor element back surface 12 as shown in the sectional view of FIG. Then, the fixing adhesive 8 is hardened and then the heating tool 11 is raised again, whereby the electrode 3 of the semiconductor element 1 and the wiring pattern 5 on the glass wiring substrate 4
It was possible to make an electrical connection with the connection portion 6 of.

【0004】[0004]

【発明が解決しようとする課題】しかし前述の従来技術
では半導体素子の電極と、配線パターンとの接続の場
合、加熱工具の加熱分布の不均一や、半導体素子裏面の
表面状態、また固定用接着剤の硬化速度の不均一、基板
接続箇所の放熱状態の違い等のため固定用接着剤の硬化
不良を起こして電気的接続不良を起こし易いという問題
点を有する。
However, in the above-mentioned prior art, in the case of connecting the electrode of the semiconductor element and the wiring pattern, the heat distribution of the heating tool is not uniform, the surface state of the back surface of the semiconductor element, and the bonding for fixing. There is a problem that the fixing adhesive is apt to be hardened due to the uneven curing rate of the agent, the difference in the heat radiation state of the substrate connecting portion, and the like, and the electrical connection is easily caused.

【0005】また、接続後の信頼性試験において、熱衝
撃試験を繰り返した場合半導体素子、配線基板、及び固
定用接着剤、それぞれの接続面での界面剥離や、固定用
接着剤の割れ、接続部の浮きによる電気的な導通不良等
の問題点が発生する。
Further, in the reliability test after connection, when the thermal shock test is repeated, the semiconductor element, the wiring board, and the fixing adhesive, interface peeling on each connection surface, cracking of the fixing adhesive, and connection Problems such as poor electrical continuity due to floating parts occur.

【0006】更に、接続した半導体素子の電気特性検査
の結果、接続不良や半導体素子の機能不良が判明して
も、半導体素子を接続箇所から取り外すことが困難であ
るという問題点もあった。
Further, even if a defective connection or a defective function of the semiconductor element is found as a result of the inspection of the electric characteristics of the connected semiconductor element, it is difficult to remove the semiconductor element from the connection point.

【0007】そこで本発明はこのような問題点を解決す
るために為されたものであり、その目的は基板上に半導
体素子を接続する場合に、接続部の信頼性が高くかつ電
気的な導通不良のおこることの無い半導体装置の実装構
造及び接続部の信頼性が高く電気的な導通不良が起こる
ことが無く、かつ、万一不良の発見された場合でも半導
体素子のガラス配線基板からの取り外しが簡単にできる
半導体装置の実装方法を提供するところにある。
Therefore, the present invention has been made to solve the above problems, and its purpose is to provide a highly reliable and electrically conductive connecting portion when connecting a semiconductor element on a substrate. Defect-free mounting structure of semiconductor device and highly reliable connection part does not cause electrical continuity failure, and even if a failure is found, removal of semiconductor element from glass wiring board There is provided a method of mounting a semiconductor device which can be easily manufactured.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置の実
装構造は、半導体素子と、半導体素子の電極と対向する
位置に接続部を有するガラス配線基板とを、半導体素子
の能動面あるいはガラス配線基板の半導体素子配置範囲
に固定用接着剤を塗布した後、半導体素子の能動面と前
記ガラス配線基板とを対向して配置し、半導体素子の電
極とガラス配線基板の接続部とを電気的に接続をする半
導体装置に於て、半導体素子の能動面と対向したガラス
配線基板の半導体素子配置範囲内に、ガラス配線基板の
表面と裏面とを貫通する貫通穴を配置したガラス配線基
板の接続部と、半導体素子の電極とを整合し載置した
後、半導体素子の裏面より、加圧及び加熱することで固
定用接着剤を硬化して、半導体素子とガラス配線基板と
を接続することを特徴とする。
According to the mounting structure of a semiconductor device of the present invention, a semiconductor element and a glass wiring board having a connecting portion at a position facing an electrode of the semiconductor element are connected to an active surface of the semiconductor element or a glass wiring. After applying a fixing adhesive to the semiconductor element arrangement area of the substrate, the active surface of the semiconductor element and the glass wiring board are arranged to face each other, and the electrodes of the semiconductor element and the connection portion of the glass wiring board are electrically connected. In a semiconductor device for connection, a connection portion of a glass wiring board in which a through hole penetrating the front surface and the back surface of the glass wiring board is arranged within the semiconductor element arrangement range of the glass wiring board facing the active surface of the semiconductor element. And the electrodes of the semiconductor element are aligned and placed, and the fixing adhesive is cured by applying pressure and heat from the back surface of the semiconductor element to connect the semiconductor element and the glass wiring board. To.

【0009】また本発明の半導体装置の実装方法は、半
導体素子と、半導体素子の電極と対向する位置に接続部
を有するガラス配線基板とを、半導体素子の能動面ある
いはガラス配線基板の半導体素子配置範囲内にガラス配
線基板の表面と裏面を貫通する貫通穴を有する半導体素
子配置範囲を含む範囲に光硬化型接着剤を塗布する工程
とガラス配線基板の接続部と半導体素子の電極とを整合
し載置する工程と、半導体素子裏面側よりガラス配線基
板を露光する工程と、半導体素子裏面より接続部を加圧
しかつガラス配線基板裏面側より半導体素子配置範囲を
含む範囲を露光する工程とからなることを特徴とする。
According to the method of mounting a semiconductor device of the present invention, a semiconductor element and a glass wiring board having a connecting portion at a position facing an electrode of the semiconductor element are disposed on an active surface of the semiconductor element or a semiconductor element arrangement of the glass wiring board. The step of applying the photo-curable adhesive to the range including the semiconductor element arrangement range having the through holes penetrating the front surface and the back surface of the glass wiring board within the range, the connection part of the glass wiring board and the electrode of the semiconductor element are aligned. It comprises a step of placing, a step of exposing the glass wiring board from the back side of the semiconductor element, and a step of exposing the range including the semiconductor element placement range from the back side of the glass wiring board by pressurizing the connection part from the back side of the semiconductor element. It is characterized by

【0010】[0010]

【作用】本発明の上記の半導体装置の実装構造によれば
まず半導体素子の能動面あるいはガラス配線基板の半導
体素子配置範囲に固定用接着剤を塗布した後半導体素子
の能動面と前記ガラス配線基板とを対向して配置し半導
体素子の電極とガラス配線基板の接続部とを電気的に接
続をする半導体装置に於て、半導体素子の能動面と対向
したガラス配線基板の半導体素子配置範囲内に、ガラス
配線基板の表面と裏面とを貫通する貫通穴を配置したガ
ラス配線基板の接続部と、半導体素子の電極とを整合し
載置した後、半導体素子の裏面より、加圧及び加熱する
ことで固定用接着剤を硬化させ、半導体素子とガラス配
線基板とを接続するとき、貫通穴を通じて加圧による固
定用接着剤の余剰量また加熱による固定用接着剤の膨張
分を逃がし、半導体素子の能動面とガラス配線基板の間
の接着剤層の押し広げ力を緩和することができる。
According to the mounting structure of the semiconductor device of the present invention, first, the fixing adhesive is applied to the active surface of the semiconductor element or the semiconductor element arrangement area of the glass wiring board, and then the active surface of the semiconductor element and the glass wiring board. In a semiconductor device in which the electrodes of the semiconductor element are electrically connected to the connection portion of the glass wiring board by facing the After pressing and heating from the back surface of the semiconductor element after aligning and mounting the electrode of the semiconductor element with the connection portion of the glass wiring board in which the through holes penetrating the front surface and the back surface of the glass wiring substrate are arranged. When the fixing adhesive is hardened with, and the semiconductor element and the glass wiring board are connected, the excess amount of the fixing adhesive due to pressure and the expansion of the fixing adhesive due to heating are released through the through holes, and the semiconductor is removed. It is possible to alleviate the pressing spread strength of the adhesive layer between the active surface of the element and the glass wiring substrate.

【0011】また、本発明の半導体装置の実装方法によ
れば、半導体素子と、半導体素子の電極と対向する位置
に接続部を有するガラス配線基板とを、半導体素子の能
動面あるいはガラス配線基板の半導体素子配置範囲に、
ガラス配線基板の表面と裏面を貫通する貫通穴を有する
半導体素子配置範囲を含む範囲に、光硬化型接着剤を塗
布する工程と、ガラス配線基板の接続部と、半導体素子
の電極とを整合し載置する工程と、半導体素子裏面側よ
りガラス配線基板を露光する工程と、半導体素子裏面よ
り接続部を加圧しかつガラス配線基板裏面側より半導体
素子配置範囲を含む範囲を露光する工程とからなり、半
導体素子裏面側からの露光後に、電気特性検査を行うこ
とで不良が発見されたときには、半導体素子周囲の硬化
範囲の光硬化型接着剤を除去することにより半導体素子
の取り替えが可能となり、かつガラス配線基板裏面より
の半導体素子配置範囲の露光時には、貫通穴により加圧
による光硬化型接着剤の加圧分を逃がすことが可能とな
る。
Further, according to the semiconductor device mounting method of the present invention, the semiconductor element and the glass wiring board having the connecting portion at a position facing the electrode of the semiconductor element are connected to the active surface of the semiconductor element or the glass wiring board. In the semiconductor element arrangement range,
The step of applying the photo-curable adhesive to the range including the semiconductor element arrangement range having the through holes penetrating the front surface and the back surface of the glass wiring board, the connection portion of the glass wiring board, and the electrode of the semiconductor element are aligned. It comprises a step of placing, a step of exposing the glass wiring substrate from the back side of the semiconductor element, and a step of exposing the range including the semiconductor element placement range from the back side of the glass wiring board by pressurizing the connecting portion from the back side of the semiconductor element. When a defect is found by conducting an electrical characteristic test after exposure from the back side of the semiconductor element, the semiconductor element can be replaced by removing the photo-curable adhesive in the curing range around the semiconductor element, and During the exposure of the semiconductor element arrangement range from the back surface of the glass wiring board, it is possible to release the pressure portion of the photocurable adhesive due to the pressure due to the through hole.

【0012】[0012]

【実施例】図1及び図2は、本発明の半導体装置の実装
構造の実施例を模式的に示す断面図であり、1は半導体
素子、2は半導体素子1の能動面、3は半導体素子1の
電極で、半導体素子1の電極上に金メッキを施し半導体
素子1の能動面2上に突起している通常金バンプと称す
る電極を使用した。4はガラス配線基板で、本説明にお
いてはガラス製液晶表示体を用いた。ガラス配線基板4
の表面には透明導電膜(ITO)により形成した配線パ
ターン5を配置した。6は半導体素子1の電極3と対向
して配置した配線パターン5の接続部である。7はガラ
ス配線基板4の半導体素子配置範囲、8は固定用接着剤
であり熱硬化性の樹脂を用い今回はエポキシ系接着剤を
用いた。また9はガラス配線基板4の貫通穴であり今回
は、ガラス配線基板裏面10より圧縮空気中に微細砥粒
を混練し吹き付けるエアーブレイシブル法を用いて0.
5mm直径の貫通穴を形成した。以上について実施例を
詳細に説明する。
1 and 2 are cross-sectional views schematically showing an embodiment of a mounting structure of a semiconductor device according to the present invention, in which 1 is a semiconductor element, 2 is an active surface of the semiconductor element 1, and 3 is a semiconductor element. As the first electrode, an electrode called gold bump, which is obtained by plating the electrode of the semiconductor element 1 with gold and protruding on the active surface 2 of the semiconductor element 1, was used. Reference numeral 4 denotes a glass wiring board, and a glass liquid crystal display body is used in this description. Glass wiring board 4
A wiring pattern 5 formed of a transparent conductive film (ITO) was arranged on the surface of the. Reference numeral 6 is a connection portion of the wiring pattern 5 arranged so as to face the electrode 3 of the semiconductor element 1. Reference numeral 7 is a semiconductor element arrangement range of the glass wiring board 4, 8 is a fixing adhesive, and a thermosetting resin is used, and an epoxy adhesive is used this time. Further, 9 is a through hole of the glass wiring board 4, and this time, it is set to 0. by using an air breakable method in which fine abrasive grains are kneaded and blown into compressed air from the back surface 10 of the glass wiring board.
A through hole having a diameter of 5 mm was formed. The above will describe the embodiment in detail.

【0013】半導体素子1の能動面2、あるいはガラス
配線基板4の半導体素子配置範囲7に固定用接着剤8を
塗布した後半導体素子1の能動面2とガラス配線基板4
とを対向して配置し、半導体素子1の電極3と、ガラス
配線基板4上に形成した配線パターン5に設けた接続部
6とを整合(位置合わせ)し、半導体素子1をガラス配
線基板4上に載置する。
After applying the fixing adhesive 8 to the active surface 2 of the semiconductor element 1 or the semiconductor element arrangement area 7 of the glass wiring board 4, the active surface 2 of the semiconductor element 1 and the glass wiring board 4 are coated.
Are arranged so as to face each other, the electrode 3 of the semiconductor element 1 and the connection portion 6 provided on the wiring pattern 5 formed on the glass wiring board 4 are aligned (positioned), and the semiconductor element 1 is placed on the glass wiring board 4 Place on top.

【0014】次に図2に示すごとき図示しない上下機構
を有する加熱ツール11を下降して半導体素子裏面12
に当接し加熱ツール11によって加熱、押圧することに
より、固定用接着剤8を硬化させる。この時固定用接着
剤8は加熱ツール11により押圧されることで半導体素
子1の能動面2及びガラス配線基板4の半導体素子配置
範囲7に広がり半導体素子1の能動面2とガラス配線基
板4間に充填され固定用接着剤8の余剰量は半導体素子
1の周囲及び貫通穴9より排出することができる。
Next, the heating tool 11 having a vertical mechanism (not shown) as shown in FIG.
The fixing adhesive 8 is hardened by being brought into contact with and being heated and pressed by the heating tool 11. At this time, the fixing adhesive 8 spreads over the active surface 2 of the semiconductor element 1 and the semiconductor element arrangement area 7 of the glass wiring board 4 by being pressed by the heating tool 11, and between the active surface 2 of the semiconductor element 1 and the glass wiring board 4. The surplus amount of the fixing adhesive 8 filled in can be discharged around the semiconductor element 1 and through the through holes 9.

【0015】更に加熱ツール11よりの伝熱による固定
用接着剤8の硬化は半導体素子1の電極3付近から開始
されるため、接続部6より内部の未硬化の固定用接着剤
8は貫通穴9より排出することで、加熱時に内部に留ま
って硬化部分の固定用接着剤8を押し開こうとしていた
未硬化部分の接着剤の応力を除去して硬化することが可
能なため、固定用接着剤8の半導体素子1及びガラス配
線基板4へのストレスを与えない硬化が可能となる。固
定用接着剤8の加熱硬化終了後に再び加熱ツール11を
上昇することによって、半導体素子1の電極3とガラス
配線基板4上の配線パターン5の接続部6との電気的な
接続が可能となる。
Further, since the hardening of the fixing adhesive 8 by the heat transfer from the heating tool 11 is started from the vicinity of the electrode 3 of the semiconductor element 1, the uncured fixing adhesive 8 inside the connecting portion 6 is a through hole. By discharging the adhesive from the sheet 9, it is possible to remove the stress of the adhesive in the uncured portion that was trying to push open the cured adhesive 8 in the cured portion that stays inside during heating, and thus the adhesive is fixed. The agent 8 can be cured without applying stress to the semiconductor element 1 and the glass wiring board 4. After the heating and curing of the fixing adhesive 8 is completed, the heating tool 11 is lifted again to electrically connect the electrode 3 of the semiconductor element 1 and the connecting portion 6 of the wiring pattern 5 on the glass wiring board 4. ..

【0016】本実施例においては貫通穴9の形成に、エ
アーブレイシブル法を用いたが、超音波による穴明け
や、レーザ加工による穴明け、ガラス配線基板のエッチ
ング等によっても同様な効果を得ることができることは
あきらかであり、また使用する固定用接着剤8の粘度及
び硬化温度により、貫通穴9の穴寸法(穴径)は変化さ
せなければならないことは当然であり貫通穴9の開口方
向、及び開口直径を変化させても本発明に含まれる。
In the present embodiment, the through-hole 9 is formed by using the air blush method. However, the same effect can be obtained by ultrasonic drilling, laser drilling, etching of a glass wiring board, or the like. It is obvious that the hole size (hole diameter) of the through hole 9 must be changed depending on the viscosity and the curing temperature of the fixing adhesive 8 used, and the opening direction of the through hole 9 must be changed. , And even if the opening diameter is changed, it is included in the present invention.

【0017】また固定用接着剤9としてエポキシ系接着
剤を使用しての接続について述べたが、電極と接続部と
の電気的な接続のために金属粒子あるいは半田もしくは
樹脂球表面に金属メッキを施した導電粒子等を用いた
り、固定用接着剤中に金属粒子等の導電粒子を含む、導
電性接着剤や、異方性導電接着剤あるいは、異方性導電
フイルムを使用したり、接続部と固定用の接着剤に異種
の接着剤を使用することによっても貫通穴を使用しての
効果には変わりが無いため本発明に含まれる。
Although the connection using the epoxy adhesive as the fixing adhesive 9 has been described, metal particles or solder or resin sphere surface is plated with metal for electrical connection between the electrode and the connecting portion. The conductive adhesive, the anisotropic conductive adhesive, or the anisotropic conductive film containing conductive particles such as metal particles in the fixing adhesive is used. The effect of using the through-holes is the same even if different kinds of adhesives are used as the fixing adhesives, and therefore, they are included in the present invention.

【0018】更に、アルミナ基板等のセラミック基板を
用いても同等の効果を得ることができ本発明に含まれ
る。
Further, even if a ceramic substrate such as an alumina substrate is used, the same effect can be obtained and is included in the present invention.

【0019】次に本発明による半導体装置の実装方法に
ついて説明する。図3及び図4は本発明にかかる半導体
装置の実装方法の実施例を説明するための断面図であ
る。
Next, a method of mounting the semiconductor device according to the present invention will be described. 3 and 4 are cross-sectional views for explaining an embodiment of a method for mounting a semiconductor device according to the present invention.

【0020】図3において、1は半導体素子、2は半導
体素子1の能動面、3は半導体素子1の電極で、半導体
素子1の電極上に金メッキを施し、半導体素子1の能動
面2上に突起している通常金バンプと称する電極を使用
した。4はガラス配線基板で、本説明においてガラス製
液晶表示体を用い、ガラス配線基板4の表面に透明導電
膜(ITO)により形成した配線パターン5を配置し
た。6は半導体素子1の電極3と対向して配置した配線
パターン5の接続部である。7はガラス配線基板3に設
けられた半導体素子配置範囲、8aは光硬化型接着剤で
固定用接着剤として用いた。また9はガラス配線基板4
の貫通穴である。以上により実施例を詳細に説明する。
In FIG. 3, reference numeral 1 is a semiconductor element, 2 is an active surface of the semiconductor element 1, and 3 is an electrode of the semiconductor element 1. The electrode of the semiconductor element 1 is gold-plated to form an active surface 2 of the semiconductor element 1. An electrode called a protruding gold bump was used. Reference numeral 4 denotes a glass wiring board. In this description, a glass liquid crystal display is used, and a wiring pattern 5 formed of a transparent conductive film (ITO) is arranged on the surface of the glass wiring board 4. Reference numeral 6 is a connection portion of the wiring pattern 5 arranged so as to face the electrode 3 of the semiconductor element 1. 7 is a semiconductor element arrangement range provided on the glass wiring board 3, and 8a is a photocurable adhesive used as a fixing adhesive. 9 is the glass wiring board 4
It is a through hole. The embodiment will be described in detail above.

【0021】まず、半導体素子1の能動面2、あるいは
ガラス配線基板4の貫通穴9を含む半導体装置配置範囲
7、もしくはその双方に光硬化型接着剤8aを塗布す
る。
First, a photo-curable adhesive 8a is applied to the active surface 2 of the semiconductor element 1, the semiconductor device arrangement area 7 including the through hole 9 of the glass wiring board 4, or both.

【0022】次に半導体素子1の能動面2とガラス配線
基板4とを対向して配置し、半導体素子1の電極3と、
ガラス配線基板4上の配線パターン5に設けた接続部6
とを整合(位置合わせ)し、半導体素子1をガラス配線
基板4上に載置する。
Next, the active surface 2 of the semiconductor element 1 and the glass wiring board 4 are arranged so as to face each other, and the electrode 3 of the semiconductor element 1 and
Connection part 6 provided on the wiring pattern 5 on the glass wiring board 4
Are aligned (aligned) with each other, and the semiconductor element 1 is mounted on the glass wiring board 4.

【0023】半導体素子裏面12より半導体素子1を加
圧してガラス配線基板4に押し付けた状態で、半導体素
子1の能動面2及びガラス配線基板4の半導体素子配置
範囲7に広がった光硬化型接着剤8aは、半導体素子1
の能動面2とガラス配線基板4間に充填され、光硬化型
接着剤8aの余剰量は半導体素子1の周囲及び貫通穴9
より排出させる。
In the state where the semiconductor element 1 is pressed from the rear surface 12 of the semiconductor element and pressed against the glass wiring board 4, a photo-curing type adhesive spread over the active surface 2 of the semiconductor element 1 and the semiconductor element arrangement area 7 of the glass wiring board 4. The agent 8a is the semiconductor element 1
Is filled between the active surface 2 and the glass wiring board 4, and the surplus amount of the photo-curable adhesive 8a surrounds the semiconductor element 1 and the through hole 9.
Let it drain more.

【0024】この状態で半導体素子裏面12側より光硬
化型接着剤8aの硬化に有効な波長を有する光源よりの
硬化光13を用いて露光して、半導体素子1周囲付近の
光硬化型接着剤8aを硬化し半導体素子1とガラス配線
基板4とを仮接続する。この時、光硬化型接着剤8aは
半導体素子1の周囲付近のみ硬化し、半導体素子1によ
り遮光された内部の光硬化型接着剤8aは未だ未硬化状
態を維持している。半導体素子裏面12よりの露光によ
る仮接続を終了した後にガラス配線基板4と半導体素子
1との接続及び半導体素子1の電気的特性を調べるため
に電気特性試験を行う。電気特性試験の結果、不良と判
定された半導体素子1は半導体素子1の周囲の光硬化型
接着剤8aを剥離し、再び接続をやり直すことができ
る。
In this state, the back surface 12 of the semiconductor element is exposed by using curing light 13 from a light source having a wavelength effective for curing the photo-curable adhesive 8a to expose the photo-curable adhesive around the semiconductor element 1. 8a is cured and the semiconductor element 1 and the glass wiring board 4 are temporarily connected. At this time, the photo-curable adhesive 8a is cured only around the periphery of the semiconductor element 1, and the internal photo-curable adhesive 8a shielded from light by the semiconductor element 1 is still in an uncured state. After the temporary connection by exposure from the back surface 12 of the semiconductor element is completed, an electrical characteristic test is performed to check the connection between the glass wiring board 4 and the semiconductor element 1 and the electrical characteristic of the semiconductor element 1. The semiconductor element 1 determined to be defective as a result of the electrical characteristic test can be stripped of the photo-curable adhesive 8a around the semiconductor element 1 and re-connected.

【0025】電気特性検査終了後、図4のごとく、接続
に必要となる加圧力を加圧工具14を用いて半導体素子
裏面12から加え、光硬化型接着剤8aの余剰量を貫通
穴9より排出させた後ガラス配線基板裏面10側より光
硬化型接着剤8aの硬化に有効な波長を有する光源より
の硬化光13aを用いて露光し、半導体素子1とガラス
配線基板4との接続を完了する。半導体素子裏面10よ
り加圧し接続圧力を加えた時、未硬化部分の光硬化型接
着剤8aは、半導体素子1の周囲付近が硬化されている
ため貫通穴9よりのみ排出されることになり、内部に残
留する光硬化型接着剤8aの応力を減少した状態での光
硬化が可能となる。
After the completion of the electrical characteristic inspection, as shown in FIG. 4, a pressing force necessary for connection is applied from the back surface 12 of the semiconductor element by using a pressing tool 14, and the surplus amount of the photo-curable adhesive 8a is passed through the through hole 9. After being discharged, the glass wiring board back surface 10 side is exposed by using curing light 13a from a light source having a wavelength effective for curing the photocurable adhesive 8a, and the connection between the semiconductor element 1 and the glass wiring board 4 is completed. To do. When pressure is applied from the semiconductor element back surface 10 and connection pressure is applied, the photo-curable adhesive 8a in the uncured portion is discharged only from the through hole 9 because the vicinity of the semiconductor element 1 is cured. It is possible to perform photo-curing while reducing the stress of the photo-curable adhesive 8a remaining inside.

【0026】また本発明はガラス配線基板により説明し
たが、光透過性セラミック等のような、硬化光の透過可
能な基板については本発明に含まれる。
Although the present invention has been described with reference to a glass wiring board, a substrate capable of transmitting curing light, such as a light transmissive ceramic, is included in the present invention.

【0027】[0027]

【発明の効果】以上述べたごとく本発明の半導体装置の
実装構造によれば、半導体素子の能動面、あるいはガラ
ス配線基板の半導体素子配置範囲内に、ガラス配線基板
の表面と裏面とを貫通する貫通穴を配置したガラス配線
基板の半導体素子配置範囲に、固定用接着剤を塗布した
後、半導体素子の能動面と対向したガラス配線基板の接
続部と、半導体素子の電極とを整合し載置した後、半導
体素子の裏面より、加圧及び加熱することによって半導
体素子とガラス配線基板とを接続することにより、加熱
工具の加熱分布の不均一や、半導体素子裏面の表面状態
また固定用接着剤の硬化速度の不均一、基板接続箇所の
放熱状態の違い等のため固定用接着剤の硬化不良を起こ
して電気的接続不良を起こし易いという状態を、貫通穴
を通じて加圧による固定用接着剤の余剰量、また加熱に
よる固定用接着剤の膨張分を逃がすことで、半導体素子
の能動面とガラス配線基板の間の接着剤層の押し広げ力
を緩和して接続部と半導体素子の電極との接続の密着力
を強め浮きによる接続不良を減少することができる。
As described above, according to the mounting structure of the semiconductor device of the present invention, the front surface and the back surface of the glass wiring board are penetrated into the active surface of the semiconductor element or within the semiconductor element disposition range of the glass wiring board. After applying a fixing adhesive in the semiconductor element arrangement area of the glass wiring board with the through holes, the connection part of the glass wiring board facing the active surface of the semiconductor element and the electrode of the semiconductor element are aligned and placed. After that, the semiconductor element and the glass wiring board are connected to each other by applying pressure and heat from the back surface of the semiconductor element, so that the heating tool has a non-uniform heat distribution, the surface state of the back surface of the semiconductor element, and an adhesive for fixing. When the fixing adhesive is liable to be hardened due to uneven curing speed and difference in heat dissipation at the substrate connection, electrical connection failure may occur. By releasing the surplus amount of the fixing adhesive and the expansion of the fixing adhesive due to heating, the spreading force of the adhesive layer between the active surface of the semiconductor element and the glass wiring board is relaxed, and the connection part and the semiconductor It is possible to increase the adhesiveness of the connection with the electrode of the element and reduce the connection failure due to floating.

【0028】また、本発明の、半導体素子と、半導体素
子の電極と対向する位置に接続部を有しかつ、半導体素
子配置範囲にガラス配線基板の表面と裏面を貫通する貫
通穴を有するガラス配線基板とを、半導体素子の能動面
あるいはガラス配線基板の半導体素子配置範囲を含む範
囲に、光硬化型接着剤を塗布する工程と、ガラス配線基
板の接続部と、半導体素子の電極とを整合し載置する工
程と、半導体素子裏面側よりガラス配線基板を露光する
工程と、半導体素子裏面より接続部を加圧し、かつガラ
ス配線基板裏面側より半導体素子配置範囲を含む範囲を
露光する工程とからなる実装方法によれば、半導体素子
裏面側からの露光後電気特性検査を行うことで、万一接
続不良が発見された場合には、半導体素子周囲付近のの
硬化した光硬化型接着剤を除去することにより簡単に半
導体素子の取り替えが可能となり、かつガラス配線基板
裏面よりの半導体素子配置範囲の露光時には貫通穴によ
り、加圧による光硬化型接着剤の加圧分を逃がすことが
可能となり、半導体素子の能動面とガラス配線基板の間
の接着剤層の押し広げ力を緩和して、接続部と半導体素
子の電極との接続の密着力を強めて浮きによる接続不良
を減少することができるという利点があり、実施による
効果が大である
Further, according to the present invention, a glass wiring having a semiconductor element and a connecting portion at a position facing an electrode of the semiconductor element, and having a through hole penetrating the front surface and the back surface of the glass wiring board in the semiconductor element arrangement range. The substrate and the active surface of the semiconductor element or the range including the semiconductor element arrangement range of the glass wiring board, the step of applying the photo-curable adhesive, the connection portion of the glass wiring board, and the electrode of the semiconductor element are aligned. From the step of placing, the step of exposing the glass wiring substrate from the back side of the semiconductor element, and the step of pressurizing the connection portion from the back side of the semiconductor element and exposing the range including the semiconductor element placement range from the back side of the glass wiring board According to the mounting method, if a connection failure is found by conducting an electrical characteristic inspection after exposure from the back side of the semiconductor element, the cured photo-curable type around the semiconductor element will be used. The semiconductor element can be easily replaced by removing the adhesive, and the exposed portion of the semiconductor element arrangement area from the back surface of the glass wiring board can escape the pressure of the photocurable adhesive due to the pressure due to the through hole. It is possible to reduce the spreading force of the adhesive layer between the active surface of the semiconductor element and the glass wiring board, strengthen the adhesion between the connection part and the electrode of the semiconductor element, and reduce the connection failure due to floating. There is an advantage that it can be done, and the effect of implementation is great

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の実装構造の実施例を模式
的に示した断面図。
FIG. 1 is a sectional view schematically showing an embodiment of a mounting structure of a semiconductor device of the present invention.

【図2】本発明の半導体装置の実装構造の実施例の接続
を説明するための断面図。
FIG. 2 is a cross-sectional view for explaining the connection of the embodiment of the mounting structure of the semiconductor device of the present invention.

【図3】本発明の半導体装置の実装方法の実施例を説明
するための断面図。
FIG. 3 is a sectional view for explaining an embodiment of a method for mounting a semiconductor device of the present invention.

【図4】本発明の半導体装置の実装方法の実施例の接続
方法を説明するための断面図。
FIG. 4 is a cross-sectional view for explaining a connection method of the embodiment of the mounting method of the semiconductor device of the present invention.

【図5】従来の半導体装置の構造を示す断面図。FIG. 5 is a cross-sectional view showing the structure of a conventional semiconductor device.

【図6】従来の半導体装置の接続方法を説明するための
断面図。
FIG. 6 is a sectional view for explaining a conventional method for connecting semiconductor devices.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 能動面 3 電極 4 ガラス配線基板 5 配線パターン 6 接続部 7 半導体素子配置範囲 8 固定用接着剤 8a 光硬化型接着剤 9 貫通穴 10 ガラス配線基板裏面 11 加熱ツール 12 半導体素子裏面 13,13a 硬化光 14 加圧工具 15 導電粒子 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Active surface 3 Electrode 4 Glass wiring board 5 Wiring pattern 6 Connection part 7 Semiconductor element arrangement range 8 Fixing adhesive 8a Photocurable adhesive 9 Through hole 10 Glass wiring board back surface 11 Heating tool 12 Semiconductor element back surface 13 , 13a Curing light 14 Pressure tool 15 Conductive particles

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体素子と、前記半導体素子の電極と対
向する位置に接続部を有するガラス配線基板と固定用接
着剤とからなり、前記半導体素子の能動面と前記ガラス
配線基板とを前記半導体素子の能動面と、前記ガラス配
線基板の間に固定用接着剤を挟み、対向して配置して、
該半導体素子の電極とガラス配線基板の接続部とを、電
気的に接続をする半導体装置に於て、前記半導体素子の
能動面と対向したガラス配線基板の半導体素子配置範囲
内に、ガラス配線基板の表面と裏面とを貫通する貫通穴
を配置したことを特徴とする半導体装置の実装構造。
1. A semiconductor element, a glass wiring board having a connecting portion at a position facing an electrode of the semiconductor element, and a fixing adhesive. The active surface of the semiconductor element and the glass wiring board are formed by the semiconductor. A fixing adhesive is sandwiched between the active surface of the element and the glass wiring board, and the elements are arranged to face each other.
In a semiconductor device for electrically connecting an electrode of the semiconductor element and a connecting portion of the glass wiring board, a glass wiring board is provided within a semiconductor element disposition range of the glass wiring board facing the active surface of the semiconductor element. A mounting structure for a semiconductor device, wherein a through hole penetrating the front surface and the back surface of the semiconductor device is arranged.
【請求項2】半導体素子と、前記半導体素子の電極と対
向する位置に接続部を有するガラス配線基板とを、前記
半導体素子の能動面と前記ガラス配線基板とを対向して
配置し、該半導体素子の電極とガラス配線基板の接続部
とを、電気的に接続をする半導体装置に於て、前記半導
体素子の能動面、もしくは前記ガラス配線基板の半導体
素子配置範囲内にガラス配線基板の表面と裏面を貫通す
る貫通穴を有する半導体素子配置範囲を含む範囲に、光
硬化性接着剤を塗布する工程と、ガラス配線基板の接続
部と、半導体素子の電極とを整合しガラス配線基板上に
半導体素子を載置する工程と、半導体素子裏面側よりガ
ラス配線基板を露光する工程と、半導体素子裏面より接
続部を加圧しかつガラス配線基板裏面側より半導体素子
配置範囲を含む範囲を露光する工程とからなることを特
徴とする半導体装置の実装方法。
2. A semiconductor element and a glass wiring board having a connecting portion at a position facing an electrode of the semiconductor element are arranged such that an active surface of the semiconductor element and the glass wiring board face each other. In the semiconductor device for electrically connecting the electrode of the element and the connection portion of the glass wiring board, the active surface of the semiconductor element or the surface of the glass wiring board within the semiconductor element arrangement range of the glass wiring board. A step of applying a photo-curable adhesive to a range including a semiconductor element arrangement range having a through hole penetrating the back surface, aligning the connection portion of the glass wiring board and the electrode of the semiconductor element, and forming a semiconductor on the glass wiring board. A step of placing the element, a step of exposing the glass wiring board from the back side of the semiconductor element, a pressure of the connecting portion from the back side of the semiconductor element, and a range including the semiconductor element placement range from the back side of the glass wiring board. Mounting method of a semiconductor device characterized by comprising a step of exposing.
JP3260072A 1991-10-08 1991-10-08 Mounting structure of semiconductor device and mounting method of semiconductor device Pending JPH05102343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3260072A JPH05102343A (en) 1991-10-08 1991-10-08 Mounting structure of semiconductor device and mounting method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3260072A JPH05102343A (en) 1991-10-08 1991-10-08 Mounting structure of semiconductor device and mounting method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05102343A true JPH05102343A (en) 1993-04-23

Family

ID=17342917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3260072A Pending JPH05102343A (en) 1991-10-08 1991-10-08 Mounting structure of semiconductor device and mounting method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05102343A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274389B1 (en) 1997-01-17 2001-08-14 Loctite (R&D) Ltd. Mounting structure and mounting process from semiconductor devices
US6316528B1 (en) 1997-01-17 2001-11-13 Loctite (R&D) Limited Thermosetting resin compositions
US6572980B1 (en) 2001-08-13 2003-06-03 Henkel Loctite Corporation Reworkable thermosetting resin compositions
US6605355B1 (en) 1999-02-18 2003-08-12 Three Bond Co., Ltd. Epoxy resin composition
US7012120B2 (en) 2000-03-31 2006-03-14 Henkel Corporation Reworkable compositions of oxirane(s) or thirane(s)-containing resin and curing agent
US7108920B1 (en) 2000-09-15 2006-09-19 Henkel Corporation Reworkable compositions incorporating episulfide resins
US8053587B2 (en) 2000-03-31 2011-11-08 Henkel Corporation Reworkable thermosetting resin composition
JP2021051167A (en) * 2019-09-24 2021-04-01 株式会社ジャパンディスプレイ Repair method for display device
WO2023195175A1 (en) * 2022-04-08 2023-10-12 株式会社Fuji Electrical circuit formation method and electrical circuit formation device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274389B1 (en) 1997-01-17 2001-08-14 Loctite (R&D) Ltd. Mounting structure and mounting process from semiconductor devices
US6316528B1 (en) 1997-01-17 2001-11-13 Loctite (R&D) Limited Thermosetting resin compositions
US6605355B1 (en) 1999-02-18 2003-08-12 Three Bond Co., Ltd. Epoxy resin composition
US7012120B2 (en) 2000-03-31 2006-03-14 Henkel Corporation Reworkable compositions of oxirane(s) or thirane(s)-containing resin and curing agent
US8053587B2 (en) 2000-03-31 2011-11-08 Henkel Corporation Reworkable thermosetting resin composition
US7108920B1 (en) 2000-09-15 2006-09-19 Henkel Corporation Reworkable compositions incorporating episulfide resins
US6572980B1 (en) 2001-08-13 2003-06-03 Henkel Loctite Corporation Reworkable thermosetting resin compositions
JP2021051167A (en) * 2019-09-24 2021-04-01 株式会社ジャパンディスプレイ Repair method for display device
WO2023195175A1 (en) * 2022-04-08 2023-10-12 株式会社Fuji Electrical circuit formation method and electrical circuit formation device

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