JP2827565B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2827565B2 JP2827565B2 JP9201491A JP9201491A JP2827565B2 JP 2827565 B2 JP2827565 B2 JP 2827565B2 JP 9201491 A JP9201491 A JP 9201491A JP 9201491 A JP9201491 A JP 9201491A JP 2827565 B2 JP2827565 B2 JP 2827565B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- chip
- wiring board
- insulating resin
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83871—Visible light curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/799—Apparatus for disconnecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はワークステーションやコ
ンピュータなどに用いるマルチチップモジュールの実装
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a multi-chip module used in a workstation or a computer.
【０００２】[0002]
【従来の技術】近年、ワークステーションやコンピュー
タに対する小型化の要求は益々強くなっている。これら
の要求に対処するためＬＳＩの実装においてはＬＳＩチ
ップを直接実装するマルチチップモジュールの開発が盛
んに行なわれている。マルチチップモジュールでは複数
のＬＳＩチップを同一の基板に搭載するため不良チップ
の交換技術が非常に重要になってきている。2. Description of the Related Art In recent years, there is an increasing demand for miniaturization of workstations and computers. In order to meet these demands, in the implementation of LSIs, multi-chip modules for directly mounting LSI chips have been actively developed. In a multi-chip module, since a plurality of LSI chips are mounted on the same substrate, a technique for replacing defective chips has become very important.
【０００３】以下図面を参照しながら、上記した従来の
マルチチップモジュールの不良チップの交換方法の一例
について説明する。An example of a method for replacing a defective chip of the above-mentioned conventional multi-chip module will be described below with reference to the drawings.
【０００４】（図２）は従来のマルチチップモジュール
の実装方法及び不良チップの除去方法の工程別断面図を
示すものである。（図２）において、３１は配線基板、
３２は導体配線、３３は光硬化性絶縁樹脂、３４、３８
はＬＳＩチップ、３５はバンプ、３６は加圧ツール、３
７は光照射、３９は不良チップ除去冶具、４０はせん断
力である。FIG. 2 is a cross-sectional view of a conventional method for mounting a multi-chip module and a method for removing a defective chip. In FIG. 2, 31 is a wiring board,
32 is a conductor wiring, 33 is a photocurable insulating resin, 34 and 38
Is an LSI chip, 35 is a bump, 36 is a pressure tool, 3
Reference numeral 7 denotes light irradiation, reference numeral 39 denotes a defective chip removing jig, and reference numeral 40 denotes a shearing force.
【０００５】以上のように構成された従来例について工
程別に説明する。まず図２ａに示すように配線基板３１
の導体配線３２ように光硬化性絶縁樹脂３３を塗布す
る。その後図２bに示すようにＬＳＩチップ３４のバン
プ３５と導体配線３２を一致させて配線基板３１に設置
した後、加圧冶具３６にてＬＳＩチップ３４を加圧す
る。このとき、導体配線３２とＬＳＩチップ３４のバン
プ３５は接触する。その後ＬＳＩチップ３４の側面より
光ｌを照射し、ＬＳＩチップ３４の側面の光硬化性絶縁
ん樹脂及びバンプ３５の周辺の樹脂を硬化する。その
後、加圧冶具３６を解除した後未硬化部の光硬化性絶縁
樹脂３３を常温硬化あるいは加熱硬化により硬化する
（図２ｃ）。以下同様の方法で複数のＬＳＩチップたと
えばチップ３８を実装し図２ｄに示すようなマルチチッ
プモジュールを得る。その後マルチチップモジュールの
動作試験を行なう。このときチップ３８の不良が判明し
たとき図２d,eに示すように不良チップ３８に加熱した
せん断冶具３９を用いてせん断力を印加し、チップ３８
を取り外す。A conventional example having the above-described configuration will be described step by step. First, as shown in FIG.
A photocurable insulating resin 33 is applied like the conductor wiring 32 of FIG. After that, as shown in FIG. 2B, the bumps 35 of the LSI chip 34 and the conductor wirings 32 are aligned and set on the wiring board 31, and then the LSI chip 34 is pressed by a pressing jig 36. At this time, the conductor wiring 32 and the bump 35 of the LSI chip 34 come into contact with each other. Thereafter, light 1 is irradiated from the side surface of the LSI chip 34 to cure the photocurable insulating resin on the side surface of the LSI chip 34 and the resin around the bump 35. Thereafter, after the pressing jig 36 is released, the uncured portion of the photocurable insulating resin 33 is cured by room temperature curing or heat curing (FIG. 2C). Hereinafter, a plurality of LSI chips such as a chip 38 are mounted in the same manner to obtain a multi-chip module as shown in FIG. 2D. Thereafter, an operation test of the multichip module is performed. At this time, when it is determined that the chip 38 is defective, a shearing force is applied to the defective chip 38 using a heated shear jig 39 as shown in FIGS.
Remove.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら上記のよ
うな方法では、不良チップを取り外す方法としてＬＳＩ
チップと配線基板の間にある光硬化性絶縁樹脂３３全て
を硬化した後に行なうため、ＬＳＩチップ３８の面積が
大きい場合にＬＳＩチップ３８の接着力が非常に大きく
なり不良チップの取り外しが出来なくなる。したがっ
て、マルチチップモジュールの歩留まりが非常に低いと
いう問題点を有していた。また樹脂３３の未硬化部の硬
化に加熱硬化を用いた場合は、不良チップの交換交換取
り外し後新たに実装したチップを樹脂の加熱硬化のため
に周辺の良品チップは加熱処理を何回も受けることにな
り、光硬化性絶縁樹脂の特性が変化し信頼性の低いもの
であった。However, in the above-described method, an LSI is used as a method for removing a defective chip.
Since this is performed after the entire photocurable insulating resin 33 between the chip and the wiring board is cured, when the area of the LSI chip 38 is large, the adhesive force of the LSI chip 38 becomes extremely large, and the defective chip cannot be removed. Therefore, there is a problem that the yield of the multi-chip module is very low. When heat curing is used to cure the uncured portion of the resin 33, a non-defective chip is exchanged, removed, and a newly mounted chip is subjected to heat treatment many times in order to heat and cure the resin. As a result, the characteristics of the photocurable insulating resin changed and the reliability was low.
【０００７】本発明は上記問題点に鑑み、マルチチップ
モジュールの不良チップ取り外しをの容易に行える方法
を提供するものである。The present invention has been made in view of the above problems, and provides a method for easily removing a defective chip from a multichip module.
【０００８】[0008]
【課題を解決するための手段】上記問題点を解決するた
めに本発明のマルチチップモジュールの不良チップの取
り外し方法は、配線基板もしくは、半導体素子の表面に
未硬化時の体積抵抗が１００メガオーム以上である光硬
化性絶縁樹脂を塗布する工程、配線基板の導体配線に半
導体素子の電極を一致させ前記半導体素子を前記光硬化
性樹脂を介して前記配線基板に設置する工程、前記半導
体素子を加圧し前記半導体素子を前記配線基板に押し当
て前記半導体素子の電極を前記配線基板の導体配線に接
触させる工程、前記半導体素子を加圧した状態で前記半
導体素子の側面に光を照射し前記半導体素子電極部を含
む周辺の前記光硬化性絶縁樹脂を硬化し前記半導体素子
を前記配線基板に固着するとともに前記半導体素子の電
極と前記配線基板の電極を接触により電気的に接続する
工程、前記半導体素子の動作試験を行なった後前記光硬
化性樹脂の未硬化部を硬化する工程を備えたものであ
る。According to the present invention, there is provided a method for removing a defective chip of a multi-chip module according to the present invention, wherein the uncured volume resistance of a wiring board or a semiconductor element is 100 Mohm or more. A step of applying a photocurable insulating resin, a step of aligning the electrodes of the semiconductor element with the conductor wiring of the wiring board, and installing the semiconductor element on the wiring board via the photocurable resin; Pressing the semiconductor element against the wiring board to bring the electrode of the semiconductor element into contact with the conductor wiring of the wiring board; and irradiating light to a side surface of the semiconductor element while the semiconductor element is being pressed. The semiconductor device is fixed to the wiring board by curing the photocurable insulating resin around the area including the electrode portion, and the electrodes of the semiconductor element and the wiring board are fixed. A step of electrically connecting the contact electrode, those having a curing the uncured portions of the photocurable resin after performing the operation test of the semiconductor device.
【０００９】[0009]
【作用】本発明は上記した構成によって、不良チップの
取り外しはＬＳＩチップと配線基板の間にある光硬化性
絶縁樹脂の半分以上が未硬化の状態で行なうため、面積
の大きいＬＳＩチップでも容易に取り外すことが出来
る。According to the present invention, a defective chip is removed in a state where at least half of the photo-curable insulating resin between the LSI chip and the wiring board is uncured by the above-described structure. Can be removed.
【００１０】[0010]
【実施例】以下本発明の一実施例のマルチチップモジュ
ールの不良チップの取り外し方法について図面を参照し
ながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for removing a defective chip of a multi-chip module according to one embodiment of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の実施例における不良チップ
の取り外し方法の工程別断面図を示すものである。図１
において、１は配線基板、２は導体配線、３は光硬化性
絶縁樹脂、４,１０，１５は半導体素子であるＬＳＩチ
ップ、５,１１，１６はバンプ、６は加圧ツール、７は
光照射、８,１３，１７は硬化後の光硬化性樹脂、３,１
２は未硬化の光硬化性絶縁樹脂、９は取り外し冶具、１
４はせん断力を示すものである。FIG. 1 is a sectional view showing a method of removing a defective chip according to an embodiment of the present invention. FIG.
1, 1 is a wiring board, 2 is a conductor wiring, 3 is a photocurable insulating resin, 4, 10, and 15 are LSI chips as semiconductor elements, 5, 11, and 16 are bumps, 6 is a pressure tool, and 7 is light Irradiation, 8,13,17 are photocurable resin after curing, 3,1
2 is an uncured photocurable insulating resin, 9 is a removal jig, 1
Reference numeral 4 denotes a shear force.
【００１２】以下本発明の実施例について図面を参照し
ながら説明する。まず図１aに示すように、配線基板１
の後にＬＳＩチップを搭載する領域に光硬化性絶縁樹脂
３を塗布する。配線基板１はセラミック基板、シリコン
基板などである。光硬化性絶縁樹脂３はアクリル、エポ
キシ、シリコーン、ポリイミドなどであり、未硬化時の
体積抵抗が１００メガオーム以上のものを用いる。また
光硬化性絶縁樹脂の粘度は１０００から３０００cps程
度である。次に図１bに示すようにＬＳＩチップ４の電
極であるバンプ５と配線基板の導体配線を位置合わせし
ＬＳＩチップ４を配線基板１に設置する。バンプ５は、
金、銅、はんだ等でありその厚みは５から５０μｍ程度
である。その後加圧ツール６にてＬＳＩチップ４を加圧
する。このとき導体配線２とバンプの間にある光硬化性
絶縁樹脂３は周囲に押し出され導体配線２とバンプ５は
接触する。次にＬＳＩチップ４を加圧した状態でＬＳＩ
チップの側面より光照射７を行ないＬＳＩチップの側面
の光硬化性絶縁樹脂及びバンプ５の周辺部のみの樹脂を
硬化した光硬化性絶縁樹脂８を得る。このとき光照射７
の照射エネルギーをコントロールすることにより光硬化
性絶縁樹脂３の硬化領域を容易に制御することが出来
る。An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG.
After that, the photocurable insulating resin 3 is applied to a region where the LSI chip is mounted. The wiring substrate 1 is a ceramic substrate, a silicon substrate, or the like. The photocurable insulating resin 3 is made of acrylic, epoxy, silicone, polyimide, or the like, and has a volume resistance of 100 Mohm or more when uncured. The viscosity of the photocurable insulating resin is about 1000 to 3000 cps. Next, as shown in FIG. 1B, the bumps 5 serving as the electrodes of the LSI chip 4 are aligned with the conductor wiring of the wiring board, and the LSI chip 4 is mounted on the wiring board 1. Bump 5
Gold, copper, solder, etc., whose thickness is about 5 to 50 μm. Thereafter, the LSI chip 4 is pressed by the pressing tool 6. At this time, the photocurable insulating resin 3 between the conductor wiring 2 and the bump is pushed out to the periphery, and the conductor wiring 2 and the bump 5 come into contact. Next, while the LSI chip 4 is pressed, the LSI
The resin of only the peripheral portion of the photocurable insulating resin and the bumps 5 of the LSI chip side surface of the perform light irradiation 7 from the side surface of the chip
Obtaining a photocurable insulating resin 8 ized hard. At this time, light irradiation 7
By controlling the irradiation energy, the cured region of the photocurable insulating resin 3 can be easily controlled.
【００１３】次に図１Cに示すように加圧ツール６を解
除してＬＳＩチップ４を配線基板１に固着するとともに
ＬＳＩチップ４のバンプ５と配線基板１の導体配線２を
電気的に接続する。このときＬＳＩチップ４の中央にあ
る光硬化性絶縁樹脂３は未硬化状態であるが、バンプ５
周辺は硬化しているためＬＳＩチップ４と配線基板１の
間には十分な収縮力が作用し完全な接続を得ることが出
来る。次に図１dに示すように同様の方法でＬＳＩチッ
プ１０を実装し、複数のＬＳＩチップの実装されたマル
チチップモジュールを得た後、次にマルチチップモジュ
ールの特性検査を行ない不良の場合は不良ＬＳＩチップ
の特定を行なう。このときＬＳＩチップ４，１０の中央
部にある光硬化性樹脂３，１２は、未硬化であるが未硬
化時の体積抵抗が１００メガオーム以上と絶縁性が非常
に高いため、特性検査への影響はまったく無い。次にた
とえばＬＳＩチップ１０が不良と判明したとき、不良Ｌ
ＳＩチップ１０の側面に取り外し冶具９を押し当てせん
断力１４を印加して配線基板１より取り外す。このとき
ＬＳＩチップ１０は、チップの周辺でしか固定されてい
ないため大面積のＬＳＩチップでも非常に小さいせん断
力１４で容易に取り外すことができる。またこのときＬ
ＳＩチップ１０を加熱することにより更に小さいせん断
力でＬＳＩチップ１０を取り外すことが出来る。ＬＳＩ
チップ１０を除去した後の配線基板１の表面は有機溶剤
などでクリーニングする。Next, as shown in FIG. 1C, the pressing tool 6 is released to fix the LSI chip 4 to the wiring board 1, and the bumps 5 of the LSI chip 4 are electrically connected to the conductor wiring 2 of the wiring board 1. . At this time, the photocurable insulating resin 3 at the center of the LSI chip 4 is in an uncured state,
Since the periphery is hardened, a sufficient contraction force acts between the LSI chip 4 and the wiring board 1, and complete connection can be obtained. Next, as shown in FIG. 1d, the LSI chip 10 is mounted by the same method, and a multichip module on which a plurality of LSI chips are mounted is obtained. The LSI chip is specified. At this time, the photocurable resins 3 and 12 at the center of the LSI chips 4 and 10 are uncured, but have an extremely high volume resistivity of 100 Mohm or more when uncured, and have an extremely high insulating property, which may affect the characteristic inspection. Is not at all. Next, for example, when the LSI chip 10 is found to be defective,
The detachment jig 9 is pressed against the side surface of the SI chip 10 and a shearing force 14 is applied to detach it from the wiring board 1. At this time, since the LSI chip 10 is fixed only at the periphery of the chip, even a large-area LSI chip can be easily removed with a very small shearing force 14. At this time, L
By heating the SI chip 10, the LSI chip 10 can be removed with a smaller shear force. LSI
After removing the chip 10, the surface of the wiring board 1 is cleaned with an organic solvent or the like.
【００１４】次に図１fに示すようにチップ１０の代わ
りに再度ＬＳＩチップ１５を同様の方法で配線基板１上
に固着しモジュールの特性検査を行ない、その結果モジ
ュールが良品であればにＬＳＩチップの中央部にある未
硬化の光硬化性樹脂を硬化する。硬化の方法は加熱硬化
あるいはＬＳＩチップの側面よりの光照射による。８，
１７は硬化後の絶縁樹脂である。また同様の不良チップ
交換方法をマルチチップモジュールのスクーリーニング
試験後に行うことも可能である。Next, as shown in FIG. 1f, instead of the chip 10, the LSI chip 15 is fixed on the wiring board 1 again by the same method, and the characteristics of the module are inspected. The uncured photo-curable resin in the center of is cured. The curing method is heat curing or light irradiation from the side of the LSI chip. 8,
Reference numeral 17 denotes a cured insulating resin. A similar defective chip replacement method can be performed after a screening test of a multichip module.
【００１５】[0015]
【発明の効果】以上のように本発明は、ＬＳＩチップと
配線基板の接続をＬＳＩチップの周辺部の光硬化性絶縁
樹脂を硬化させることにより行い、動作試験を行った後
全領域の樹脂を硬化させる方法であるため、動作試験に
おいて、不良チップが発生しても光硬化性絶縁樹脂は、
ＬＳＩチップの周辺しか硬化していないため接着強度が
弱く容易に取り外すことが出来、 歩留まりの高いマル
チチップモジュールを得ることが出来る。As described above, according to the present invention, the connection between the LSI chip and the wiring board is performed by curing the photo-curable insulating resin in the peripheral portion of the LSI chip, and after performing an operation test, the resin in the entire area is removed. Because it is a method of curing, even if a defective chip occurs in the operation test, the photocurable insulating resin is
Since only the periphery of the LSI chip is hardened, the adhesive strength is weak and the chip can be easily removed, so that a multi-chip module with a high yield can be obtained.
【図１】本発明の一実施例における工程別断面図であ
る。FIG. 1 is a sectional view of each process in an embodiment of the present invention.
【図２】従来の工程別断面図である。FIG. 2 is a sectional view of a conventional process.
１ 配線基板 ２ 導体配線 ３、１２ 未硬化の光硬化性絶縁樹脂 ４、１０、１５ ＬＳＩチップ ５、１１、１６ バンプ ６ 加圧ツール ７ 光照射 ８、１３、１７ 硬化後の光硬化性絶縁樹脂 ９ 取り外し治具 １４ せんだん力 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Conductor wiring 3, 12 Uncured photocurable insulating resin 4, 10, 15 LSI chip 5, 11, 16 Bump 6 Press tool 7 Light irradiation 8, 13, 17 Photocurable insulating resin after curing 9 Removal jig 14 Sendan power
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−290936（ＪＰ，Ａ) 特開 平３−129843（ＪＰ，Ａ) 特開 昭63−240036（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 321 H01L 21/60 311 H01L 25/00──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-290936 (JP, A) JP-A-3-129843 (JP, A) JP-A-63-240036 (JP, A) (58) Investigation Field (Int.Cl. 6 , DB name) H01L 21/60 321 H01L 21/60 311 H01L 25/00
Claims (1)
未硬化時の体積抵抗が１００メガオーム以上である光硬
化性絶縁樹脂を塗布する工程、前記配線基板の導体配線
に前記半導体素子の電極を一致させ前記半導体素子を前
記光硬化性絶縁樹脂を介して前記配線基板に設置する工
程、前記半導体素子を加圧し前記半導体素子を前記配線
基板に押し当て前記半導体素子の電極を前記配線基板の
導体配線に接触させる工程、前記半導体素子を加圧した
状態で前記半導体素子の側面に光を照射し前記半導体素
子の側面の光硬化性絶縁樹脂と前記半導体素子の電極の
周辺部との半導体素子の周辺部のみの光硬化性絶縁樹脂
を硬化し前記半導体素子を前記配線基板に固着するとと
もに前記半導体素子の電極と前記配線基板の導体配線と
を接触により電気的に接続する工程、前記半導体素子の
動作試験を行ない不良素子の交換を行った後前記光硬化
性絶縁樹脂の未硬化部を硬化する工程を備えたことを特
徴とする半導体装置の製造方法。1. The method according to claim 1, wherein:
A step of applying a photocurable insulating resin having an uncured volume resistance of 100 Mohm or more, matching the electrodes of the semiconductor element to the conductor wiring of the wiring board, and allowing the semiconductor element to pass through the photocurable insulating resin. A step of placing the semiconductor element on the wiring board, a step of pressing the semiconductor element and pressing the semiconductor element against the wiring board to bring the electrodes of the semiconductor element into contact with the conductor wiring of the wiring board, and Irradiating light to the side surface of the semiconductor element , the photocurable insulating resin on the side surface of the semiconductor element and the electrode of the semiconductor element
By hardening the photocurable insulating resin only at the peripheral portion of the semiconductor element and the peripheral portion of the semiconductor element and fixing the semiconductor element to the wiring board, the electrodes of the semiconductor element and the conductor wiring of the wiring board are brought into contact with each other by contact. A method of manufacturing a semiconductor device, comprising: a step of electrically connecting; a step of performing an operation test of the semiconductor element; replacing a defective element ; and then curing an uncured portion of the photocurable insulating resin. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201491A JP2827565B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201491A JP2827565B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04322439A JPH04322439A (en) | 1992-11-12 |
| JP2827565B2 true JP2827565B2 (en) | 1998-11-25 |
Family
ID=14042657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9201491A Expired - Fee Related JP2827565B2 (en) | 1991-04-23 | 1991-04-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2827565B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251695B1 (en) | 1999-09-01 | 2001-06-26 | S3 Graphics Co., Ltd. | Multichip module packaging process for known good die burn-in |
| WO2007058142A1 (en) * | 2005-11-21 | 2007-05-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing circuit board having electronic part |
-
1991
- 1991-04-23 JP JP9201491A patent/JP2827565B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04322439A (en) | 1992-11-12 |
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