JPH07231020A - Manufacture of semiconductor chip with area pad - Google Patents

Abstract

PURPOSE:To obtain a semiconductor chip with which a burn-in test can be readily conducted by laminating and arranging a prepreg layer on a wiring board, positioning and arranging a semiconductor wafer on it thereby forming a compound material and then cutting and separating it. CONSTITUTION:Connecting bumps 6a in a group are provided on one principal plane and area pads 6b in a group are provided on other principal plane of the principal plane of a wiring board 6 respectively, and a prepreg layer 7 is laminated and arranged on the principal plane. Next, projected bonding pads 5a in each element region possessed by a semiconductor wafer 5 and the connecting bumps 6a of the wiring board 6 are respectively corresponded on the prepreg layer 7, and the semiconductor wafer 5 is positioned and arranged. Thereafter, the semiconductor wafer 5 arranged on the prepreg layer 7 and the wiring board 6 are bonded together under pressure, the projected bonding pads 5a of the semiconductor wafer 5 are corresponded to the connecting bumps 6a of the corresponding wiring board 6, in this bonding state, the prepreg layer 7 is hardened, and a compound material 8 is formed. This is then cut and separated to obtain a semiconductor chip for which a burn-in test can be performed easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor chip with an area pad, and more particularly to a method of mass-producing a thin semiconductor chip with an area pad suitable for the structure of a mounting circuit device.

[0002]

2. Description of the Related Art A mounting circuit device has been developed and put to practical use for the purpose of downsizing electronic devices and improving their performance. For example, a mounting circuit device having a structure in which a semiconductor chip (for example, an IC chip), a chip type resistor, a chip capacitor, etc. are mounted and mounted on the surface of a multilayer wiring board is being put into practical use. Then, this type of mounted circuit device, for example, a multi-chip module (MCM: mu
In the configuration of the (lti chip module), it is difficult to sufficiently evaluate the characteristics of the mounted semiconductor chip in advance. That is, it is practically impossible to carry out a burn-in test or the like on each semiconductor chip prior to mounting or mounting the semiconductor chip, since it involves a complicated operation. Therefore, after mounting on the surface of the wiring board, the mounting circuit device as a whole is tested and evaluated, and the semiconductor chip is also evaluated. If the circuit function as designed is not obtained as a result of the test and evaluation of the mounted circuit device as a whole, the mounted semiconductor chip is considered to be defective or unsuitable, and is attached / detached / replaced.

In mounting the semiconductor chip, the semiconductor chip is previously mounted on a carrier tape having required lead terminals, and the semiconductor chip is punched out from the carrier tape in each semiconductor chip area and mounted on the wiring board surface. (TAB: Tape Auotmated Bounding: Law) Means are also known. However, in the case of this TAB method, the manufacturing cost of the carrier tape is relatively high, and a dedicated die and bonding tool are required in accordance with the package size in the mounting process, so the assembly cost is relatively high. It becomes expensive and economically problematic as a practical means.

[0004]

By the way, in the case of flip-chip mounting, as described above, the so-called burn-in test, which detects a defect even if it appears in the near future, cannot be performed on the semiconductor chip itself to be mounted. Therefore, there is a possibility of causing trouble at the initial stage of practical use after mounting and modularization, and it can be said that there is a problem in terms of reliability. Although it is possible to deal with this reliability problem by means of attachment / detachment or replacement of the mounted semiconductor chips, that is, repair or rework, as a result, the assembly cost will be further increased. Then, in the present situation where the semiconductor chip used for the configuration of the mounting circuit has a high capacity and a narrow pitch pad, it poses a serious problem.

From this point of view, in the case of the TAB mounting method or the like, a so-called burn-in test is easy to perform, which is advantageous for ensuring reliability, but in terms of compactness, in the case of the flip chip mounting. Compared to
A large mounting area is required, which hinders compactness.
Moreover, as shown in FIG.
When the semiconductor chip 2 mounted and mounted on the IC chip is used as a packaged module by using a resin mold 3 or the like, it is advantageous in terms of ensuring reliability. Since the size is large, compactness is impaired. In FIG. 5, 1a is a ball grid array (terminal electrode) led out to the back surface side of the wiring board 1, and 4 is a part of an electrical connection portion between the electrode terminals of the semiconductor chip 2 and the ball grid array 1a. Bonding wire. The present invention has been made in response to the above circumstances and can be easily applied to a burn-in test or the like, so that the reliability can be guaranteed, and
It is an object of the present invention to provide a method capable of manufacturing a semiconductor chip with an area pad that functions as a compact semiconductor chip at low cost and high yield.

[0006]

A first method of manufacturing a semiconductor chip with area pads according to the present invention has outer dimensions substantially the same as those of a semiconductor wafer to be mounted and arranged, and a connecting bump group on one main surface, Stacking and arranging a prepreg layer on one main surface of the wiring board having area pad groups respectively connected to the connection bump group on the other main surface; connecting bumps of the wiring board on the prepreg layer; The step of aligning and arranging the semiconductor wafer by associating the protruding bonding pads of the respective element regions of the semiconductor wafer with each other, and pressing the arranged semiconductor wafer and the wiring board to correspond the protruding bonding pads of the semiconductor wafer. A step of bringing the prepreg layer into contact with the connection bumps of the wiring board, and curing the prepreg layer to form an integrated composite; Cut along the outside shape, characterized by comprising; and a step of separating.

A second method for manufacturing a semiconductor chip with area pads according to the present invention has outer dimensions which are substantially the same as those of a semiconductor wafer to be mounted and arranged, and has a connection bump group on one main surface and the connection bumps on the other main surface. A step of laminating and disposing a thermoplastic resin layer on one main surface of a wiring board on which area pad groups for connection corresponding to the bump groups are respectively provided, and connection bumps of the wiring board and a semiconductor wafer on the thermoplastic resin layer The semiconductor wafers are aligned and arranged so as to correspond to the protruding bonding pads of each element region of the semiconductor device, and the semiconductor resin is pressure-bonded in a plasticized state of the thermoplastic resin layer or in a state of a glass transition temperature or higher. The protruding bonding pads on the wafer are brought into contact with the corresponding connection bumps on the wiring board,
And a step of solidifying the thermoplastic resin layer to form a composite body in which a semiconductor wafer and a wiring board are integrated, and a step of cutting and separating the composite body along the outer shape of each element region of the semiconductor wafer. Is characterized by. Further, the third method for manufacturing a semiconductor chip with area pad according to the present invention is
One of the wiring boards whose external dimensions are substantially the same as those of the semiconductor wafer to be mounted and arranged, and in which one main surface is provided with connection bump groups and the other main surface is provided with area pad groups to be connected corresponding to the connection bump groups. Positioning the semiconductor wafer by stacking and arranging a UV-curable prepreg layer on the main surface, and connecting bumps of the wiring board and projecting bonding pads of each element region of the semiconductor wafer to each other on the prepreg layer. The step of aligning and arranging, the above-mentioned semiconductor chip and the wiring board are pressure-bonded, the protruding bonding pads of the semiconductor wafer are brought into contact with the connection bumps of the corresponding wiring board, and ultraviolet rays are irradiated to cure the prepreg layer. A step of forming an integrated composite body, and a step of cutting and separating the composite body along the outer shape of each element region of a semiconductor wafer. And it features.

According to the present invention, (a) a semiconductor wafer having an element region divided into a plurality of semiconductor chips at the final stage and a corresponding connection bump group are connected on one main surface in correspondence with the connection bump group. Area pad group is combined with a wiring board provided on the other main surface, and (b) the combined composite is separated into element regions to form a semiconductor chip with area pads. The main point is that each element region can be simultaneously subjected to a burn-in test or the like (a connection K test with a wiring board is also possible) prior to the semiconductor chip formation.

In the present invention, as the wiring board, for example, a resin plate system, a ceramic plate system, a glass plate system or the like having a thickness of about 0.2 to 0.5 mm is used. Here, as the resin plate type wiring board, for example, polyimide resin film type, glass cloth-epoxy resin type, etc., and as the ceramic plate type wiring board, for example, alumina,
Examples of the insulating material include aluminum nitride and silicon nitride. Then, a UV-curable prepreg layer is laminated,
When arranging, if a transparent glass plate type wiring board is used, it is possible to irradiate ultraviolet rays from the back surface side.

In the present invention, the resin layer interposed between the wiring board surface and the semiconductor wafer is, for example, a prepreg layer, a thermoplastic resin layer, or an ultraviolet-curable prepreg layer exhibiting insulating properties and a joint-integrating function. . here,
Examples of the prepreg layer to be used include epoxy resin prepregs and glass-epoxy resin type prepregs, and examples of the thermoplastic resin layer include polyetherimide resin film, polyether sulfone resin film and polyether phenyl resin film. Examples thereof include an yl resin film and an ultraviolet-curable prepreg. The thickness of these resin layers may be such as to satisfy the above-mentioned insulating property, the function of joining and unifying, etc., and is generally about 50 to 100 μm.

Further, in the present invention, the bonding pad in each element region of the semiconductor wafer is not particularly limited in the shape of the protruding bonding pad, but in the case of, for example, a conical shape or a pyramidal shape, it easily penetrates the resin layer. Preferably, the protruding bonding pad can be formed by plating or the like, or a conductive composition.

[0012]

According to the method of manufacturing a semiconductor chip of the present invention, a required test can be easily performed before the semiconductor chip is individually divided and separated from the semiconductor wafer. In other words, in a normal semiconductor chip manufacturing process, after a required semiconductor element (element region) is formed, those element regions are kept in one piece and are mechanically and electrically reinforced by a wiring board. Since it is adopted, it is easy to handle in the manufacturing process, testing, and evaluation. Moreover, each of the semiconductor chip forming regions is provided with a corresponding area pad group on a certain surface side, and since the area pads can be set to be relatively large, a burn-in test required for each semiconductor chip forming region is performed. It becomes possible to carry out a test including, and at this stage, each semiconductor chip can be guaranteed and selected. Here, the fact that the semiconductor chip can be guaranteed prior to mounting means that it is possible to avoid the work of attaching and detaching the semiconductor chip, the work of replacing the semiconductor chip after the assembled circuit device is assembled and tested. It can be said that it will greatly contribute to cost reduction. In addition, the semiconductor chip with the area pad has a slightly thicker thickness, but its outer shape and dimensions are the same as those of the semiconductor chip body, and since it is compact, it is easy to use and has a good manufacturing yield. Combined with the above, it can be said to bring many advantages.

[0013]

Embodiments of the present invention will be described below with reference to FIGS.

1 to 3 are sectional views schematically showing an embodiment of a method of manufacturing a semiconductor chip with an area pad according to the present invention in the order of steps.

First, as shown in FIG. 1, the external dimensions are substantially the same as those of the semiconductor wafer 5 to be mounted and arranged, and the connection bumps 6a are arranged on one main surface and the connection bumps 6a are formed on the other main surface. The prepreg layer 7 is laminated and arranged on one main surface of the wiring board 6 on which the area pads 6b to be connected are respectively provided.
Here, the wiring board 6 is a disk-shaped ceramic wiring board having the same outer shape as the semiconductor wafer 5, for example, a diameter of 15 cm and a thickness of about 0.5 mm. Then, on one main surface of the ceramic wiring board 6, the connection bumps 6a having a diameter of 80 μm are 150 μm.
Area pads of 0.5 × 0.5 mm, which are provided all over with a pitch of about 4 mm, and which correspond to the connection bumps 6a group and which are electrically connected through the ceramic wiring board 6 on the other main surface. 6b is provided all over. On the other hand, the prepreg layer 7 is, for example, a glass cloth-epoxy resin prepreg layer having a thickness of about 100 μm, and its outer shape is also a disk shape having a diameter of 15 cm.

Next, on the prepreg layer 7, the connection bumps 6a of the wiring board 6 and the protruding bonding pads 5a of each element region of the semiconductor wafer 5 are made to correspond to each other.
The semiconductor wafer 5 is aligned and arranged. Here, the semiconductor wafer 5 is, for example, a disc shape having a diameter of 15 cm and a thickness of 0.5 mm.
This is a Si wafer, and IC element regions are formed in a lattice pattern on the Si wafer 5 in a multi-chambered manner, and the IC element regions formed in the multi-chambered manner each have a required protrusion. -Shaped bonding pad 5a is
It is formed by stacking a plating layer and an Au plating layer. In FIG. 1, 5b is the protruding bonding pad.
It is a protective film (layer) that exposes the tip side of 5a and covers the surface of the Si wafer 5.

Thereafter, the semiconductor wafer 5 and the wiring board 6 arranged on the prepreg layer 7 are pressure-bonded to each other so that the protruding bonding pads 5a of the semiconductor wafer 5 are brought into contact with the corresponding connection bumps 6a of the wiring board 6. In this pressure-bonded state, the prepreg layer 7 is cured to form an integrated composite as shown in FIG. The pressing force and temperature at this time are selected and set in consideration of the properties of the prepreg layer 7, such as flexibility, fluidity, and curing temperature.

When the composite body is constructed as described above, the composite body is mounted on a test device and tested as a product. Next, the formed composite body 8 is provided with, for example, slits or grooves for bending along the outer shape of each element region of the semiconductor wafer 5, and is cut and separated based on the slits or grooves for bending. As a result, a semiconductor chip with an area pad having a structure as shown in FIG. 3 could be obtained. FIG. 4 is a plan view showing the arrangement and shape of the area pads 6b in the semiconductor chip with area pads.

The present invention is not limited to the above examples, and various modifications can be made without departing from the spirit of the invention. For example, the wiring board may be made of an aluminum nitride wiring board, a polyimide resin wiring board, or the like, instead of being made of alumina, and the aluminum nitride wiring board is particularly advantageous in terms of heat dissipation. . Further, instead of the glass cloth-epoxy resin prepreg layer, a thermoplastic resin layer such as a polyetherimide resin film or a polyether sulfone resin film, or a photocurable resin layer may be interposed. In particular, in the case of a photo-curable resin layer that is cured by ultraviolet rays, selective exposure and development processing is performed to make the connecting portion between the protruding bond pad of the semiconductor chip and the connecting bump of the wiring board fine and precise. Since it can be opened well, the connection can be made reliable.

[0020]

As can be seen from the above description, according to the method of manufacturing a semiconductor chip with an area pad of the present invention,
It is possible to easily obtain a semiconductor chip having high reliability in characteristics and functions while adopting a compact form. That is, since a semiconductor wafer from which a plurality of (many) semiconductor chips are cut out is handled in a composite structure with a wiring board having corresponding area pads, handling and operation are facilitated. Furthermore, since it is possible to provide a semiconductor chip with an area pad, it is possible to perform a chip burn-in test and a performance test with a simple jig.
Since it is possible to use a semiconductor chip whose characteristics or functions are guaranteed, it is possible to avoid attachment / detachment, replacement, etc. of the semiconductor chip of the mounted circuit device, which is often regarded as a problem in the past.
Since it is possible to use a semiconductor chip with this function guaranteed, it greatly contributes to the improvement of the manufacturing yield of the mounted circuit device and the reduction of cost, so in combination with maintaining the compactness, It can be said that it brings many advantages in practical use.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically showing a state of stacking and arranging a semiconductor wafer, a prepreg layer, and a wiring board in an embodiment of a method for manufacturing a semiconductor chip according to the present invention.

FIG. 2 is a cross-sectional view schematically showing a state in which a semiconductor wafer, a prepreg layer, and a wiring board are pressure-bonded into a composite in the embodiment example of the method for manufacturing a semiconductor chip according to the present invention.

FIG. 3 is a cross-sectional view schematically showing a state of the semiconductor chip obtained by cutting and separating from the composite in the embodiment example of the method for manufacturing a semiconductor chip according to the present invention.

FIG. 4 is a plan view showing a configuration example of an area pad forming surface of a semiconductor chip manufactured in an embodiment of the method for manufacturing a semiconductor chip according to the present invention.

FIG. 5 is a cross-sectional view showing a main part configuration of a conventional chip-on-wiring board type semiconductor package.

[Explanation of symbols]

1, 6 ... Wiring board 1a ... Ball grid array 2,
5 '... semiconductor chip 3 ... resin mold layer 4 ... bonding wire 5
… Semiconductor wafer 5a… Protrusion bonding pad
6a ... Connection bump 6b ... Area pad 7 ... Prefreg layer 8 ... Composite

Claims (3)

[Claims] 1. A semiconductor device having external dimensions substantially the same as those of a semiconductor wafer to be mounted and arranged, and a connection bump group is provided on one main surface, and an area pad group to be connected corresponding to the connection bump group is provided on the other main surface. The step of stacking and arranging the prepreg layer on one main surface of the wiring board, and the connection bumps of the wiring board and the projecting bonding pads of each element region of the semiconductor wafer on the prepreg layer are made to correspond to each other to form the semiconductor wafer. A step of aligning and arranging, and arranging the semiconductor wafer and the wiring board that have been arranged by pressure bonding, bringing the protruding bonding pads of the semiconductor wafer into contact with the connection bumps of the corresponding wiring board, and curing the prepreg layer to form an integrated composite. And a step of cutting the composite along the outer shape of each element region of the semiconductor wafer and separating the composite. Manufacturing method of semiconductor chip with pad. 2. A semiconductor device having external dimensions substantially the same as those of a semiconductor wafer to be mounted and arranged, and a connection bump group is provided on one main surface, and an area pad group to be connected corresponding to the connection bump group is provided on the other main surface. A step of laminating and arranging a thermoplastic resin layer on one main surface of the wiring board; and connecting bumps of the wiring board and projecting bonding pads of each element area of the semiconductor wafer on the thermoplastic resin layer in correspondence with each other. , Align the semiconductor wafer,
The step of arranging, press-bonding in a plasticized state of the thermoplastic resin layer, or in a state of a glass transition temperature or higher, and bring the protruding bonding pads of the semiconductor wafer into contact with the connection bumps of the corresponding wiring board. And a step of solidifying the layers to form a composite body in which a semiconductor wafer and a wiring board are integrated, and a step of cutting and separating the composite body along the outer shape of each element region of the semiconductor wafer. Method for manufacturing semiconductor chip with area pad. 3. An external pad having substantially the same external dimensions as that of a semiconductor wafer to be mounted and arranged, a connecting bump group being provided on one main surface, and an area pad group being connected corresponding to the connecting bump group on the other main surface. The step of stacking and arranging a UV-curable prepreg layer on one main surface of the wiring board, and the connection bumps of the wiring board and the protruding bonding pads of each element area of the semiconductor wafer are made to correspond to each other on the prepreg layer. Aligning and arranging the semiconductor wafer, pressure-bonding the arranged semiconductor chip and the wiring board, contacting the protruding bonding pads of the semiconductor wafer with the connection bumps of the corresponding wiring board, and irradiating ultraviolet rays. A step of curing the prepreg layer to form an integrated composite body; and a step of cutting and separating the composite body along the outer shape of each element region of the semiconductor wafer. A method for manufacturing a semiconductor chip with an area pad, comprising: