JP2002359350A - Method of manufacturing stacked circuit module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a stacked circuit module which can form an interlayer connecting electrode quickly and accurately. SOLUTION: Thick resist 10 is applied in a thickness of about 200 μm on a wiring board 2 to serve as a base, and it is exposed to an ultraviolet ray using a photomask 11 where the section corresponding to the section to form the interlayer connecting electrode 6 is patterned. An opening 10a is made in the thick resist 10 by development treatment. The interlayer connecting electrode 6 is made by performing plating treatment, thereby plating the opening 10a in the thick resist 10 with metal (copper). The height of the electrode is about 200 μm, and the diameter is tens of μm or thereabouts. After this, the thick resist 10 is removed, and a semiconductor chip is mounted. Resin is applied to cover it all over with a resin layer, and after hardening, the resin layer is thinned by grinding, and also the rear of the semiconductor chip 5 is ground to a specified thickness dimension. A bump electrode is made at the interlayer connecting electrode 6, and a resin layer is provided to cover the rear of the semiconductor chip 5. Since the interlayer connecting electrodes 6 can be made en block, the time required for manufacture can be made a fixed and short one even in the case that the number of pieces is large.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated circuit module which is formed on a wiring board or another laminated circuit module as a base.

[0002]

In recent years, electronic devices have become smaller and more sophisticated, and accordingly, there has been a demand for higher density in circuit component mounting techniques. In particular, in the mounting technology of IC chips, a method of stopping packaging of individual IC chips and mounting the chips directly on a wiring substrate, so-called flip-chip mounting, is being performed. Thus, a plurality of IC chips are mounted on a wiring board in a state of bare chips, and the whole is protected by resin or the like, so that miniaturization and high functionality are achieved.

As described above, by using the flip-chip mounting using the bare chip and the high-density laminated wiring board, the mounting size of the circuit can be reduced to about the occupied area (footprint area) of the mounted component itself. become able to. However, this means that the area must be smaller than the footprint area in order to achieve further miniaturization, and there is a limit in a planar arrangement.

Therefore, conventionally, in order to achieve high-density mounting or miniaturization, a configuration in which bare chips are stacked in a plurality of layers has been proposed. One of the proposals made by the inventors has been disclosed in, for example, JP-A-2000-183283. This is a structure in which bare chips are stacked in the stacking direction to reduce the area of the substrate, and the resin and chips are ground during the process to reduce the size in the stacking direction.

However, in the above-described structure, when the interlayer connection electrode is formed during the process, the JPS (Je
The technology uses a technique called t Printing System) to deposit metal particles. When this method is adopted, since the electrodes are formed individually, it is a good method when the number of interlayer connection electrodes to be formed is small. As a result, the entire time required for formation is increased.

In this case, there is no problem if the formation time per unit is very short, but at present, it takes about 10 seconds to form one unit. Therefore, when the number of interlayer connection electrodes formed on the order of several hundreds per one laminated circuit module is present, it takes several thousand seconds, which cannot be said to be a realistic manufacturing method. It was the situation.

[0007] In addition to the method using the JPS, when the stud bumps are formed by laminating them in multiple stages in order to form the interlayer connection electrodes, the balance becomes poor when forming the second and subsequent stud bumps. In some cases, there is a risk of collapse during the lamination process, and this is not always an appropriate method in terms of yield to adopt as a process technology.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a laminated circuit module to be formed on a wiring substrate or another laminated circuit module as a base, and particularly to an interlayer connection. The present invention relates to a method for manufacturing a laminated circuit module in which electrodes can be formed quickly and reliably.

[0009]

According to the first aspect of the present invention, when an interlayer connection electrode which is a structure of a laminated circuit module is formed on a base, a pattern forming material having a thick film is applied. Since an opening corresponding to the shape of the interlayer connection electrode is formed in the forming material and the interlayer connection electrode is formed so as to fill the opening, a large number of interlayers are provided so as to connect terminals of a semiconductor chip mounted inside. Since the connection electrodes can be formed in a lump, they can be quickly formed by one forming process regardless of the number of formed electrodes, and the openings can be filled using a pattern forming material. Since it is formed, the shape of the interlayer connection electrode can be formed with high accuracy.

According to the second aspect of the present invention, in the above invention, since a photosensitive material having a negative characteristic or a positive characteristic is used as the pattern forming material, the patterning process for forming the opening of the interlayer connection electrode is negative or negative. By preparing and exposing a positive mask, it can be easily formed.

According to the third aspect of the present invention, in the second aspect of the present invention, the pattern forming material is exposed to a light source having a shorter wavelength than visible light such as ultraviolet rays, X-rays or other radiation. In addition, it is possible to form a sharp pattern by minimizing a decrease in patterning accuracy caused by a light source transmitting through a pattern forming mask causing phenomena such as diffraction and interference.

According to the invention of claim 4, in each of the above-mentioned inventions, a material having thermosetting properties is used as the pattern forming material, so that the durability can be improved.
Even when performing a process such as grinding in which a mechanical stress is applied in a state in which the pattern forming material is formed, the process can be performed without impairing the patterned state.

According to the fifth aspect of the present invention, in each of the above-mentioned inventions, the step of forming the interlayer connection electrode is performed by filling the opening of the pattern forming material with metal by performing a plating process. By selectively plating metal on portions, an interlayer connection electrode having a thickness dimension of a thick film pattern forming material or higher can be formed, thereby quickly forming an interlayer connection electrode. In addition to this, the interlayer connection electrode can be formed with a formation accuracy that is in accordance with the formation accuracy of the opening of the pattern forming material.

According to the sixth aspect of the present invention, in the first to fourth aspects of the present invention, in the step of forming an interlayer connection electrode, the interlayer connection electrode is formed by filling a conductive paste so as to be embedded in the opening of the pattern forming material. For example, if a conductive paste is filled in the opening by using a printing technique and then a thermosetting treatment is performed, the interlayer connection electrode can be formed quickly and accurately.

According to a seventh aspect of the present invention, in the first to sixth aspects of the present invention, after the step of forming the interlayer connection electrode, the semiconductor chip is mounted on a bare chip, and a resin is applied so as to cover the semiconductor chip. Then, by performing a grinding process on the applied resin, the semiconductor chip is ground to a predetermined thickness and the interlayer connection electrode is exposed,
While the thickness of the resin was ground so as to match the height of the interlayer connection electrode, the thickness of the semiconductor chip could be ground to the predetermined thickness at the same time, and the interlayer connection electrode was easily and quickly formed. A configuration can be obtained.

According to the invention of claim 8, in the invention of claim 7, after the resin grinding process is completed, a stud bump electrically connected to the exposed interlayer connection electrode is formed. Since the resin layer is formed so as to cover the ground upper surface portion of the semiconductor chip in a state where the upper surface portion is exposed, even when a multilayer circuit module is further stacked on the upper portion, the underlying structure can be easily obtained. become able to.

According to a ninth aspect of the present invention, in the first to sixth aspects of the present invention, after forming the interlayer connection electrode, the height in the mounted state is previously set to be equal to or less than the height of the interlayer connection electrode. Since the ground semiconductor chip is mounted on a bare chip and a resin layer is formed so as to cover the semiconductor chip and expose at least an upper portion of the interlayer connection electrode,
There is no need to perform grinding after mounting the semiconductor chip,
As a method of forming the resin layer, a method other than grinding can be used, and the degree of freedom in designing the manufacturing process increases.
In addition, a configuration in which the interlayer connection electrode is formed easily and quickly can be obtained.

According to the tenth aspect, the ninth aspect is provided.
In the invention of the above, in the mounting state of the semiconductor chip, the height dimension is set to be lower than the height dimension of the interlayer connection electrode by a predetermined dimension or more, so that after applying the resin, the resin layer is formed on the interlayer connection electrode. By performing height adjustment by grinding or other methods until the height is reached, a configuration in which an insulating layer on the back surface side of the semiconductor chip is provided can be achieved.

According to the eleventh aspect of the present invention, in the first to sixth aspects, prior to the step of applying a thick film pattern forming material for forming an interlayer connection electrode, a semiconductor chip is mounted on a base, Since grinding processing is performed from the upper surface side of the mounted semiconductor chip to a predetermined height dimension,
Since the height of the interlayer connection electrode can be formed to a desired size without depending on the thickness of the semiconductor chip, a method other than grinding can be used as a method of forming the resin layer. In addition, it is possible to increase the degree of freedom of the manufacturing process, and to obtain a configuration in which the interlayer connection electrode is formed easily and quickly.

According to a twelfth aspect of the present invention, in the first to sixth aspects, prior to the step of applying a thick film pattern forming material for forming an interlayer connection electrode, a semiconductor chip is mounted on a base, Thereafter, a thick film pattern forming material is applied, and a grinding process is performed until the height of the semiconductor chip reaches a predetermined height in a state in which the thick film pattern forming material is applied. Since the opening corresponding to the shape of the interlayer connection electrode is formed in the forming material, the semiconductor chip is ground so as to have a predetermined thickness while the thick film pattern forming material is applied. Therefore, since the interlayer connection electrode is formed using the pattern forming material having the same height as the height, the height can be accurately formed and the height of the pattern forming material can be increased. When the interlayer connection electrode is formed so as to protrude from the semiconductor layer, the semiconductor chip can be buried and formed with the insulating layer interposed therebetween in a simple process with high accuracy in forming the resin layer. Exposed.

According to the thirteenth aspect of the present invention, a laminated circuit module having a configuration in which a semiconductor chip is electrically connected and resin-sealed on a wiring substrate or another laminated circuit module serving as a base is formed. In the method of manufacturing a circuit module, a semiconductor chip is mounted on a bare chip, a metal pillar serving as an interlayer connection electrode is bonded to a base, and a resin layer is formed so as to cover the semiconductor chip and expose an upper surface of the interlayer connection electrode. Therefore, since the interlayer connection electrode is formed by joining the metal pillars, the interlayer connection electrode can be formed relatively quickly, and can be formed by a simple and inexpensive process using existing equipment. Become.

According to the fourteenth aspect, the first aspect is provided.
In the invention of the third aspect, in the step of joining the metal pillars, the metal pillars are pressed and joined in a state of being vibrated by ultrasonic waves, so that the joining of the metal pillars can be surely performed, and the joining can be quickly performed. You will be able to proceed with your work.

According to the fifteenth aspect, the ninth aspect is provided.
In the fourteenth invention, the upper surface portion of the resin applied to cover the semiconductor chip and the interlayer connection electrode is subjected to pressure treatment with a flat plate from the upper surface portion so that the upper surface portion of the interlayer connection electrode is exposed. Therefore, when the thickness of the semiconductor chip is previously formed to a predetermined size by grinding or the like, a process for exposing the interlayer connection electrode can be performed quickly and reliably, and the resin layer can be accurately formed. Will be able to

According to a sixteenth aspect of the present invention, in the ninth to fourteenth aspects, the resin applied so as to cover the semiconductor chip and the interlayer connection electrode is thermally cured, and then subjected to a grinding process. Is performed so that the upper surface portion of the interlayer connection electrode is exposed, so that when the semiconductor chip needs to be ground, it can be simultaneously processed in the process of grinding the resin layer. Thus, it can be formed quickly and reliably.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, as a first embodiment of the present invention, one wiring board is provided on a wiring substrate as a base.
A manufacturing method in the case of forming a layered circuit module for layers will be described with reference to FIGS. In addition,
In this configuration, surface mount components such as other ICs and discrete elements are mounted on the surface of each wiring board.

The laminated circuit module 1 to which the manufacturing method of the present invention is applied is configured as shown in the schematic cross section shown in FIG. The wiring board 2 as a base is a multilayer wiring board having a thickness of, for example, about 0.6 to 0.8 mm. A plurality of conductor layers are formed in a predetermined wiring pattern inside the wiring board 2 and exposed on the front and back. Wiring patterns 2a, 2
b. On the wiring board 2, a first resin layer 3 and a second resin layer 4 are sequentially laminated.

The first resin layer 3 is buried in a state where a semiconductor chip 5 and an interlayer connection electrode 6 and the like in which a semiconductor element typified by an IC or an LSI is formed are mounted on the wiring board 1. ing. In this case, the semiconductor chip 5 is electrically connected to the wiring pattern of the wiring board 1 via the bump electrodes 7 with the element forming surface facing down, and
It is fixed using an anisotropic conductive paste 8 and is in a state of being flip-chip mounted face-down.

The lower end of the interlayer connection electrode 6 is electrically connected to the wiring patterns 2a and 2b of the wiring board 1, and the like.
The upper end is provided so as to be exposed on the upper surface of the first resin layer 3. The first resin layer 3 has a thickness of, for example, 1
The semiconductor chip 5 is formed to have a thickness of about 50 μm.
It is in a state of being ground to about 0 μm.

In FIG. 3 (the same applies to FIGS. 1 and 2),
For the sake of simplicity, a configuration in which one semiconductor chip 5 is mounted as the laminated circuit module 1 is shown, but a configuration in which a plurality of various semiconductor chips corresponding to the semiconductor chip 5 are mounted is assumed. ing.

The second resin layer 4 is laminated on the first resin layer 3 and has a thickness of, for example, about 50 μm on the upper surface of the semiconductor chip 5 so as to function as an insulating layer. It is formed so that it becomes. This second resin layer 4
Is formed in a state in which a bump electrode 9 for electrically connecting the interlayer connection electrode 6 on the lower surface side to the upper surface side is buried.

As will be described later, the first resin layer 3
The upper surface of the semiconductor chip 5 and the interlayer connection electrode 6 are ground by grinding.
Are removed to a predetermined thickness so as to be exposed, and as a result, a flat surface is formed. Therefore, the semiconductor portion on the back surface, that is, the upper surface of the semiconductor chip 5 is exposed, and the second resin layer 4 is formed so as to cover the exposed portion of the semiconductor chip 5.

With the configuration described above, the portion on which the semiconductor chip 5 is mounted can be configured not to be exposed on the surface of the multilayer circuit module 1, and the area for mounting discrete components can be reduced. This can be performed using the entire surface of the substrate, or another stacked circuit module can be formed in a stacked manner. As a result,
Since a three-dimensional mounting structure can be provided, the overall mounting efficiency can be improved, and the degree of freedom in design can be increased.

Next, a method of manufacturing the above-described laminated circuit module 1 will be described with reference to FIGS.
A description will be given with reference to cross-sectional structural diagrams in each step of FIG. In the actual manufacture of the multilayer circuit module 1, the wiring board 2 is formed in a size of a plurality (for example, six) of the multilayer circuit modules 1 so that a plurality of the circuit boards can be manufactured at a time. The completed product is cut off by a method such as dicing to finally obtain the laminated circuit module 1.

In the following description, the manufacturing process of one laminated circuit module 1 is divided into the following seven processes according to the process flow of FIG. (1) Base preparation step S
1, (2) interlayer connection electrode forming step S2, (3) chip mounting step S3, (4) first resin layer forming step S4,
(5) grinding step S5, (6) wiring electrode forming step S6,
(7) Second resin layer forming step S7.

(1) Base preparation step S1 First, a wiring board 2 to be used as a base for forming the laminated circuit module 1 is prepared. The wiring board 2 is laid out on one side in a wiring pattern corresponding to the flip-chip mounting of the semiconductor chip 5, and on the back side (lower side),
The wiring pattern is laid out with input / output electrode pads, pads for mounting discrete components, etc., and connected via an internal wiring conductor pattern layer.

(2) Interlayer Connection Electrode Forming Step S2 Next, an interlayer connection electrode 6 is formed on the wiring board 2. In this step, processing is performed according to the process flow shown in FIG. First, as shown in FIG. 1A, a thick film resist 10 as a pattern forming material is
A predetermined film thickness is applied in a range of up to 150 μm (thick film resist coating step P1). In this case, the thick film resist 10
For example, LIGA (Lithographie Galvanoformung und Ab
Form-8) uses a photoresist called SU-8 developed by IBM, which is used in processes and the like, and is known as a negative type resist exposed to ultraviolet rays using an epoxy resin.

The pattern forming material is not limited to the above-mentioned materials, but is not limited to the above-mentioned negative type, epoxy-based, and ultraviolet exposure conditions as long as it functions as a thick film resist, and may be a positive type. It may be made of various materials, or may be exposed by X-rays, which are short-wavelength light other than ultraviolet rays, or radiation light called SR (Syncrotron Radiation).

Subsequently, as shown in FIG. 1B, exposure is performed with ultraviolet rays using a photomask 11 on which a pattern for forming an interlayer connection electrode 6 is formed (exposure step P2).
Thereby, the thick film resist 1 in the portion exposed to the ultraviolet rays
0 is exposed to light and deteriorates, and becomes insoluble in the resist patterning process.

The arrangement position of the interlayer connection electrode 6 is set at a predetermined position around a region where the semiconductor chip 5 is mounted, at a portion where the wiring patterns 2a and 2b of the wiring substrate 2 as a base are exposed. Although one interlayer connection electrode 6 is arranged on each side of the semiconductor chip 5 in FIG. 1, generally several tens to several hundreds are arranged according to the function of the semiconductor chip 5. It has become so.

Thereafter, as shown in FIG. 1C, an opening 10a is formed by performing a developing process to selectively remove the thick film resist 10 at a portion where the interlayer connection electrode 6 is to be formed (opening 10a). Forming step P3). The opening 10a is formed to have a depth dimension of 100 to 150 μm and an outer diameter of, for example, about 10 to 50 μm. The technique using the thick film resist 10 has a high aspect ratio and good accuracy in the depth direction. Pattern can be formed.

Next, as shown in FIG. 1D, a metal, for example, copper (Cu) to be the interlayer connection electrode 6 is filled and formed in the opening 10a by performing a plating process (electrode forming step). P4). In this plating process, the case where copper plating is performed is described, but other metals can also be plated. Subsequently, as shown in FIG. 2E, the thick film resist 11 is removed to make the interlayer connection electrodes 6 independently formed (thick film resist removing step P5). As described above, the interlayer connection electrode forming step S1 is completed, and the interlayer connection electrode 6 is formed.

(3) Chip mounting step S3 Subsequently, the semiconductor chip 5 is flip-chip mounted on the wiring board 2 as shown in FIG. Prior to mounting the semiconductor chip 5, the bump electrodes 7 are formed.
The bump electrode 7 is formed by forming a stud bump such as gold (Au) or copper (Cu) with a ball bonder or the like. Unlike a solder bump, a reflow process cannot be performed when the semiconductor chip 5 is mounted. As described above, the anisotropic conductive paste 8 is applied to the mounting position of the wiring board 2.

The wiring board 2 is coated with the anisotropic conductive paste 8, the semiconductor chip 5 is placed in this state, and the semiconductor chip 5 is placed on the wiring board 2, and the semiconductor chip 5 is heated while being pressurized to perform a curing process. The force applied to the semiconductor chip 5 is one bump electrode 7
Per hundred to several hundreds of mN (millinewton), and the anisotropic conductive paste 12 is thermally cured by heating in that state. The curing temperature at this time is, for example, 120 ° C to 14 ° C.
The predetermined temperature is in the range of 0 ° C.

The thickness of the semiconductor chip 5 to be mounted is, for example, 300 to 600 μm when a wafer having a diameter of 15 cm is used in the manufacturing process, and at least about 300 μm when supplied in a chip state. It is common that there is. Even when the wafer is relatively thick in a wafer state, it may be thinned by grinding before cutting into chips. Although the case where the bump electrode 7 is formed of gold has been described, for example, a bump electrode made of copper may be formed.

(4) First Layer Resin Layer Forming Step S4 Next, as shown in FIG. 2G, the flip-chip mounted semiconductor chip 5 and the interlayer connection electrode 6 are connected to the thermosetting resin 1.
2 to form the first resin layer 3.
The thermosetting resin 12 is made of, for example, an epoxy-based material,
After being applied to the upper surface of the wiring board 2, a thermosetting treatment is performed at a heat treatment temperature in the range of 120 to 140C. in this case,
The coating operation is performed so that the epoxy-based thermosetting resin 12 completely covers the semiconductor chip 5 and the interlayer connection electrode 6.

The selection of the epoxy-based thermosetting resin 12 is based on a resin having sufficient resistance to treatments such as pressure and heating during a series of manufacturing steps. In this embodiment, a material having a glass transition temperature of 140 ° C. or higher is used as the epoxy-based thermosetting resin 12, and the thermosetting treatment is performed at a temperature lower than the glass transition temperature. .

Thus, the epoxy thermosetting resin 12
Can be prevented from being softened and plastically deformed when thermally hardened, and from applying unexpected stress to the semiconductor chip 5. Further, the processing time of the thermosetting treatment depends on the processing temperature, and for example, a predetermined time in a range from several minutes to about 20 minutes is set. The relationship between the heat treatment temperature and the heat treatment time can be shortened by setting the temperature to a high value. However, since it is expected that the stress applied to the semiconductor chip 5 is also increased, these factors are taken into consideration. Therefore, it is necessary to set appropriate temperature and time.

(5) Grinding Step S5 Next, as shown in FIG. 2H, the first resin layer 3 is formed by grinding the resin layer 12 in which the semiconductor chip 5 and the interlayer connection electrode 6 are embedded. . Here, the resin layer 12 is ground from the surface using a grinding machine. When the semiconductor chip 5 is exposed, the semiconductor chip 5 is also ground together. When the upper surface of the interlayer connection electrode 6 is finally exposed, the grinding is performed. The process ends. Therefore, the grinding process is performed until the thickness of the semiconductor chip 5 is about 100 μm and the height from the surface of the wiring board 2 is about 150 μm.

As a result, on the surface of the resin layer 12 after the grinding, the back side of the semiconductor chip 5 is exposed and the upper part of the interlayer connection electrode 6 is exposed. Thereby, the interlayer connection electrode 6 can be formed so as to be embedded while penetrating the first resin layer 3, and the semiconductor chip 5 ground to a predetermined thickness is embedded therein. It can be.

(6) Wiring Electrode Forming Step S6 Next, as shown in FIG. 3 (i), bump electrodes 9 are formed. This is performed by using gold (Au) or copper (C
u) is formed by using a ball bonder. In this case, the height dimension of the bump electrode 9 is, for example, about 50 μm.

(7) Second Resin Layer Forming Step S7 Subsequently, as shown in FIGS. 3 (j) and 3 (k), the second resin layer 4 is formed so that the bump electrodes 9 are buried. To form First, an epoxy-based thermosetting resin 13 is formed on the ground upper surface of the first resin layer 3 so as to cover the bump electrodes 9.
Is applied (see FIG. 3 (j)). Next, in a state where the release agent 14a is applied to the flat glass 14 having a plate thickness of about 1 mm and having good flatness and parallelism, the release agent 14a is placed on the applied thermosetting resin 13 and heated under pressure. A curing process is performed (see FIG. 3 (k)). In this case, the flat glass 14 is made of a material that does not deform when pressed, and the release agent 14a is a silicon-based heat-resistant material such as a release agent used in casting. You are using

The bump electrode 9 covered with the thermosetting resin 13 by the flat glass 14 is crushed. The force applied to the bump electrodes 9 is about several hundreds to several hundreds of mN. Then, heating is performed in this state to cure the thermosetting resin 13, thereby forming the second resin layer 4. The thermosetting temperature at this time is a predetermined temperature in the range of 120 to 140 ° C.

Thus, a second resin layer 4 is formed,
The bump electrode 9 is formed with its upper surface exposed. The semiconductor chip 5 and the interlayer connection electrode 6 are formed so as to be embedded in the first resin layer 3 and the second resin layer 4, and the interlayer connection electrode 6 is
Is brought into a state where it can be electrically connected to the surface of the resin layer 4.

Through the above steps, a one-layer laminated circuit module 1 is obtained. Further, when the present invention is applied to a multilayer circuit module, the same steps as described above are repeatedly performed to form a multilayer circuit module having another semiconductor chip embedded in the same structure on the multilayer circuit module 1. Can be formed.

Finally, as described above, the circuit module 1 is divided into individual circuit modules 1 through a dicing process and the like. Finally, other semiconductor elements and surface mount components such as discrete components are mounted on the wiring board 2. By mounting and arranging, it is possible to obtain a compact circuit board having a high mounting density.

According to the first embodiment, when the interlayer connection electrode 6 is formed, a metal such as copper is collectively formed by plating, so that the method using the conventional technique such as the JPS method is used. The processing time required for formation is not proportional to the processing time per piece, but all the interlayer connection electrodes 6 can be formed collectively. This means that regardless of the type of the semiconductor chip 5 to be mounted, that is, the number of wiring electrodes, and the number of the semiconductor chips 5 to be mounted, the interlayer connection electrodes 6 can be collectively formed. The effect increases as the number increases for the purpose of improving the degree of integration. In addition, since the technique used in the LIGA process or the like is applied, the interlayer connection electrode 6 can be formed efficiently and accurately using the thick film resist 10.

(Second Embodiment) FIGS. 6 and 7 show a second embodiment of the present invention. The difference from the first embodiment is that the manufacturing process is as shown in FIG. The laminated circuit module 15 is formed by performing a grounded chip mounting step S8 instead of the chip mounting step S3 and performing a pressure hardening step S9 instead of the grinding step S5.

FIG. 6E shows a cross-sectional structure of the laminated circuit module 15. In this embodiment, the same structure as described above is obtained by using one resin layer 16 except for this point. Thus, the configuration is the same as that of the first embodiment.

Next, a method of manufacturing the above configuration will be described. In the second embodiment, a base preparation step Q1
After the wiring board 2 is prepared by performing (same as the base preparation step S1), the interlayer connection electrode forming step Q2 (same as the interlayer connection electrode forming step S2) is performed to form the interlayer connection electrode 6 (FIG. 6). (A)).

Subsequently, as shown in FIG. 6B, the semiconductor chip 5 which has been subjected to a grinding process in advance and adjusted to a predetermined thickness is mounted on the wiring board 2 (ground chip mounting step Q3). The thickness dimension of the semiconductor chip 5 at this time is prepared by performing a grinding process in a wafer or chip state in advance so that the thickness dimension of the semiconductor chip 5 is lower than the height dimension of the interlayer connection electrode 6 in a state of being mounted on the wiring board 2. I have.

Thereafter, as shown in FIG. 6C, an epoxy-based thermosetting resin 17 is applied to bury the semiconductor chip 5 and the interlayer connection electrode 6 (resin layer forming step Q4). Next, as shown in FIG. 6D, the applied thermosetting resin 1
7 having a release agent 14a applied to the surface from above
Then, a thermal curing process is performed while pressing and applying pressure (pressure curing process step Q5).

At this time, the force applied to the flat glass 14 is
For example, it is set so as to be several hundreds to several hundreds mN per one interlayer connection electrode, and the thermosetting temperature is about 110 ° C.
When the flat glass 14 is removed after the thermosetting treatment, the resin layer 16 is formed, and the surface thereof is formed such that the upper portion of the interlayer connection electrode 6 is exposed (FIG. 6D).
reference).

According to the second embodiment, since the semiconductor chip 5 is mounted in a state where the grinding processing has been performed in advance, it is possible to employ a process other than the grinding processing when forming the resin layer 16. If the thermosetting treatment is performed while pressing with the flat glass 14 as in this embodiment, the laminated circuit module 15 can be manufactured simply and inexpensively.

(Third Embodiment) FIGS. 8 to 10 show a third embodiment of the present invention. The difference from the second embodiment is that the semiconductor chip 5 is mounted first, and The connection electrode 6 has just been formed. By mounting the semiconductor chip 5 first, the grinding process can be performed first.

FIG. 10 shows the manufacturing process. When a base preparation step R1 (same as the base preparation step S1) is carried out, next, as shown in FIG. Mount the chip 5 (chip mounting process R
2). Subsequently, as shown in FIG. 8B, the mounted semiconductor chip 5 is subjected to a grinding process in that state and adjusted to a predetermined thickness (grinding step R3).

Next, an interlayer connection electrode 6 is formed by performing an interlayer connection electrode forming step R4. in this case,
First, as shown in FIG. 8C, a thick resist 10 is applied on the wiring substrate 2 so as to cover the semiconductor chip 5 (thick resist application step P1). Next, as shown in FIG. 8D, exposure is performed with ultraviolet rays using the photomask 11 in the same manner as in the first embodiment (exposure step P2). Thereafter, as shown in FIG. 9 (e), an opening 10a is formed by performing a developing process to selectively remove the portion of the thick film resist 10 where the interlayer connection electrode 6 is to be formed (opening forming step P3). ).

Next, as shown in FIG. 9 (f), a plating process is performed to fill and form a metal, for example, copper (Cu), which will become the interlayer connection electrode 6 in the opening 10a (electrode forming step). P4). Subsequently, as shown in FIG. 9G, the thick-film resist 11 is removed so that the interlayer connection electrode 6 is formed independently (thick-film resist removing step P).
5). As described above, the interlayer connection electrode forming step R4 is completed, and the interlayer connection electrode 6 is formed.

In the following steps, as in the second embodiment, the resin layer forming step R5 (the resin layer forming step Q4
And the pressure hardening step R6 (the same as the pressure hardening step Q5), whereby the laminated circuit module 15 can be obtained.

A similar effect can be obtained by the third embodiment, and the grinding step R3 is performed before the formation of the interlayer connection electrode 6, so that the height of the interlayer connection electrode 6 is reduced The height of the resin layer 1 can be set to be higher than the height of the chip 5.
The laminated circuit module 15 can be formed by the processing of forming only one layer 6.

(Fourth Embodiment) FIGS. 11 to 13 show a fourth embodiment of the present invention. The difference from the third embodiment is that a semiconductor chip 5 is mounted and then a grinding step is performed. The step of applying the thick film resist 10 has just been performed. FIG. 13 shows the manufacturing process, in which a base preparation step T1 (the same as the base preparation step R1) is performed, and a chip mounting step T2 (the same as the chip mounting step R2) is performed as shown in FIG. carry out.

Subsequently, as shown in FIG. 11B, a thick film resist coating step T3 is performed. In this case, a positive type resist is used here as the thick film resist 18 which is a pattern forming material. After the application, heat treatment is performed at, for example, about 100 ° C. in order to thermally cure the thick film resist 18. This is to prevent the thick film resist 18 from being damaged by the subsequent grinding process.

Then, with the thick film resist 18 applied, a grinding step T4 is subsequently performed as shown in FIG. 11 (c). In other words, here, the grinding process is performed on the semiconductor chip 5 together with the thick film resist 18 until the semiconductor chip 5 has a predetermined thickness. Therefore, as the thick film resist 18, it is assumed that a material that is not damaged by the grinding process is selected and used.

Subsequently, as shown in FIG. 11D, a photomask 19 patterned for the positive type is positioned and placed on the surface of the ground thick-film resist 18 and is irradiated with ultraviolet rays. Exposure is performed (exposure step T5).
Thereafter, as shown in FIG. 11E, the exposed thick film resist 18 is developed to form an opening 18a in a portion corresponding to the interlayer connection electrode 6 (opening forming step T).
6).

Next, as shown in FIG. 12F, the above-described plating process is performed so as to fill the formed opening 18a with the electrode metal (electrode forming step T7). At this time, the height dimension of the interlayer connection electrode 6 formed by the plating process is set to a predetermined position protruding from the upper surface of the thick film resist 18. Although the interlayer connection electrode 6 may tend to spread slightly above the upper surface of the opening 18a, the amount of the interlayer connection electrode 6 does not substantially adversely affect the interlayer connection electrode 6.

Thereafter, as shown in FIG. 12G, the thick film resist 18 is removed (thick film resist removing step T).
8), it can be formed in the same state as FIG. 9 (g) in the third embodiment. Thereafter, the laminated circuit module 15 is obtained through the same manufacturing process. Specifically, FIG.
As shown in (h), an epoxy-based thermosetting resin 17 is applied to perform a resin layer forming step T9. Next, a pressure curing treatment step T9 is performed using the flat glass 14 having the surface coated with the release agent 14a. As a result, FIG.
As shown in (1), a laminated circuit module 15 is obtained. In addition, according to the fourth embodiment, the same effect curing as in the third embodiment can be obtained.

(Fifth Embodiment) FIGS. 14 and 15 show a fifth embodiment of the present invention. The difference from the second, third or fourth embodiment is that a resin layer 16 is added. The resin layer 1 is formed by grinding the thermosetting resin 17 instead of the pressure hardening process Q5, R6 or T10.
I'm trying to get 6.

That is, the semiconductor chip 5 mounted on the wiring board 2 is ground to a predetermined thickness, and an interlayer connection electrode 6 is formed around the periphery of the semiconductor chip 5 to a predetermined size higher than the height of the semiconductor chip 5. 6 (b) of the second embodiment, the state of FIG. 9 (g) of the third embodiment, and the state of FIG. 12 (g) of the fourth embodiment. The following configuration is implemented.

As shown in FIG. 15, a part of the manufacturing process is performed. First, an epoxy-based thermosetting resin 17 is applied, and a resin layer forming process T9 is performed (see FIG. 14A). Subsequently, the applied thermosetting resin 17 is cured by performing a heat treatment at a predetermined temperature (thermosetting process T11). Thereafter, as shown in FIG. 14B, the thermosetting resin 17 is ground until the interlayer connection electrode 6 is exposed from the upper surface (grinding step T12). Thereby, the laminated circuit module 15 can be obtained.

(Sixth Embodiment) FIG. 16 shows a sixth embodiment of the present invention.
This embodiment is different from the fourth embodiment in the method of forming the electrode forming step T7 and the subsequent processing steps. That is, this embodiment is different from the first embodiment in that the interlayer connection electrode 20 is formed not by plating but by printing.

As described in the fourth embodiment, when the opening 18a is formed in the thick film resist 18 through the exposure step T5 and the opening forming step T6 (see FIG. 11E),
Thereafter, using a screen printing technique, the squeegee 21
The conductive paste 22 is printed from above the thick film resist 18 (see FIG. 16A). As a result, the conductive paste 22 is filled in the openings 18a of the thick film resist 18, and thereafter, a thermosetting process is performed to form the interlayer connection electrodes 20.

Subsequently, as shown in FIG. 16B, when the thick film resist 18 is removed, an interlayer connection electrode 20 erected by the conductive paste 22 is obtained. In this state, since the height of the interlayer connection electrode 20 cannot be formed to be larger than the height of the thick film resist 18 due to the printing process, the height of the interlayer connection electrode 20 is formed to be the same as the height of the semiconductor chip 5. Will be done. Therefore, in the subsequent processing steps, the same processing steps as those in the fourth embodiment cannot be performed, so the processing is performed as follows.

First, the semiconductor chip 5 and the interlayer connection electrode 2
The first resin layer 3 is formed by applying an epoxy thermosetting resin so as to cover 0 and performing a pressure thermosetting process. Subsequently, the bump electrode 9 is formed on the interlayer connection electrode 20 by performing the wiring electrode forming step S6 in the first embodiment, as shown in FIG. Subsequently, a second-layer resin layer forming step S7 is performed to form the second-layer resin layer 4 so as to bury the bump electrodes 9, whereby a laminated circuit module can be obtained.

(Seventh Embodiment) FIG. 17 shows a seventh embodiment of the present invention.
It shows the embodiment of the present invention, unlike the above-described embodiments,
The interlayer connection electrode 23 is formed as follows. That is, the semiconductor chip 5 (having a thickness of 100 μm)
m) (see FIG. 17A), and in this state,
Using an ultrasonic bonding apparatus 24, a column made of gold (Au) (for example, a gold wire having a height of 200 μm and a diameter of about 100 μm) is ultrasonically bonded (see FIG. 17B). In this case, since the height of the semiconductor chip 5 in the mounted state is about 150 μm, the interlayer connection electrode 23 is 50 μm thicker than the semiconductor chip 5.
The size is set to about μm higher. Thereafter, an epoxy-based thermosetting resin 12 is applied (see FIG. 17C), and thereafter, a pressure curing process is performed to obtain a laminated circuit module.

(Other Embodiments) The present invention is not limited to the above embodiment, but can be modified or expanded as follows. Thick film resist 10 as a pattern forming material,
Although the description has been given of the case where 18 is used, the material is not limited to this, and any material that can achieve the above object can be used, even if the material is applied to other than the LIGA process.

In the case of using the first resin layer 3 and the second resin layer 4, the same resin may be used or different kinds of resins may be used. For their selection, optimal ones can be used from various viewpoints such as the relationship of stress, affinity, and electrical characteristics. The bump electrodes 9 embedded in the second resin layer 4 may be formed by printing a conductive paste.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view corresponding to a processing step according to a first embodiment of the present invention (part 1).

FIG. 2 is a schematic cross-sectional view corresponding to a processing step (part 2).

FIG. 3 is a schematic cross-sectional view corresponding to a processing step (part 3).

FIG. 4 is a process flow diagram (part 1).

FIG. 5 is a process flowchart (part 2).

FIG. 6 is a schematic cross-sectional view corresponding to a processing step according to a second embodiment of the present invention.

FIG. 7 is a process flowchart.

FIG. 8 is a schematic cross-sectional view corresponding to a processing step according to a third embodiment of the present invention (part 1).

FIG. 9 is a schematic cross-sectional view corresponding to a processing step (part 2).

FIG. 10 is a process flow chart.

FIG. 11 is a schematic cross-sectional view corresponding to a processing step according to a fourth embodiment of the present invention (part 1).

FIG. 12 is a schematic cross-sectional view corresponding to a processing step (part 2).

FIG. 13 is a process flow chart.

FIG. 14 is a schematic cross-sectional view corresponding to a processing step showing a fifth embodiment of the present invention.

FIG. 15 is a process flow chart.

FIG. 16 is a schematic cross-sectional view corresponding to a processing step showing a sixth embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view corresponding to a processing step showing a seventh embodiment of the present invention.

[Explanation of symbols]

Reference numerals 1 and 15 are laminated circuit modules, 2 is a wiring board, 3 is a first resin layer, 4 is a second resin layer, 5 is a semiconductor chip, 6, 20, and 23 are interlayer connection electrodes, and 7 is a bump electrode. ,
8 is an anisotropic conductive paste; 9 is a bump electrode;
Is a thick film resist (pattern forming material), 10a is an opening, 11 and 19 are photomasks, 12, 13, and 17 are epoxy thermosetting resins, 14 is a flat glass, 14a is a release agent, and 16 is a resin layer. , 21 is a squeegee, 22 is a conductive paste, and 24 is an ultrasonic bonding device.

Claims (16)

[Claims] 1. A method for manufacturing a laminated circuit module, comprising laminating a laminated circuit module having a configuration in which a semiconductor chip is electrically connected and resin-sealed on a wiring substrate or another laminated circuit module serving as a base. A step of applying a thick film pattern forming material to the base, and forming an opening corresponding to a shape of an interlayer connection electrode for electrically connecting the base and the upper part to the pattern forming material. A method for manufacturing a laminated circuit module, comprising: a step of forming the interlayer connection electrode so as to fill an opening of the pattern forming material; and a step of removing the pattern forming material. 2. The method for manufacturing a laminated circuit module according to claim 1, wherein the pattern forming material is a photosensitive material having a negative characteristic or a positive characteristic. 3. The method for manufacturing a laminated circuit module according to claim 2, wherein the pattern forming material is a material that is exposed to a light source having a shorter wavelength than visible light, such as ultraviolet light, X-ray, or other radiation. A method for manufacturing a laminated circuit module, comprising: 4. The method for manufacturing a laminated circuit module according to claim 1, wherein the pattern forming material has a thermosetting property. Method. 5. The method for manufacturing a laminated circuit module according to claim 1, wherein in the step of forming the interlayer connection electrode, an opening of the pattern forming material is filled with metal by performing a plating process. Forming the interlayer connection electrode by performing the method. 6. The method for manufacturing a laminated circuit module according to claim 1, wherein in the step of forming the interlayer connection electrode, a conductive paste is filled so as to be embedded in an opening of the pattern forming material. Forming the inter-layer connection electrode by using the method. 7. The method for manufacturing a laminated circuit module according to claim 1, wherein after forming the interlayer connection electrode, a step of mounting the semiconductor chip on a bare chip, and covering the semiconductor chip. Applying a resin by grinding the semiconductor chip to a predetermined thickness dimension by performing a grinding process on the applied resin, and exposing the interlayer connection electrode. Manufacturing method of a laminated circuit module. 8. The method for manufacturing a laminated circuit module according to claim 7, further comprising: forming a stud bump electrically connected to the exposed interlayer connection electrode after the resin grinding process is completed. Forming a resin layer so as to cover at least an upper surface portion of the stud bump and to cover a ground upper portion of the semiconductor chip. 9. The method for manufacturing a laminated circuit module according to claim 1, wherein after forming the interlayer connection electrode, a height dimension in a mounted state is equal to or less than a height dimension of the interlayer connection electrode. A step of mounting the semiconductor chip which has been ground in advance so as to be a bare chip, and a step of forming a resin layer so as to cover the semiconductor chip and expose at least an upper surface portion of the interlayer connection electrode. Manufacturing method of a laminated circuit module. 10. The method of manufacturing a laminated circuit module according to claim 9, wherein, in the mounting state of the semiconductor chip, a height thereof is set to be lower than a height of the interlayer connection electrode by a predetermined size or more. A method for manufacturing a laminated circuit module, comprising: 11. The method for manufacturing a multilayer circuit module according to claim 1, wherein the step of applying a thick film pattern forming material for forming the interlayer connection electrode comprises: A method for manufacturing a laminated circuit module, comprising: a step of mounting a semiconductor chip; and a step of performing a grinding process from an upper surface side of the mounted semiconductor chip to a predetermined height. 12. The method for manufacturing a laminated circuit module according to claim 1, wherein the step of applying a thick film pattern forming material for forming the interlayer connection electrode comprises: Implementing a step of mounting a semiconductor chip, following the step of applying the thick film pattern forming material, the height of the semiconductor chip in a state where the thick film pattern forming material is applied and a predetermined height dimension A method of manufacturing a laminated circuit module, comprising: performing a grinding process until the formation is completed; and forming an opening corresponding to the shape of the interlayer connection electrode in the pattern forming material. 13. A method for manufacturing a laminated circuit module, comprising laminating a laminated circuit module having a configuration in which a semiconductor chip is electrically connected to a base substrate or another laminated circuit module and sealed with a resin. A step of mounting the semiconductor chip on a bare chip, a step of joining a metal pillar serving as an interlayer connection electrode to the base, and a step of forming a resin layer so as to cover the semiconductor chip and expose at least an upper surface of the interlayer connection electrode. And a method for manufacturing a laminated circuit module. 14. The method for manufacturing a laminated circuit module according to claim 13, wherein, in the step of joining the metal columns, the metal columns are joined by pressure contact in a state of being vibrated by ultrasonic waves. A method for manufacturing a circuit module. 15. The method for manufacturing a laminated circuit module according to claim 9, wherein a resin applied to cover the semiconductor chip and the interlayer connection electrode is flat-plated from above. A method of manufacturing a laminated circuit module, wherein a thermosetting treatment is performed while pressing to form at least an upper surface portion of the interlayer connection electrode. 16. The method of manufacturing a laminated circuit module according to claim 9, wherein the resin applied to cover the semiconductor chip and the interlayer connection electrode is thermally cured. A method of manufacturing a laminated circuit module, wherein the upper surface of the interlayer connection electrode is exposed by performing a grinding process thereafter.