JPH0558660B2 - - Google Patents

Info

Publication number
JPH0558660B2
JPH0558660B2 JP14047689A JP14047689A JPH0558660B2 JP H0558660 B2 JPH0558660 B2 JP H0558660B2 JP 14047689 A JP14047689 A JP 14047689A JP 14047689 A JP14047689 A JP 14047689A JP H0558660 B2 JPH0558660 B2 JP H0558660B2
Authority
JP
Japan
Prior art keywords
semiconductor element
conductor wiring
ring
pressurizing body
pressurizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14047689A
Other languages
Japanese (ja)
Other versions
JPH034546A (en
Inventor
Tomohiko Suzuki
Izumi Okamoto
Masayoshi Mihata
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14047689A priority Critical patent/JPH034546A/en
Publication of JPH034546A publication Critical patent/JPH034546A/en
Publication of JPH0558660B2 publication Critical patent/JPH0558660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758Means for moving parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83859Localised curing of parts of the layer connector

Description

【発明の詳細な説明】 産業上の利用分野 本発明は各種電子機器に利用される半導体の実
装装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor mounting device used in various electronic devices.

従来の技術 従来の技術を第2図a,bとともに説明する。
まず第2図aに示すようにセラミツク、ガラス、
ガラスエポキシ等よりなる配線基板1の導体配線
2を有す面に絶縁性の樹脂5を塗布する。導体配
線2はCr−Au、Al、Cu、ito等であり、樹脂5
は熱硬化型又は紫外線硬化型のエポキシ、シリコ
ン、アクリル等である。次に第2図bに示すよう
に半導体素子3の電極4と導体配線2とを一致さ
せ、半導体素子3を加圧し、配線基板1に押し当
てる。電極4はAl、Al、Cu等である。この時、
導体配線2上の樹脂5は周囲に押し出され、半導
体素子3の電極4を導体配線2は電気的に接触す
る。次に半導体素子3を加圧体6により加圧した
状態で上部外方により紫外線9を照射することに
より、半導体素子3周縁の樹脂5を硬化させ、仮
固定する。更に半導体素子3を加圧しながら加熱
することにより、樹脂5全体を硬化させ、この時
半導体素子3の電極4と導体配線2は樹脂5の接
着力により電気的接続がなされ、同時に半導体素
子3を配線基板1に固着することができる。
Prior Art The conventional technology will be explained with reference to FIGS. 2a and 2b.
First, as shown in Figure 2a, ceramic, glass,
An insulating resin 5 is applied to a surface of a wiring board 1 made of glass epoxy or the like having conductor wiring 2. The conductor wiring 2 is made of Cr-Au, Al, Cu, ito, etc., and the resin 5
are thermosetting or ultraviolet curing epoxy, silicone, acrylic, etc. Next, as shown in FIG. 2b, the electrodes 4 of the semiconductor element 3 and the conductor wiring 2 are aligned, and the semiconductor element 3 is pressed against the wiring board 1 by applying pressure. The electrode 4 is made of Al, Al, Cu, etc. At this time,
The resin 5 on the conductor wiring 2 is pushed out to the periphery, and the conductor wiring 2 comes into electrical contact with the electrode 4 of the semiconductor element 3. Next, while the semiconductor element 3 is pressurized by the pressurizing body 6, ultraviolet rays 9 are irradiated from the upper part outward to harden the resin 5 around the semiconductor element 3 and temporarily fix the semiconductor element 3. Furthermore, by heating the semiconductor element 3 while applying pressure, the entire resin 5 is cured, and at this time, the electrode 4 of the semiconductor element 3 and the conductor wiring 2 are electrically connected by the adhesive force of the resin 5, and at the same time, the semiconductor element 3 is cured. It can be fixed to the wiring board 1.

発明が解決しようとする課題 以上のように従来の技術では、半導体素子3の
電極4を配線基板1の導体配線2に直接接触させ
る方法であるため、多端子、狭ピツチの半導体素
子3の実装に有利な方法であるが、半導体素子3
が加圧体6に対し傾きを生じた時半導体素子3は
不均一に加圧され、そのひずみにより接続の信頼
性が低下すると云う問題があつた。
Problems to be Solved by the Invention As described above, in the conventional technology, the electrodes 4 of the semiconductor element 3 are brought into direct contact with the conductor wiring 2 of the wiring board 1, so the mounting of the semiconductor element 3 with multiple terminals and narrow pitches is difficult. This is an advantageous method for semiconductor device 3.
When the semiconductor element 3 is tilted with respect to the pressurizing body 6, the semiconductor element 3 is pressed unevenly, and the strain causes a problem in that the reliability of the connection is reduced.

課題を解決するための手段 上記問題点を解決するために本発明は、加圧部
を加圧体をOリングを介して押圧体で押圧する構
成としたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a configuration in which the pressurizing section presses a pressurizing body with a pressurizing body via an O-ring.

作 用 上記構成によれば、弾性体であるOリングの圧
縮ひずみによつて加圧体で半導体素子を均一に加
圧させることができるので、接続の信頼性の高い
ものとなる。
Effects According to the above configuration, the semiconductor element can be uniformly pressurized by the pressurizing body due to the compressive strain of the O-ring, which is an elastic body, so that the connection becomes highly reliable.

実施例 以下、本発明の一実施例を第1図a,bととも
に説明する。
Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1a and 1b.

まず第1図aに示すように、セラミツク、ガラ
ス、エポキシ等によりなる配線基板11の半導体
素子13を固着する部分にエポキシ、シリコン、
アクリル等よりなる絶縁性樹脂15を塗布する。
なお配線基板11上には導体配線12が設けられ
ている。この導体配線12はCr−Au、Al、Ito等
によりなる。次に第1図bに示すように半導体素
子13のAl、Au、Cu等よりなる突起状の電極1
4と導体配線12を一致させ、加圧体16により
加圧する。この時加圧体16はその押圧体17と
の間にOリング18を介在させておりOリング1
8の弾性によつて半導体素子13の傾きを吸収
し、平行な状態で加圧体16で半導体素子13を
加圧している。なお、加圧体16はガラス、サフ
アイア等の透明体で形成する。またOリング18
はシリコン、フツ素ゴム、CR等の弾性体よりな
る。加圧により導体配線12上の樹脂15は周囲
に押し出され、電極14と導体配線12が当接
し、この状態で加圧体16を通して紫外線19を
照射し、これによつて半導体素子13の周縁部の
樹脂15を硬化させ仮固定する。更に半導体素子
13を加圧しながら加熱することによつて半導体
素子13の電極14と導体配線12の電気的接続
と半導体素子13の機械的保持が完了される。
First, as shown in FIG.
An insulating resin 15 made of acrylic or the like is applied.
Note that conductor wiring 12 is provided on the wiring board 11. The conductor wiring 12 is made of Cr-Au, Al, Ito, or the like. Next, as shown in FIG. 1b, protruding electrodes 1 made of Al, Au, Cu, etc. of the semiconductor element 13
4 and the conductor wiring 12 and pressurized by the pressurizing body 16. At this time, the O-ring 18 is interposed between the pressing body 16 and the pressing body 17, and the O-ring 1
The elasticity of the semiconductor element 13 absorbs the tilt of the semiconductor element 13, and the pressure member 16 presses the semiconductor element 13 in a parallel state. Note that the pressurizing body 16 is made of a transparent material such as glass or sapphire. Also O-ring 18
is made of an elastic material such as silicone, fluorocarbon rubber, or CR. Due to the pressure, the resin 15 on the conductor wiring 12 is pushed out to the periphery, and the electrode 14 and the conductor wiring 12 come into contact with each other. The resin 15 is cured and temporarily fixed. Further, by heating the semiconductor element 13 while applying pressure, electrical connection between the electrode 14 of the semiconductor element 13 and the conductor wiring 12 and mechanical holding of the semiconductor element 13 are completed.

なお、加圧体16にFe、Al、Cu等よりなるリ
ング20を設けることにより、配線基板11によ
り反射された紫外線19がOリング18を劣下さ
せ、傾き吸収能力が低下することを防いでいる。
In addition, by providing the ring 20 made of Fe, Al, Cu, etc. on the pressurizing body 16, it is possible to prevent the ultraviolet rays 19 reflected by the wiring board 11 from degrading the O-ring 18 and reducing the tilt absorption ability. There is.

発明の効果 本発明の効果を以下に示す。Effect of the invention The effects of the present invention are shown below.

(1) 半導体素子を均一に加圧することにより、半
導体素子に与えるひずみをなくすることができ
るとともに、導体配線との接続の信頼性の高い
ものとすることができる。
(1) By uniformly applying pressure to the semiconductor element, it is possible to eliminate strain on the semiconductor element, and the reliability of the connection with the conductor wiring can be made high.

(2) 紫外線の照射と加圧が簡易な構造で実現で
き、量産性に優れたものとなる。
(2) Ultraviolet irradiation and pressurization can be achieved with a simple structure, making it highly suitable for mass production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本発明の一実施例の半導体実装
装置で用いる配線基板の断面図と加圧体部の断面
図、第2図a,bはともに従来の技術を示す断面
図である。 11……配線基板、12……導体配線、13…
…半導体素子、14……半導体素子の電極、15
……絶縁性の樹脂、16……加圧体、17……加
圧体の押圧体、18……Oリング、19……紫外
線、20……金属リング。
1A and 1B are cross-sectional views of a wiring board and a pressurizing body used in a semiconductor packaging device according to an embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views showing a conventional technique. . 11... Wiring board, 12... Conductor wiring, 13...
...Semiconductor element, 14... Electrode of semiconductor element, 15
... Insulating resin, 16 ... Pressure body, 17 ... Pressure body of pressure body, 18 ... O ring, 19 ... Ultraviolet light, 20 ... Metal ring.

Claims (1)

【特許請求の範囲】[Claims] 1 一端面が加圧面となり、他端面が紫外線の透
照面となつた加圧体と、この加圧体をOリングを
介して半導体素子に加圧する押圧体とを備えた半
導体実装装置。
1. A semiconductor mounting device comprising: a pressurizing body having one end surface serving as a pressurizing surface and the other end surface serving as a surface for transmitting ultraviolet rays; and a pressurizing body that presses the pressurizing body against a semiconductor element via an O-ring.
JP14047689A 1989-06-01 1989-06-01 Semiconductor mounting device Granted JPH034546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14047689A JPH034546A (en) 1989-06-01 1989-06-01 Semiconductor mounting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14047689A JPH034546A (en) 1989-06-01 1989-06-01 Semiconductor mounting device

Publications (2)

Publication Number Publication Date
JPH034546A JPH034546A (en) 1991-01-10
JPH0558660B2 true JPH0558660B2 (en) 1993-08-27

Family

ID=15269495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14047689A Granted JPH034546A (en) 1989-06-01 1989-06-01 Semiconductor mounting device

Country Status (1)

Country Link
JP (1) JPH034546A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2547895B2 (en) * 1990-03-20 1996-10-23 シャープ株式会社 Semiconductor device mounting method
JP2662131B2 (en) * 1991-12-26 1997-10-08 松下電器産業株式会社 Bonding equipment
WO2000011731A1 (en) * 1998-08-21 2000-03-02 Eveready Battery Company, Inc. Battery having printed label
JP3603890B2 (en) 2002-03-06 2004-12-22 セイコーエプソン株式会社 Electronic device, method of manufacturing the same, and electronic apparatus
JP4902229B2 (en) * 2006-03-07 2012-03-21 ソニーケミカル&インフォメーションデバイス株式会社 Implementation method
JP2010178667A (en) * 2009-02-05 2010-08-19 Nissin Frozen Foods Co Ltd Frozen seasoning liquid pack, frozen noodle containing the same, and method for producing the frozen noodle

Also Published As

Publication number Publication date
JPH034546A (en) 1991-01-10

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