KR100188707B1 - Mounting method of chip device using bidirectional conductive film - Google Patents
Mounting method of chip device using bidirectional conductive film Download PDFInfo
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- KR100188707B1 KR100188707B1 KR1019950028507A KR19950028507A KR100188707B1 KR 100188707 B1 KR100188707 B1 KR 100188707B1 KR 1019950028507 A KR1019950028507 A KR 1019950028507A KR 19950028507 A KR19950028507 A KR 19950028507A KR 100188707 B1 KR100188707 B1 KR 100188707B1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
이방성 도전막(ACF: anisotropic conductive film)을 갖는 IC 칩을 패널에 실장하는 칩형 소자의 실장방법에 관하여 개시한다. 본 발명의 칩형 소자 실장 방법은 IC칩 상에 패드 패턴을 형성하는 단계와, 상기 IC칩 상에 상기 패드패턴을 노출하는 절연막을 형성하는 단계와, 상기 패드 패턴 및 절연막 상에 보호막을 갖는 이방성 도전막을 부착하는 단계와, 상기 패드패턴을 통하여 상기 이방성 도전막을 가열시키는 단계와, 상기 가열되지 않은 보호막을 갖는 이방성 도전막을 제거하여 상기 패드패턴 상에 패터닝된 이방성 도전막을 형성하는 단계와, 상기 IC칩을 뒤집어 패터닝된 이방성 도전막과 패드부를 갖는 유리패널을 정렬하고 압착하여 접속하는 단계와, 상기 압착된 IC칩을 견고하게 접속되도록 상기 패터닝된 이방성 도전막을 경화하는 단계를 포함한다. 본 발명은 이방성 도전막이 형성된 IC칩과 유리패널의 패드부가 직접 접촉함으로써, 유리 패널의 패드부 방향으로만 통전되고 IC칩과 IC칩, 유리 패널과 유리 패널 각각의 방향으로는 절연되므로 패턴의 미세화에 추세에 대응하여 좌우통전에 의한 쇼트를 방지할 수 있다.A method of mounting a chip-shaped element in which an IC chip having an anisotropic conductive film (ACF) is mounted on a panel is disclosed. The chip type device mounting method of the present invention comprises the steps of forming a pad pattern on an IC chip, forming an insulating film exposing the pad pattern on the IC chip, and an anisotropic conductive layer having a protective film on the pad pattern and the insulating film. Attaching a film, heating the anisotropic conductive film through the pad pattern, removing the anisotropic conductive film having the unheated protective film to form a patterned anisotropic conductive film on the pad pattern, and forming the IC chip. Arranging and pressing the glass panel having the patterned anisotropic conductive film and the pad portion by turning over, and curing the patterned anisotropic conductive film to firmly connect the compressed IC chip. According to the present invention, the IC chip on which the anisotropic conductive film is formed and the pad portion of the glass panel are directly in contact with each other, so that only the pad portion of the glass panel is energized and insulated in each of the IC chip, IC chip, glass panel, and glass panel, thereby miniaturizing the pattern. In response to the trend, short circuits due to left and right energization can be prevented.
Description
제1도 내지 제4도는 본 발명에 따른 칩형 소자의 실장방법을 설명하기 위하여 도시한 단면도들이다.1 through 4 are cross-sectional views illustrating a method of mounting a chip type device according to the present invention.
본 발명은 칩형 소자의 실장방법에 관한 것으로, 보다 상세하게는 이방성 도전막(ACF: anisotropic conductive film)을 갖는 IC 칩을 패널에 실장하는 칩형 소자의 실장방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a chip element, and more particularly, to a method of mounting a chip element in which an IC chip having an anisotropic conductive film (ACF) is mounted on a panel.
일반적으로, 이방성 도전막을 사용한 실장방법은 주로 LCD의 외부단자와 TCP(tape carrier package)의 단자를 접속시키는데 사용되어 왔으나, 히다지 케미칼사와 소니 케미칼사는 이방성 도전막을 COG기술에 적용하였다.In general, a mounting method using an anisotropic conductive film has been mainly used to connect an external terminal of the LCD and a terminal of a TCP (tape carrier package), but Hitachi Chemical and Sony Chemical have applied an anisotropic conductive film to COG technology.
먼저, 히다지 케미칼사의 이방성도전막을 이용한 COG(chip on glass)구조를 살펴보면, 절연막이 부착되어 있는 이방성 도전막을 유리패널 상에 부착한다. 이어서, 유리 패널과 IC칩의 패드(pad)들을 얼라인시켜 적당한 압력으로 IC칩을 눌러 절연막을 파괴시켜 IC칩과 유리 패널을 통전시킨다. 이러한 방법은 상기 이방성 도전막 상에 절연막을 형성하기 어렵고, 더욱이 상기 실장시 압력을 조절하는데 어려운 문제점이 있다.First, a COG (chip on glass) structure using an anisotropic conductive film manufactured by Hidaji Chemical Co., Ltd. is attached to the glass panel. Subsequently, the pads of the glass panel and the IC chip are aligned, and the IC chip is pressed at an appropriate pressure to break the insulating film to conduct the IC chip and the glass panel. This method has a problem that it is difficult to form an insulating film on the anisotropic conductive film, and furthermore, it is difficult to control the pressure during the mounting.
다음에, 소니 케미칼사의 이방성도전막을 사용한 COG구조를 살펴보면, 표면에 절연막이 형성된 도전입자가 들어있는 이방성도전막을 부착한후 유리 패널과 IC칩의 패드(pad)들을 얼라인시켜 적당한 압력으로 IC칩을 눌러 IC칩과 유리 패널을 통전시킨다. 이렇게 되면, 미세 피치화에 따른 좌우간 통전을 방지하면서 유리 패널과 IC칩의 전기적 접촉을 이루게 된다. 이러한 방법은 상기 절연막의 형성이 어렵고 절연막 형성에 따른 단가가 상승하는 문제점이 있다.Next, look at the COG structure using the anisotropic conductive film of Sony Chemical Company, after attaching an anisotropic conductive film containing conductive particles formed with an insulating film on the surface, and then align the pads of the glass panel and the IC chip to the appropriate pressure Press to energize the IC chip and glass panel. In this case, electrical contact between the glass panel and the IC chip is achieved while preventing the left and right conduction caused by the fine pitch. This method has a problem in that the formation of the insulating film is difficult and the unit cost increases due to the formation of the insulating film.
따라서, 본 발명의 목적은 상기와 같은 문제점을 개선하기 위하여 이방성 도전막이 형성된 IC칩을 유리 패널의 패드에 직접 접촉하여 유리패널과 IC칩을 통전시킬 수 있는 칩형 소자의 실장 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a method of mounting a chip-type device capable of energizing the glass panel and the IC chip by directly contacting the pad of the glass panel with an IC chip formed with an anisotropic conductive film to improve the above problems. .
상기 목적을 달성하기 위하여 본 발명의 칩형 소자 실장 방법은 IC칩상에 패드 패턴을 형성하는 단계와, 상기 IC칩 상에 상기 패드패턴을 노출하는 절연막을 형성하는 단계와, 상기 패드 패턴 및 절연막 상에 보호막을 갖는 이방성 도전막을 부착하는 단계와, 상기 패드패턴을 통하여 상기 이방성 도전막을 가열시키는 단계와, 상기 가열되지 않은 보호막을 갖는 이방성 도전막을 제거하여 상기 패드패턴 상에 패터닝된 이방성 도전막을 형성하는 단계와, 상기 IC칩을 뒤집어 패터닝된 이방성 도전막과 패드부를 갖는 유리패널을 정렬하고 압착하여 접속하는 단계와, 상기 압착된 IC칩을 견고하게 접속되도록 상기 패터닝된 이방성 도전막을 경화하는 단계를 포함한다.In order to achieve the above object, the chip type device mounting method of the present invention includes forming a pad pattern on an IC chip, forming an insulating film exposing the pad pattern on the IC chip, and forming a pad pattern on the pad pattern and the insulating film. Attaching an anisotropic conductive film having a protective film, heating the anisotropic conductive film through the pad pattern, and removing the anisotropic conductive film having the unheated protective film to form a patterned anisotropic conductive film on the pad pattern. And aligning, pressing, and connecting the patterned anisotropic conductive film and the glass panel having the pad portion by inverting the IC chip, and curing the patterned anisotropic conductive film so as to firmly connect the compressed IC chip. .
상기 패드 패턴의 재료로 Au, ITO, Ni 및 Al중에서 선택된 적어도 어느 하나를 사용하며, 상기 이방성 도전자의 경화는 상기 유리 패널을 통한 자외선 조사 및 열조사 중에서 선택된 적어도 어느 하나를 사용한다.At least one selected from Au, ITO, Ni, and Al is used as the material of the pad pattern, and the curing of the anisotropic conductor uses at least one selected from ultraviolet irradiation and heat irradiation through the glass panel.
본 발명은 이방성 도전막이 형성된 IC칩과 유리패널의 패드부가 직접 접촉함으로써, 유리 패널의 패드부 방향으로만 통전되고 IC칩과 IC칩, 유리 패널과 유리 패널 각각의 방향으로는 절연되므로 패턴의 미세화에 추세에 대응하여 좌우통전에 의한 쇼트를 방지할 수 있다.According to the present invention, the IC chip on which the anisotropic conductive film is formed and the pad portion of the glass panel are directly in contact with each other, so that only the pad portion of the glass panel is energized and insulated in each of the IC chip, IC chip, glass panel, and glass panel, thereby miniaturizing the pattern In response to the trend, short circuits due to left and right energization can be prevented.
이하, 첨부도면을 참조하여 본 발명의 실시예에 따른 칩형 소자 실장 방법을 설명한다.Hereinafter, a chip type device mounting method according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.
제1도 내지 제4도는 본 발명에 따른 칩형 소자의 실장방법을 설명하기 위하여 도시한 단면도들이다.1 through 4 are cross-sectional views illustrating a method of mounting a chip type device according to the present invention.
제1도는 IC칩(1) 상에 패드 패턴(3)을 노출하는 절연막(5), 보호막(9)을 갖는 이방성 도전막(7)을 형성하는 단계를 나타낸다.FIG. 1 shows a step of forming an anisotropic conductive film 7 having an insulating film 5 and a protective film 9 exposing the pad pattern 3 on the IC chip 1.
구체적으로, IC칩(1) 상면에 패드 패턴(3)을 형성한다. 상기 패드 패턴(3)의 재료로는 Au, Ni, Al, ITO(Indium Tin Oxide) 등을 쓴다.Specifically, the pad pattern 3 is formed on the upper surface of the IC chip 1. As the material of the pad pattern 3, Au, Ni, Al, ITO (Indium Tin Oxide) or the like is used.
이어서, 상기 패드 패턴(3)이 형성된 Ic칩(1)의 전면에 절연물질을 도포한 후 패터닝하여 상기 패드패턴(3)을 노출하는 절연막(5)을 형성한다.Subsequently, an insulating material is coated on the entire surface of the Ic chip 1 on which the pad pattern 3 is formed, and then patterned to form an insulating film 5 exposing the pad pattern 3.
계속하여, 상기 패드패턴(3) 및 절연막(5) 상에 보호막(9)을 갖는 이방성 도전막(7)을 부착시킨다. 이 이방성 도전막(7)은 그 내부에 도전입자들이 포함되어 있으며, 접착성도 함께 가진다.Subsequently, an anisotropic conductive film 7 having a protective film 9 is attached onto the pad pattern 3 and the insulating film 5. The anisotropic conductive film 7 contains conductive particles therein and also has adhesiveness.
제2도는 이방성 도전막(7)을 가열하는 단계를 나타낸다.2 shows a step of heating the anisotropic conductive film 7.
구체적으로, 상기 IC칩(1)의 패드 패턴(3)을 통하여 상기 이방성 도전막(5)을 가열한다.Specifically, the anisotropic conductive film 5 is heated through the pad pattern 3 of the IC chip 1.
제3도는 가열되지 않은 보호막(9)을 갖는 이방성 도전막(7)을 제거하는 단계를 나타낸다. 구체적으로, 상기 패드 패턴(3)을 통하여 가열되지 않은 보호막(9)을 갖는 이방성 도전막(7)을 제거한다. 이렇게 되면, 상기 패드 패턴(3) 상에 패터닝된 이방성 도전막(9a)이 형성된다.3 shows a step of removing the anisotropic conductive film 7 having the unheated protective film 9. Specifically, the anisotropic conductive film 7 having the unheated protective film 9 is removed through the pad pattern 3. In this case, the patterned anisotropic conductive film 9a is formed on the pad pattern 3.
제4도는 IC칩(1)을 패드부(13)가 형성된 유리패널(11)에 정렬 압착한 후 패터닝된 이방성 도전막(9a)을 경화하는 단계를 나타낸다.FIG. 4 shows a step of curing the patterned anisotropic conductive film 9a after the IC chip 1 is aligned and crimped on the glass panel 11 having the pad portion 13 formed thereon.
구체적으로, 패터닝된 이방성 도전막을 갖는 IC칩(1)을 뒤집어서 패드부(13)가 형성된 유리패널(11) 상에 정렬하여 압착한다. 본 실시예에서는 유리패널(11) 상에 패드부(13)만 형성되어 있으나, 패드부(13)을 노출하는 절연막(도시 안됨)이 형성되어 있을 수 있다.Specifically, the IC chip 1 having the patterned anisotropic conductive film is turned upside down and aligned on the glass panel 11 where the pad portion 13 is formed to be pressed. In the present exemplary embodiment, only the pad part 13 is formed on the glass panel 11, but an insulating film (not shown) exposing the pad part 13 may be formed.
다음으로, 얼라인된 유리 패널(1)을 통하여 자외선 조사, 열조사 또는 자외선 조사와 열조사를 혼용하여 패터닝된 이방성 도전막을 경화시킴으로써 접속을 견고히 하여 본 접착 공정을 완료한다.Next, the connection is completed by hardening the patterned anisotropic conductive film by mixing ultraviolet irradiation, heat irradiation, or ultraviolet irradiation and heat irradiation through the aligned glass panel 1 to complete the present bonding process.
상술한 바와 같이, 본 발명에 따른 IC칩의 실장 방법은 종래기술의 특수한 이방성 도전막이 아닌 통상의 이방성 도전막을 사용하고, IC칩의 패드 패턴상에 범프를 형성하지 않음으로써 원가를 절감하는 효과가 있다.As described above, the IC chip mounting method according to the present invention uses a conventional anisotropic conductive film instead of the special anisotropic conductive film of the prior art, and has the effect of reducing the cost by not forming a bump on the pad pattern of the IC chip. have.
또한, 본 발명은 IC칩 상의 패드 패턴 상에 형성된 패터닝된 이방성 도전막을 통하여 IC칩과 유리 패널의 패드부 방향으로만 통전되고 IC칩과 IC칩, 유리 패널과 유리패널 각각의 방향으로는 절연되므로 패턴의 미세화에 추세에 대응하여 좌우통전에 의한 쇼트를 방지할 수 있다.In addition, the present invention is energized only in the direction of the pad portion of the IC chip and the glass panel through the patterned anisotropic conductive film formed on the pad pattern on the IC chip and insulated in each direction of the IC chip, IC chip, glass panel and glass panel. In response to a trend in miniaturization of the pattern, short circuits due to left and right energization can be prevented.
이상, 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 당업자의 통상적인 지식의 범위에서 그 변형이나 개량이 가능하다.As mentioned above, although this invention was demonstrated concretely, this invention is not limited to this, A deformation | transformation and improvement are possible in the range of the common knowledge of a person skilled in the art.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950028507A KR100188707B1 (en) | 1995-08-31 | 1995-08-31 | Mounting method of chip device using bidirectional conductive film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950028507A KR100188707B1 (en) | 1995-08-31 | 1995-08-31 | Mounting method of chip device using bidirectional conductive film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970013000A KR970013000A (en) | 1997-03-29 |
| KR100188707B1 true KR100188707B1 (en) | 1999-06-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950028507A KR100188707B1 (en) | 1995-08-31 | 1995-08-31 | Mounting method of chip device using bidirectional conductive film |
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| Country | Link |
|---|---|
| KR (1) | KR100188707B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980017398A (en) * | 1996-08-30 | 1998-06-05 | 김광호 | Attaching Drive IC for Liquid Crystal Display Devices |
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1995
- 1995-08-31 KR KR1019950028507A patent/KR100188707B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970013000A (en) | 1997-03-29 |
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