JPH04254343A - Packaging method of semiconductor device - Google Patents
Packaging method of semiconductor deviceInfo
- Publication number
- JPH04254343A JPH04254343A JP1518991A JP1518991A JPH04254343A JP H04254343 A JPH04254343 A JP H04254343A JP 1518991 A JP1518991 A JP 1518991A JP 1518991 A JP1518991 A JP 1518991A JP H04254343 A JPH04254343 A JP H04254343A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- heat
- resin
- electrode
- lsi chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000000034 method Methods 0.000 title claims description 22
- 238000004806 packaging method and process Methods 0.000 title 1
- 229920005989 resin Polymers 0.000 claims abstract description 52
- 239000011347 resin Substances 0.000 claims abstract description 52
- 229920006257 Heat-shrinkable film Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 10
- 230000008602 contraction Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 239000011521 glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83859—Localised curing of parts of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83874—Ultraviolet [UV] curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体の実装方式であ
るＣＯＢ実装に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to COB mounting, which is a semiconductor mounting method.
【０００２】0002
【従来の技術】 近年、半導
体素子は益々大型化、多ピン化、狭ピッチ化の傾向にあ
り、これらの半導体素子を以下に高密度に実装するかが
最重要課題となっている。この高密度化を図る方法のひ
とつとしてＣＯＢ実装方式がある。BACKGROUND OF THE INVENTION In recent years, semiconductor devices have become increasingly larger, have more pins, and have a narrower pitch, and the most important issue is how to package these semiconductor devices with higher density. One of the methods for achieving this high density is the COB mounting method.
【０００３】従来のＣＯＢ実装方式としては、例えばマ
イクロバンプボンディング方式（ＭＢＢ実装）がある。
従来のＭＢＢ実装方式を図３、図４とともに説明する。[0003] As a conventional COB mounting method, for example, there is a micro bump bonding method (MBB mounting). A conventional MBB mounting method will be explained with reference to FIGS. 3 and 4.
【０００４】まず接続後の断面を図３（ａ）に示す。Ｍ
ＢＢ実装方式はＬＳＩ電極３０に金属突起３１（以下バ
ンプと呼ぶ。）を有したＬＳＩチップ３２、回路基板３
３、光硬化性絶縁樹脂３５の３つの要素から構成される
。ＬＳＩチップ３２は、光硬化性絶縁樹脂３５によりフ
ェースダウンで回路基板３３に固定され、ＬＳＩチップ
３２のバンプ３１と回路基板の電極３４は光硬化性絶縁
樹脂３５の収縮力により、圧接接合される。図３（ｂ）
に接続原理を示す。ＬＳＩチップ３２と回路基板３３間
のギャップｈは、バンプ３１の厚みで規制されるが、こ
の状態で光硬化性絶縁樹脂３５を硬化すると、Δｈの収
縮量をもった状態で収縮力Ｗが作用する。また、ＬＳＩ
チップ３２と光硬化性絶縁樹脂３５および回路基板３３
と光硬化性絶縁樹脂３５間は各々の密着力α、βが作用
しているためバンプ３１と回路基板の電極３４同士は圧
接・接続される。First, a cross section after connection is shown in FIG. 3(a). M
The BB mounting method includes an LSI chip 32 having metal protrusions 31 (hereinafter referred to as bumps) on an LSI electrode 30, and a circuit board 3.
3. It is composed of three elements: photocurable insulating resin 35. The LSI chip 32 is fixed face down to the circuit board 33 by a photocurable insulating resin 35, and the bumps 31 of the LSI chip 32 and the electrodes 34 of the circuit board are pressure-bonded by the contractile force of the photocurable insulating resin 35. . Figure 3(b)
shows the connection principle. The gap h between the LSI chip 32 and the circuit board 33 is regulated by the thickness of the bump 31, but when the photocurable insulating resin 35 is cured in this state, a shrinkage force W acts with a shrinkage amount of Δh. do. Also, LSI
Chip 32, photocurable insulating resin 35, and circuit board 33
Since adhesion forces α and β act between the bumps 31 and the photocurable insulating resin 35, the bumps 31 and the electrodes 34 of the circuit board are pressed together and connected.
【０００５】図４はＭＢＢ実装方式のプロセスを示す。
まず回路基板３３上もしくはＬＳＩチップ３２側に光硬
化性絶縁樹脂３５をディスペンサなどで滴下する（ａ）
。ついで、ＬＳＩチップ３２のバンプ３１と回路基板の
電極３４とを位置合わせする（ｂ）。この位置合わせは
、回路基板３３がガラス板であればガラス板側から行い
、不透明基板であれば２個のカメラでＬＳＩチップ３２
面と回路基板３３面の両方のパターンを認識させ合体さ
せる。位置合わせが終わると、ＬＳＩチップ３２を加圧
する（ｃ）。この加圧により光硬化性絶縁樹脂３５はＬ
ＳＩチップ３２のバンプ３１と回路基板の電極３４の間
から排出され、バンプ３１と回路基板の電極３４は電気
的に接触する。次に紫外光ＵＶ光を照射して光硬化性絶
縁樹脂３５を硬化させる（ｄ）。このとき基板３３がガ
ラス等の透明なものであれば（ｅ）のごとく裏面からＵ
Ｖ光を照射してもよい。硬化が終了してから加圧治具３
６を取り去るとＬＳＩチップ３２と回路基板の電極３４
との接続が完了する（ｆ）。このように、ＬＳＩチップ
３２の回路基板３３への実装が完了する。FIG. 4 shows the process of the MBB implementation method. First, drop the photocurable insulating resin 35 onto the circuit board 33 or the LSI chip 32 side using a dispenser or the like (a)
. Next, the bumps 31 of the LSI chip 32 and the electrodes 34 of the circuit board are aligned (b). If the circuit board 33 is a glass plate, this alignment is performed from the glass plate side; if the circuit board 33 is an opaque board, two cameras are used to perform this alignment.
The patterns on both the surface and the surface of the circuit board 33 are recognized and combined. When the alignment is completed, pressure is applied to the LSI chip 32 (c). Due to this pressurization, the photocurable insulating resin 35 is
It is discharged from between the bumps 31 of the SI chip 32 and the electrodes 34 of the circuit board, and the bumps 31 and the electrodes 34 of the circuit board come into electrical contact. Next, the photocurable insulating resin 35 is cured by irradiating ultraviolet light (d). At this time, if the substrate 33 is transparent such as glass, the U from the back side as shown in (e).
V light may be irradiated. Pressure jig 3 after curing is completed.
6 is removed, the LSI chip 32 and the electrode 34 of the circuit board are removed.
The connection with is completed (f). In this way, the mounting of the LSI chip 32 onto the circuit board 33 is completed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら従来例に
おいては以下のような問題点がある。However, the conventional example has the following problems.
【０００７】回路基板３３とＬＳＩチップ３２とを加圧
接続するとき加圧治具３６と回路基板３３、ＬＳＩチッ
プ３２との間の平行度を保つのが難しくバンプ３１と回
路基板の電極３４との間に接続不良が起こりやすい。ま
た、光硬化性樹脂３５がＬＳＩチップ３２やまわりの雰
囲気の温度上昇により熱膨張し、そのためにバンプ３１
が回路基板の電極３４から離れ接続不良を起こすという
問題点を有していた。When connecting the circuit board 33 and the LSI chip 32 by pressure, it is difficult to maintain parallelism between the pressure jig 36, the circuit board 33, and the LSI chip 32, and the bumps 31 and the electrodes 34 of the circuit board Poor connection is likely to occur during this time. In addition, the photocurable resin 35 thermally expands due to the temperature rise of the LSI chip 32 and the surrounding atmosphere, so that the bumps 31
There was a problem in that the electrodes separated from the electrodes 34 of the circuit board, causing poor connection.
【０００８】本発明は上記問題点に鑑み、バンプと回路
基板の電極とを接続不良無く接続する方法を提供するも
のである。In view of the above problems, the present invention provides a method for connecting bumps and electrodes of a circuit board without causing connection failure.
【０００９】[0009]
【課題を解決するための手段】本発明は、絶縁基板上に
半導体素子の電極に対応した位置に電極配線を形成し、
前記基板の電極配線部に光硬化性絶縁樹脂をを塗布し、
前記光硬化性絶縁樹脂上に前記電極配線以外の部分に熱
収縮性樹脂を載せ、前記熱収縮性樹脂上に更に光硬化性
樹脂を塗布した後、前記電極配線に対応した電極部に金
属突起を有する半導体導体素子の金属突起と前記電極配
線を位置合わせし、前記光硬化性樹脂を硬化させ前記基
板と半導体素子を接合した後、前記半導体素子を接合し
た基板を熱処理し、前記熱収縮性樹脂を収縮させ、前記
熱収縮性樹脂の収縮力により前記半導体素子の金属突起
と前記基板の電極配線をしっかりと接触させる方法を提
供する。前記熱収縮性樹脂には熱収縮性フィルムを用い
るのが望ましい。[Means for Solving the Problems] The present invention forms electrode wiring on an insulating substrate at a position corresponding to the electrode of a semiconductor element,
Applying a photocurable insulating resin to the electrode wiring part of the substrate,
A heat-shrinkable resin is placed on the photocurable insulating resin in areas other than the electrode wiring, and a photocurable resin is further coated on the heat-shrinkable resin, and then metal protrusions are placed on the electrode portions corresponding to the electrode wiring. After aligning the metal protrusions of the semiconductor conductor element having the heat-shrinkable property with the electrode wiring, curing the photocurable resin, and bonding the substrate and the semiconductor element, the substrate to which the semiconductor element has been bonded is heat-treated, and the heat-shrinkable A method is provided in which a resin is contracted and the metal protrusions of the semiconductor element are brought into firm contact with the electrode wiring of the substrate by the contraction force of the heat-shrinkable resin. It is desirable to use a heat-shrinkable film as the heat-shrinkable resin.
【００１０】0010
【作用】本発明のごとく、絶縁性光硬化性樹脂の間に熱
収縮性フィルムを入れ、熱収縮性フィルムの収縮力によ
って電極配線とバンプを接触させることにより、電極配
線とバンプとを接続不良無く容易に接続することができ
る。[Operation] According to the present invention, a heat-shrinkable film is placed between insulating photocurable resins, and the electrode wiring and bumps are brought into contact with each other by the shrinkage force of the heat-shrinkable film, resulting in poor connection between the electrode wiring and the bumps. It can be easily connected without any problems.
【００１１】[0011]
【実施例】以下本発明の一実施例にかかる方法を図１、
図２とともに説明する。[Example] A method according to an embodiment of the present invention will be described below with reference to FIG.
This will be explained in conjunction with FIG.
【００１２】まず接続後の断面を図１（ａ）に示す。本
発明は、ＬＳＩ電極１にバンプ２を有したＬＳＩチップ
３、回路基板４、光硬化性等の絶縁樹脂６および熱収縮
性フィルム７の４つの要素から構成される。バンプ２は
、例えばＡｕを用い、回路基板の電極５は例えはＴｉ−
Ｐｄ−Ａｕの３層膜を用いる。ＬＳＩチップ３は、光硬
化性絶縁樹脂６によりフェースダウンで回路基板４に固
定され、ＬＳＩチップ３のバンプ２と回路基板の電極５
は光硬化性絶縁樹脂６の収縮力により、接触させられる
。この後、全体を熱処理する事により熱収縮性フィルム
７の収縮力によりＬＳＩチップ３のバンプ２と回路基板
の電極５は更にしっかりと接触させられる。このとき熱
硬化性フィルム７は回路基板の電極５やバンプ２の位置
まで広がらない量とする。図１（ｂ）に接続原理を示す
。ＬＳＩチップ３と回路基板４間のギャップｈは、バン
プ２の厚みで規制されるが、この状態で光硬化性絶縁樹
脂６を硬化すると、Δｈ１の収縮量をもった状態で収縮
力Ｗ１が作用する。また、ＬＳＩチップ３と光硬化性絶
縁樹脂６および回路基板４と光硬化性絶縁樹脂６間は各
々の密着力α、βが作用しているためバンプ２と回路基
板の電極５同士は圧接・接触させられる。次に熱処理を
行うことにより熱収縮性フィルム７が収縮し、更に△ｈ
２の収縮量をもった状態で収縮力Ｗ２が作用し、バンプ
２と回路基板の電極５同士を強く圧接する。この時、収
縮量△ｈ２のおよび収縮力Ｗ２は、光硬化性絶縁樹脂６
の熱膨張力−△ｈ３および膨張量−Ｗ３よりも大きなも
のを用いる。First, a cross section after connection is shown in FIG. 1(a). The present invention is composed of four elements: an LSI chip 3 having bumps 2 on an LSI electrode 1, a circuit board 4, an insulating resin 6 such as a photocurable resin, and a heat-shrinkable film 7. The bumps 2 are made of, for example, Au, and the electrodes 5 of the circuit board are made of, for example, Ti-
A three-layer film of Pd-Au is used. The LSI chip 3 is fixed face down to the circuit board 4 by a photocurable insulating resin 6, and the bumps 2 of the LSI chip 3 and the electrodes 5 of the circuit board
are brought into contact by the contraction force of the photocurable insulating resin 6. Thereafter, by heat-treating the entire structure, the bumps 2 of the LSI chip 3 and the electrodes 5 of the circuit board are brought into even more firm contact due to the contraction force of the heat-shrinkable film 7. At this time, the amount of thermosetting film 7 is set so that it does not spread to the positions of electrodes 5 and bumps 2 of the circuit board. Figure 1(b) shows the connection principle. The gap h between the LSI chip 3 and the circuit board 4 is regulated by the thickness of the bump 2, but when the photocurable insulating resin 6 is cured in this state, a shrinkage force W1 acts with a shrinkage amount of Δh1. do. Furthermore, since adhesion forces α and β act between the LSI chip 3 and the photocurable insulating resin 6 and between the circuit board 4 and the photocurable insulating resin 6, the bumps 2 and the electrodes 5 of the circuit board are pressed together. be brought into contact. Next, by performing heat treatment, the heat-shrinkable film 7 shrinks, and further △h
A contraction force W2 acts with a contraction amount of 2, strongly pressing the bumps 2 and the electrodes 5 of the circuit board together. At this time, the shrinkage amount △h2 and the shrinkage force W2 of the photocurable insulating resin 6
The thermal expansion force -Δh3 and the amount of expansion -W3 are used.
【００１３】図２は本発明における実装方式のプロセス
を示す。まず回路基板４に光硬化性絶縁樹脂６をディス
ペンサなどで滴下する（ａ）。ついで、熱収縮性フィル
ム７を回路基板４上の光硬化性樹脂６の上に載せ、さら
に、熱収縮性フィルム７上に光硬化性絶縁樹脂６を滴下
する。このとき熱収縮性フィルム７はバンプ２や回路基
板の電極５を覆わない量とする（ｂ）。ついで、ＬＳＩ
チップ３のバンプ２と回路基板の電極５とを位置合わせ
する（ｃ）。この位置合わせは、回路基板４がガラス板
であればガラス板側から行い、不透明基板であれば２個
のカメラでＬＳＩチップ３面と回路基板４面の両方のパ
ターンを認識させ合体させる。位置合わせが終わると、
ＬＳＩチップ３を加圧する。この加圧によりバンプ２と
回路基板の電極５は電気的にほぼ接触する。次に光硬化
性絶縁樹脂６を例えば（ｄ）のごとくＵＶ光を照射して
硬化させる。なお、基板４が透明の場合は、（ｅ）のご
とく裏面からＵＶ光を照射してもよい。硬化が終了して
から加圧治具８を取り去るとＬＳＩチップ３と回路基板
４との接続が完了する。このあとＬＳＩチップ３の接合
された回路基板４を熱処理し熱収縮性フィルム７を収縮
させ、さらにしっかりとＬＳＩチップ３のバンプ２と回
路基板の電極５とを接触させ、ＬＳＩチップ３の回路基
板４への実装が完了する（ｆ）。FIG. 2 shows the process of implementation in the present invention. First, photocurable insulating resin 6 is dropped onto circuit board 4 using a dispenser or the like (a). Next, the heat-shrinkable film 7 is placed on the photocurable resin 6 on the circuit board 4, and the photocurable insulating resin 6 is further dropped onto the heat-shrinkable film 7. At this time, the amount of heat-shrinkable film 7 is set so as not to cover bumps 2 and electrodes 5 of the circuit board (b). Next, LSI
The bumps 2 of the chip 3 and the electrodes 5 of the circuit board are aligned (c). If the circuit board 4 is a glass plate, this alignment is performed from the glass plate side, and if the circuit board 4 is an opaque substrate, two cameras are used to recognize the patterns on both the LSI chip 3 surface and the circuit board 4 surface, and the patterns are combined. Once the alignment is complete,
Pressurize the LSI chip 3. This pressurization brings the bumps 2 and the electrodes 5 of the circuit board into almost electrical contact. Next, the photocurable insulating resin 6 is cured by irradiating it with UV light, for example as shown in (d). Note that when the substrate 4 is transparent, UV light may be irradiated from the back side as shown in (e). When the pressing jig 8 is removed after curing is completed, the connection between the LSI chip 3 and the circuit board 4 is completed. After that, the circuit board 4 to which the LSI chip 3 is bonded is heat-treated to shrink the heat-shrinkable film 7, and the bumps 2 of the LSI chip 3 are brought into firm contact with the electrodes 5 of the circuit board. 4 is completed (f).
【００１４】その効果について従来例との比較を（表１
）に示す。[0014] The effect is compared with the conventional example (Table 1
).
【００１５】[0015]
【表１】[Table 1]
【００１６】以上の方法により、加圧治具７とＬＳＩチ
ップ３、および回路基板４との平行度の不十分さによる
バンプ２と回路基板の電極５との接続不良、および光硬
化性樹脂６がＬＳＩチップ３やまわりの雰囲気の温度上
昇により熱膨張し、そのためにバンプ３１が回路基板の
電極３４から離れ接続不良を起こすという問題を著しく
減少させることができる。By the above method, connection failure between the bumps 2 and the electrodes 5 of the circuit board due to insufficient parallelism between the pressure jig 7, the LSI chip 3, and the circuit board 4, and the photocurable resin 6 can be avoided. It is possible to significantly reduce the problem of the bumps 31 being separated from the electrodes 34 of the circuit board and causing connection failures due to thermal expansion due to the temperature rise of the LSI chip 3 and the surrounding atmosphere.
【００１７】[0017]
【発明の効果】以上のように本発明は、絶縁基板上に半
導体素子の電極に対応した位置に電極配線を形成し、前
記基板の電極配線部に光硬化性絶縁樹脂をを塗布し、前
記光硬化性絶縁樹脂上に前記電極配線以外の部分に熱収
縮性フィルムを載せ、前記熱収縮性フィルム上に更に光
硬化性樹脂を塗布した後、前記電極配線に対応した電極
部に金属突起を有する半導体導体素子の金属突起と前記
電極配線を位置合わせし、前記光硬化性樹脂を硬化させ
前記基板と半導体素子を接合した後、前記半導体素子を
接合した基板を熱処理し、前記熱収縮性フィルムを収縮
させ、前記熱収縮性フィルムの収縮力により前記半導体
素子の金属突起と前記基板の電極配線をしっかりと接触
させる方法を用いることにより、回路基板とＬＳＩチッ
プとを加圧接続するときの加圧治具と回路基板、ＬＳＩ
チップとの間の平行度の不十分さによるバンプと回路基
板の電極との間に接続不良や、光硬化性絶縁樹脂がＬＳ
Ｉチップやまわりの雰囲気の温度上昇により熱膨張し、
そのためにバンプが回路基板の電極から離れ接続不良を
起こすという問題点を著しく減少させることができ、半
導体装置の実装に十分寄与するものである。As described above, in the present invention, electrode wiring is formed on an insulating substrate at a position corresponding to the electrode of a semiconductor element, and a photocurable insulating resin is applied to the electrode wiring portion of the substrate. A heat-shrinkable film is placed on a portion other than the electrode wiring on the photocurable insulating resin, and a photocurable resin is further applied on the heat-shrinkable film, and then metal protrusions are formed on the electrode portions corresponding to the electrode wiring. After aligning the metal protrusions of the semiconductor conductor element and the electrode wiring, curing the photocurable resin and bonding the substrate and semiconductor element, the substrate to which the semiconductor element is bonded is heat-treated, and the heat-shrinkable film is bonded to the substrate. By using a method in which the metal protrusions of the semiconductor element and the electrode wiring of the substrate are brought into firm contact by the contraction force of the heat-shrinkable film, the application of pressure when connecting the circuit board and the LSI chip is reduced. Pressing jig, circuit board, LSI
There may be poor connection between the bump and the circuit board electrode due to insufficient parallelism between the chip and the photocurable insulating resin.
Thermal expansion occurs due to the rise in temperature of the I-chip and the surrounding atmosphere.
Therefore, it is possible to significantly reduce the problem of the bumps separating from the electrodes of the circuit board and causing poor connection, and this contributes sufficiently to the mounting of semiconductor devices.
【図１】本発明の一実施例における半導体素子を基板に
実装したときの断面図、および接続原理図である。FIG. 1 is a cross-sectional view and a connection principle diagram when a semiconductor element is mounted on a substrate in an embodiment of the present invention.
【図２】同実施例における実装方式のプロセス工程断面
図である。FIG. 2 is a process step cross-sectional view of the mounting method in the same embodiment.
【図３】従来例において半導体素子を実装したときの断
面図、および接続原理図である。FIG. 3 is a cross-sectional view and a connection principle diagram when a semiconductor element is mounted in a conventional example.
【図４】従来例における実装方式のプロセス工程断面図
である。FIG. 4 is a cross-sectional view of a process step of a mounting method in a conventional example.
１ ＬＳＩ電極 ２ バンプ ３ ＬＳＩチップ ４ 回路基板 ５ 回路基板の電極 ６ 光硬化性絶縁樹脂 ７ 熱収縮性フィルム ８ 加圧治具 1 LSI electrode 2 Bump 3 LSI chip 4 Circuit board 5. Circuit board electrodes 6 Photo-curable insulating resin 7 Heat shrinkable film 8 Pressure jig
Claims (2)
した位置に電極配線を形成し、前記基板の電極配線部に
光硬化性絶縁樹脂をを塗布し、前記光硬化性絶縁樹脂上
に前記電極配線以外の部分に熱収縮性樹脂を載せ、前記
熱収縮性樹脂上に更に光硬化性樹脂を塗布した後、前記
電極配線に対応した電極部に金属突起を有する半導体導
体素子の金属突起と前記電極配線を位置合わせし、前記
光硬化性樹脂を硬化させ前記基板と半導体素子を接合し
た後、前記半導体素子を接合した基板を熱処理し、前記
熱収縮性樹脂を収縮させ、前記熱収縮性樹脂の収縮力に
より前記半導体素子の金属突起と前記基板の電極配線と
を電気的に接触させることを特徴とする半導体装置の半
導体装置の実装方法。1. Electrode wiring is formed on an insulating substrate at a position corresponding to the electrode of a semiconductor element, a photocurable insulating resin is applied to the electrode wiring portion of the substrate, and the photocurable insulating resin is coated on the photocurable insulating resin. A heat-shrinkable resin is placed on a portion other than the electrode wiring, and a photocurable resin is further applied on the heat-shrinkable resin, and then a metal projection of a semiconductor conductor element having a metal projection on an electrode portion corresponding to the electrode wiring is formed. After aligning the electrode wiring, curing the photocurable resin, and bonding the substrate and semiconductor element, the substrate to which the semiconductor element is bonded is heat-treated to shrink the heat-shrinkable resin. A method for mounting a semiconductor device, characterized in that metal protrusions of the semiconductor element and electrode wiring of the substrate are brought into electrical contact by the contraction force of a resin.
ることを特徴とする請求項１記載の半導体装置の実装方
法。2. The method for mounting a semiconductor device according to claim 1, wherein the heat-shrinkable resin is a heat-shrinkable film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1518991A JP2780499B2 (en) | 1991-02-06 | 1991-02-06 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1518991A JP2780499B2 (en) | 1991-02-06 | 1991-02-06 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04254343A true JPH04254343A (en) | 1992-09-09 |
| JP2780499B2 JP2780499B2 (en) | 1998-07-30 |
Family
ID=11881901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1518991A Expired - Fee Related JP2780499B2 (en) | 1991-02-06 | 1991-02-06 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780499B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270496A (en) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof |
| DE10232636A1 (en) * | 2002-07-18 | 2004-02-12 | Delo Industrieklebstoffe Gmbh & Co. Kg | Method and adhesive for flip-chip contacting |
| US7257001B2 (en) * | 2004-04-23 | 2007-08-14 | Shmuel Erez | Device and method for fastener-free connection via a heat-shrinkable insert |
| CN112968109A (en) * | 2020-11-27 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Driving back plate and manufacturing method thereof |
-
1991
- 1991-02-06 JP JP1518991A patent/JP2780499B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270496A (en) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | Electronic device, information processor, semiconductor device, semiconductor chip, and mounting method thereof |
| DE10232636A1 (en) * | 2002-07-18 | 2004-02-12 | Delo Industrieklebstoffe Gmbh & Co. Kg | Method and adhesive for flip-chip contacting |
| US7257001B2 (en) * | 2004-04-23 | 2007-08-14 | Shmuel Erez | Device and method for fastener-free connection via a heat-shrinkable insert |
| CN112968109A (en) * | 2020-11-27 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Driving back plate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2780499B2 (en) | 1998-07-30 |
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