JPH1140607A - Manufacture of semiconductor device and sealing member - Google Patents

Manufacture of semiconductor device and sealing member

Info

Publication number
JPH1140607A
JPH1140607A JP9195847A JP19584797A JPH1140607A JP H1140607 A JPH1140607 A JP H1140607A JP 9195847 A JP9195847 A JP 9195847A JP 19584797 A JP19584797 A JP 19584797A JP H1140607 A JPH1140607 A JP H1140607A
Authority
JP
Japan
Prior art keywords
manufacturing
sealing member
semiconductor chip
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9195847A
Other languages
Japanese (ja)
Other versions
JP3558498B2 (en
Inventor
Yoshinori Kanno
義則 閑野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP19584797A priority Critical patent/JP3558498B2/en
Publication of JPH1140607A publication Critical patent/JPH1140607A/en
Application granted granted Critical
Publication of JP3558498B2 publication Critical patent/JP3558498B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29017Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Abstract

PROBLEM TO BE SOLVED: To improve the reliability on humidity resistance of a semiconductor device, and further, shorten the manufacture process of the device. SOLUTION: At a semiconductor chip 11, an electrode 12 is arranged only at its peripheral section. A projection 15 is provided at the center of the face to mount the semiconductor chip 11 in the package substrate 13, that is, the section surrounded by the semiconductor electrode 12. When an anisotropic conductive film(ACF) 16 is joined onto the package substrate 13 provided with this projection 15, the surface on the side on which to mount the semiconductor chip 11 of the anisotropic conductive film(ACF) 16 becomes convex. Accordingly, when the semiconductor chip 11 is pressure-bonded from above, the semiconductor chip 11 and the anisotropic conductive film(ACF) 16 are joined in order from the center to the peripheral section.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、特にCSP(Chip Si
ze Package)及びMCM(Multi Chip Module)構造を持つ
半導体装置の製造方法に関するもの、並びに封止部材の
製造方法及び製造装置に関するものである。
The present invention relates to a CSP (Chip Si
The present invention relates to a method for manufacturing a semiconductor device having a ze Package) and an MCM (Multi Chip Module) structure, and a method and an apparatus for manufacturing a sealing member.

【0002】[0002]

【従来の技術】近年の高密度実装化に伴い、新しいパッ
ケージ構造として、半導体チップを実装する時のパッケ
ージの上面面積がほぼ半導体チップの面積に近いCSPや
1個のパッケージ基板の中に複数の半導体チップを搭載
するMCMが登場している。
2. Description of the Related Art Along with the recent high-density packaging, a new package structure has been developed in which a top surface area of a package when mounting a semiconductor chip is almost equal to the area of the semiconductor chip or a plurality of CSPs or a single package substrate. MCMs with semiconductor chips have appeared.

【0003】CSP構造を持つ半導体装置の場合について
説明する。半導体チップを搭載するための基板(以後、
パッケージ基板と呼ぶことにする。)の表面には電極が
形成されており、一方、半導体チップのパッケージ基板
と電気的に接続する方の面には、パッケージ基板上の電
極に対向する位置に電極が形成されている。これらの電
極はパッケージ基板に形成された回路によりパッケージ
基板の裏面(半導体チップを搭載しない方の面)の外部
端子である半田ボールと電気的に接続されている。パッ
ケージ基板としては、セラミック基板あるいは有機基板
が用いられる。
A case of a semiconductor device having a CSP structure will be described. Substrate for mounting semiconductor chips (hereafter,
I will call it a package substrate. An electrode is formed on the surface of the semiconductor chip, and an electrode is formed on a surface of the semiconductor chip that is electrically connected to the package substrate at a position facing the electrode on the package substrate. These electrodes are electrically connected to solder balls as external terminals on the back surface (the surface on which the semiconductor chip is not mounted) of the package substrate by a circuit formed on the package substrate. As the package substrate, a ceramic substrate or an organic substrate is used.

【0004】近年、半導体チップと基板との接合部分の
微細化が進んでおり、これらを電気的に接続するため
に、柔軟性に富んだ導電性物質、特に異方導電性フィル
ム(Anisotropic Conductive Film : ACF)を間に挟む
技術が適用されている。
In recent years, the joining portion between a semiconductor chip and a substrate has been miniaturized, and in order to electrically connect them, a conductive material having a high flexibility, especially an anisotropic conductive film (Anisotropic Conductive Film) has been used. : ACF) is applied.

【0005】この異方導電性フィルム(ACF)はその中
に微小な導電性粒子を分散させた有機フィルムであり、
半導体チップとパッケージ基板との間に挟んで圧力をか
けて固化させることによって、半導体チップの電極とパ
ッケージ基板の電極との間で導電性粒子同士を接触させ
る。この導電性粒子により、半導体チップの電極とパッ
ケージ基板の電極が電気的に接続される。
This anisotropic conductive film (ACF) is an organic film in which fine conductive particles are dispersed,
The conductive particles are brought into contact between the electrode of the semiconductor chip and the electrode of the package substrate by solidifying by applying pressure between the semiconductor chip and the package substrate. The electrodes of the semiconductor chip and the electrodes of the package substrate are electrically connected by the conductive particles.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、半導体
チップとパッケージ基板との間に上記の異方導電性フィ
ルム(ACF)を挟んで両者を電気的に接続する半導体装
置においては、異方導電性フィルム(ACF)を電極が配
置されたパッケージ基板上に接合すると、電極の厚みの
影響で異方導電性フィルム(ACF)の半導体チップとの
接合面には凹凸ができてしまう。従って、特に大型の半
導体チップを使用する場合、半導体チップと異方導電性
フィルム(ACF)との間の接合部に巻き込みボイドと呼
ばれる空気の泡が生じやすくなる。
However, in a semiconductor device in which the above-described anisotropic conductive film (ACF) is sandwiched between a semiconductor chip and a package substrate, the two are electrically connected to each other. When (ACF) is bonded to a package substrate on which electrodes are arranged, irregularities are formed on the bonding surface of the anisotropic conductive film (ACF) with the semiconductor chip due to the thickness of the electrodes. Therefore, particularly when a large-sized semiconductor chip is used, air bubbles called entrapment voids are likely to be generated at the joint between the semiconductor chip and the anisotropic conductive film (ACF).

【0007】この巻き込みボイド中には空気中の水分が
含まれており、また、大気中の水分も異方導電性フィル
ムを通して巻き込みボイド中に入ってくる。この状態で
半導体装置が高温状態になった場合、水分が蒸発して半
導体装置外部に出て行こうとする。
The entrapment void contains moisture in the air, and the moisture in the atmosphere also enters the entrapment void through the anisotropic conductive film. If the temperature of the semiconductor device becomes high in this state, the water evaporates and tries to go out of the semiconductor device.

【0008】この時、半導体装置外部に出て行くことが
できる水分量は限られているので、半導体装置外部に出
て行くことができなかった水分(蒸気)は膨張してパッ
ケージ等の破損を招く。すなわち、パッケージ基板を実
装する時の耐熱性(リフロー耐性)が劣化する。また、
基板を実装する際に前述のような問題が生じなくとも、
実際に使用する時に耐湿性の劣化を生じ、動作不良に至
る。
At this time, since the amount of moisture that can go out of the semiconductor device is limited, the moisture (steam) that cannot go out of the semiconductor device expands and damages the package and the like. Invite. That is, heat resistance (reflow resistance) when mounting the package substrate is deteriorated. Also,
Even if the above problems do not occur when mounting the board,
When actually used, the moisture resistance deteriorates, resulting in malfunction.

【0009】本発明は、上記の問題点を除去し、半導体
装置の耐湿信頼性及びリフロー耐性を向上させることを
目的とし、さらに様々な半導体チップに対して応用する
こと、装置製造工程の短縮、部材管理の軽減をも目的と
する。
An object of the present invention is to eliminate the above-mentioned problems and improve the moisture resistance reliability and reflow resistance of a semiconductor device. Further, the present invention is applicable to various semiconductor chips, shortens the device manufacturing process, The aim is to reduce the management of components.

【0010】[0010]

【課題を解決するための手段】本発明では、以下に述べ
るような手段を用いて上記の課題を解決する。半導体装
置の製造方法において、半導体装置の耐湿信頼性を向上
させるために、パッケージ基板の封止部材との接合面上
に凸部を設ける。この凸部は、パッケージ基板上の電極
で囲まれた領域内に設けられる。そして、凸部の形状
は、パッケージ基板上に接合した封止部材の形状を、半
導体チップとパッケージ基板の接合時に半導体チップの
中央部分から接合し始めて、その後半導体チップの周縁
部分に向かって順に接合していくような形状にすること
ができる形状になっている。
According to the present invention, the above-mentioned object is achieved by using the following means. In the method of manufacturing a semiconductor device, a projection is provided on a bonding surface of the package substrate with the sealing member in order to improve the humidity resistance of the semiconductor device. The protrusion is provided in a region surrounded by the electrode on the package substrate. Then, the shape of the convex portion is such that the shape of the sealing member joined on the package substrate starts to be joined from the central portion of the semiconductor chip when the semiconductor chip and the package substrate are joined, and then joined in order toward the peripheral portion of the semiconductor chip. It has a shape that can be made into a shape that can be done.

【0011】また、電極が半導体チップの片面の周縁部
のみに配置された半導体チップだけでなく、全域に配置
された半導体チップをパッケージ基板に接合する場合に
おいても、半導体装置の耐湿信頼性を向上させるため
に、半導体装置の製造方法において、中央部分の断面形
状が凸状になった封止部材を用いる。
In addition, in the case where not only a semiconductor chip in which electrodes are arranged on only one peripheral portion of a semiconductor chip but also a semiconductor chip arranged in the whole area are joined to a package substrate, the humidity resistance of the semiconductor device is improved. In order to achieve this, in the method of manufacturing a semiconductor device, a sealing member having a convex central section is used.

【0012】さらに、装置製造工程の短縮、部材管理の
軽減のために、中央部分が断面形状の封止部材を形成す
る工程と、その封止部材を挟んで半導体チップとパッケ
ージ基板を接合する工程を同一工程内で行う。
Further, a step of forming a sealing member having a central section having a cross-sectional shape, and a step of bonding a semiconductor chip and a package substrate with the sealing member interposed therebetween in order to shorten the device manufacturing process and reduce member management. In the same step.

【0013】[0013]

【発明の実施の形態】本発明の実施の形態をCSP(Chip
Size Package)に適用する場合において、以下に図を参
照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is described as a CSP (Chip).
In the case where the present invention is applied to (Size Package), description will be made below with reference to the drawings.

【0014】図1は、本発明の第1の実施の形態を示す
半導体装置の製造方法を表す。図1(a)に示すよう
に、半導体チップ11には、その周縁部分にのみ電極1
2が配置されている。一方、パッケージ基板13の半導
体チップ11を搭載する方の面(パッケージ基板の表
面)にも、半導体チップ11の電極12に対向する位置
に電極14が配置されている。そして、パッケージ基板
の電極14で囲まれた範囲(ボンディングエリア)の実
質的な中央部分には、凸部15が設けられている。この
凸部15は、パッケージ基板の半導体チップを搭載する
方の面からの高さが、その実質的な中央部分が最も高
く、その周縁部分に向かって順に低くなった形状になっ
ている。また、凸部15は、半導体チップとパッケージ
基板とを異方導電性フィルム(ACF)16を間に挟んで
電気的に接続させた時に、その凸部15の最上面と半導
体チップ11との間隔が半導体チップ11の電極12と
パッケージ基板13の電極14との間隔よりも広くなる
ように設けられている。16は異方導電性フィルム(AC
F)で、柔軟性に富み、かつ内部に微小な導電性粒子を
分散させた有機フィルムである。
FIG. 1 shows a method of manufacturing a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1A, a semiconductor chip 11 has an electrode 1 only on a peripheral portion thereof.
2 are arranged. On the other hand, the electrode 14 is also arranged on the surface of the package substrate 13 on which the semiconductor chip 11 is mounted (the surface of the package substrate) at a position facing the electrode 12 of the semiconductor chip 11. A convex portion 15 is provided at a substantial center portion of a range (bonding area) surrounded by the electrode 14 of the package substrate. The convex portion 15 has a shape in which the height from the surface of the package substrate on which the semiconductor chip is mounted is substantially highest at the substantially central portion and gradually decreases toward the peripheral edge portion. When the semiconductor chip and the package substrate are electrically connected to each other with an anisotropic conductive film (ACF) 16 interposed therebetween, the protrusion 15 is formed by a gap between the uppermost surface of the protrusion 15 and the semiconductor chip 11. Is provided so as to be wider than the distance between the electrode 12 of the semiconductor chip 11 and the electrode 14 of the package substrate 13. 16 is an anisotropic conductive film (AC
F), which is an organic film that is highly flexible and has fine conductive particles dispersed therein.

【0015】次に図1(b)に示すように、異方導電性
フィルム(ACF)16を凸部15が設けられたパッケー
ジ基板13の表面に接合させると、異方導電性フィルム
(ACF)16は、前述の凸部15の形状を反映した形状
になる。
Next, as shown in FIG. 1B, when an anisotropic conductive film (ACF) 16 is bonded to the surface of the package substrate 13 provided with the convex portions 15, the anisotropic conductive film (ACF) 16 is a shape reflecting the shape of the above-mentioned convex portion 15.

【0016】次に図1(c)に示すように、半導体チッ
プ11とパッケージ基板13と電気的に接続させるため
に両者を近付ける。この時まず、半導体チップ11の中
央部分が凸状になった異方導電性フィルム(ACF)16
と接触する。
Next, as shown in FIG. 1C, the semiconductor chip 11 and the package substrate 13 are brought close to each other for electrical connection. At this time, first, the anisotropic conductive film (ACF) 16 in which the central portion of the semiconductor chip 11 is convex
Contact with.

【0017】その後、図1(d)に示すように、さらに
半導体チップ11を上方から圧着させると、半導体チッ
プ11と異方導電性フィルム(ACF)16とがそれらの
中央部分から周縁部分に向かって順に接合していく。こ
の時同時に、半導体チップ11の中央部分から周縁部分
に向かって空気が押し出される。
Thereafter, as shown in FIG. 1 (d), when the semiconductor chip 11 is further pressed from above, the semiconductor chip 11 and the anisotropic conductive film (ACF) 16 are moved from the central portion to the peripheral portion thereof. In order. At this time, air is simultaneously pushed out from the central portion of the semiconductor chip 11 toward the peripheral portion.

【0018】従って、半導体チップ11とパッケージ基
板13との間の巻き込みボイド発生を防止することがで
きる。また、凸部15を設けることによって、その凸部
15の体積分だけ従来よりも半導体装置内部に含まれる
異方導電性フィルム(ACF)16の量を低減させること
ができる。半導体装置内部に含まれる異方導電性フィル
ム(ACF)16の量が減少すれば、異方導電性フィルム
(ACF)16の吸湿量も絶対的に減少する。
Accordingly, it is possible to prevent the occurrence of a entangled void between the semiconductor chip 11 and the package substrate 13. Further, by providing the protrusions 15, the amount of the anisotropic conductive film (ACF) 16 included in the inside of the semiconductor device can be reduced by the volume of the protrusions 15 compared to the related art. When the amount of the anisotropic conductive film (ACF) 16 contained in the semiconductor device decreases, the amount of moisture absorption of the anisotropic conductive film (ACF) 16 absolutely decreases.

【0019】また、凸部15は、半導体チップとパッケ
ージ基板とを異方導電性フィルム(ACF)16を間に挟
んで電気的に接続させた時に、その凸部15の最上面と
半導体チップ11との間隔が半導体チップ11の電極1
2とパッケージ基板13の電極14との間隔よりも広く
なるように設けられている。すなわち、半導体チップ1
1とパッケージ基板13とを、異方導電性フィルム(AC
F)16を間に挟んで電気的に接続させるために圧着さ
せても、凸部15は半導体チップ11に接触することは
ない。従って、凸部15によって半導体チップ11に損
傷や反りが発生することはない。
When the semiconductor chip and the package substrate are electrically connected to each other with an anisotropic conductive film (ACF) 16 interposed therebetween, the convex portion 15 is connected to the uppermost surface of the convex portion 15 and the semiconductor chip 11. Of the electrode 1 of the semiconductor chip 11
2 is provided so as to be wider than an interval between the electrode 2 and the electrode 14 of the package substrate 13. That is, the semiconductor chip 1
1 and the package substrate 13 are connected by an anisotropic conductive film (AC
F) The protrusion 15 does not come into contact with the semiconductor chip 11 even if the semiconductor chip 11 is press-fitted so as to be electrically connected with the interposition of the semiconductor chip 11. Therefore, the semiconductor chip 11 is not damaged or warped by the projection 15.

【0020】これらの結果、半導体チップの損傷や反り
を発生させることなく、半導体装置内に吸収される水分
量を低減、つまり半導体装置の耐湿信頼性を向上させ、
半導体装置の保管時の吸湿によるパッケージのリフロー
耐性の低下を防止することができる。
As a result, the amount of water absorbed in the semiconductor device can be reduced without damaging or warping the semiconductor chip, that is, the reliability of the semiconductor device can be improved.
It is possible to prevent a decrease in package reflow resistance due to moisture absorption during storage of the semiconductor device.

【0021】図2は、本発明の第2の実施の形態を示
す。図2(a)において、半導体チップ21とパッケー
ジ基板23には、それぞれ電極22あるいは電極24が
形成されており、電極22と電極24は対向した位置に
ある。また、これらの電極は、半導体チップ21あるい
はパッケージ基板23の周辺又は全面に位置している。
26は異方導電性フィルム(ACF)で、柔軟性に富み、
かつ内部に微小な導電性粒子を分散させた有機フィルム
である。また、異方導電性フィルム(ACF)26は、少
なくとも一つのフィルム面の中央部断面形状が凸状にな
っている。
FIG. 2 shows a second embodiment of the present invention. In FIG. 2A, an electrode 22 or an electrode 24 is formed on the semiconductor chip 21 and the package substrate 23, respectively, and the electrode 22 and the electrode 24 are located at positions facing each other. These electrodes are located around or on the entire surface of the semiconductor chip 21 or the package substrate 23.
26 is an anisotropic conductive film (ACF) which is rich in flexibility,
Further, it is an organic film in which minute conductive particles are dispersed. In addition, the anisotropic conductive film (ACF) 26 has at least one film surface having a convex central section.

【0022】次に、図2(b)に示すように、異方導電
性フィルム(ACF)26をパッケージ基板23上に接合
させた後、半導体チップ21を上方から圧着させると、
半導体チップ21と異方導電性フィルム(ACF)26が
それらの中央部分から接合し始め、その後図2(c)に
示すように、周縁部分に向かって順に接合していく。こ
の時同時に、半導体チップ21と異方導電性フィルム
(ACF)26との接合部分の中央部分から周縁部分に向
かって空気が押し出されていく。その結果、半導体チッ
プ21とパッケージ基板23との間の巻き込みボイドの
発生を防止することができ、耐湿信頼性が向上する。
Next, as shown in FIG. 2B, after the anisotropic conductive film (ACF) 26 is bonded onto the package substrate 23, the semiconductor chip 21 is pressed from above.
The semiconductor chip 21 and the anisotropic conductive film (ACF) 26 start to be joined from the central portion thereof, and then are joined in order toward the peripheral portion as shown in FIG. At the same time, air is pushed out from the central portion of the joining portion between the semiconductor chip 21 and the anisotropic conductive film (ACF) 26 toward the peripheral portion. As a result, it is possible to prevent the occurrence of entrapment voids between the semiconductor chip 21 and the package substrate 23, and to improve the moisture resistance reliability.

【0023】また、第2の実施の形態では、第1の実施
の形態のようにパッケージ基板23上に凸部を設ける必
要がないため、従来から使用していたパッケージ基板2
3をそのまま使用することができるので価格の増加を抑
えることができる。
In the second embodiment, there is no need to provide a projection on the package substrate 23 unlike the first embodiment.
3 can be used as it is, so that an increase in price can be suppressed.

【0024】図3は、本発明の第3の実施の形態を示し
ており、中央部分断面形状が凸状に形成された異方導電
性フィルム(ACF)の製造方法である。
FIG. 3 shows a third embodiment of the present invention, and is a method of manufacturing an anisotropic conductive film (ACF) having a central partial cross-sectional shape formed in a convex shape.

【0025】図3(a)において、35は、断面形状が
凹状になった凸状異方導電性フィルム形成部、36は中
央部断面形状が凸状に形成される前の異方導電性フィル
ムである。
In FIG. 3A, reference numeral 35 denotes a convex anisotropic conductive film forming section having a concave cross section, and 36 denotes an anisotropic conductive film before a central cross section is formed to be convex. It is.

【0026】まず、図3(b)に示すように、中央部断
面形状が凸状に形成される前の異方導電性フィルム(AC
F)36に、断面形状が凹状になった凸状異方導電性フ
ィルム形成部35を圧接して、異方導電性フィルムの中
央部断面形状を凸状に形成する。
First, as shown in FIG. 3 (b), the anisotropic conductive film (AC
F) The convex anisotropic conductive film forming portion 35 having a concave cross-sectional shape is pressed against 36 to form a convex central cross-sectional shape of the anisotropic conductive film.

【0027】次に、図3(c)に示すように、凸状異方
導電性フィルム形成部35を異方導電性フィルムから離
す。この時、凸状異方導電性フィルム形成部35の温度
は異方導電性フィルム(ACF)36が軟化する温度付近
に保持されており、かつ、凸状異方導電性フィルム形成
部35における異方導電性フィルム(ACF)36との接
触部分は異方導電性フィルム(ACF)36との離型性が
良くなるように、例えばテフロン加工されているか、あ
るいは異方導電性フィルム(ACF)36との離型性が良
好な素材でできているので、異方導電性フィルム(AC
F)36から凸状異方導電性フィルム形成部35を離し
ても、中央部分の断面形状が凸状に保持されたままの異
方導電性フィルム(ACF)37を形成することができ
る。
Next, as shown in FIG. 3C, the convex anisotropic conductive film forming portion 35 is separated from the anisotropic conductive film. At this time, the temperature of the convex anisotropic conductive film forming portion 35 is maintained near the temperature at which the anisotropic conductive film (ACF) 36 softens, and the temperature of the convex anisotropic conductive film forming portion 35 is maintained. The contact portion with the anisotropic conductive film (ACF) 36 is, for example, processed with Teflon or the anisotropic conductive film (ACF) 36 so that the releasability from the anisotropic conductive film (ACF) 36 is improved. Since it is made of a material with good mold release properties, anisotropic conductive film (AC
Even if the convex anisotropic conductive film forming portion 35 is separated from the F) 36, the anisotropic conductive film (ACF) 37 can be formed while the cross-sectional shape of the central portion is maintained in a convex shape.

【0028】最後に、図3(d)に示すように、パッケ
ージ基板上のボンディングエリアよりも大きい面積の形
状に切り離す。
Finally, as shown in FIG. 3D, the wafer is cut into a shape having an area larger than the bonding area on the package substrate.

【0029】ここでは、凸状異方導電性フィルム形成部
35は異方導電性フィルム(ACF)36を圧接すること
しかできないような形状になっているが、圧接と切り離
しが同時にできるように図3(e)のような形状にすれ
ば、製造工程の短縮が可能となる。
Here, the convex anisotropic conductive film forming portion 35 is shaped so that it can only press the anisotropic conductive film (ACF) 36, but it is necessary that the pressing and the separation can be performed simultaneously. If the shape is as shown in FIG. 3E, the manufacturing process can be shortened.

【0030】図4は、本発明の第4の実施の形態である
半導体装置の製造方法を示す。まず、図4(a)に示す
ように、パッケージ基板上のボンディングエリアよりも
大きい面積を有するサイズに加工した異方導電性フィル
ム(ACF)46をパッケージ基板43上に接合させる。
FIG. 4 shows a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. First, as shown in FIG. 4A, an anisotropic conductive film (ACF) 46 processed into a size having an area larger than the bonding area on the package substrate is bonded onto the package substrate 43.

【0031】次に、図4(b)に示すように、異方導電
性フィルム(ACF)46の軟化する温度付近に温度を保
持した凸状異方導電性フィルム(ACF)形成部45を異
方導電性フィルム(ACF)46に圧接して、異方導電性
フィルム(ACF)46の中央部分の断面形状が凸状にな
るようにする。
Next, as shown in FIG. 4 (b), the convex anisotropic conductive film (ACF) forming portion 45, which maintains the temperature near the softening temperature of the anisotropic conductive film (ACF) 46, is formed. It is pressed against the anisotropic conductive film (ACF) 46 so that the central portion of the anisotropic conductive film (ACF) 46 has a convex sectional shape.

【0032】最後に、図4(c)に示すように、半導体
チップ41とパッケージ基板43の接続温度に保った半
導体チップを保持する機器47を用いて、半導体チップ
41を上方から異方導電性フィルム(ACF)46に圧接
する。その結果、図4(d)に示すように、半導体装置
内における巻き込みボイドの発生を防止した半導体装置
を製造することができる。
Finally, as shown in FIG. 4 (c), the semiconductor chip 41 is held from above by an anisotropic conductive material using a device 47 which holds the semiconductor chip at the connection temperature between the semiconductor chip 41 and the package substrate 43. It is pressed against the film (ACF) 46. As a result, as shown in FIG. 4D, a semiconductor device in which entrapment voids are prevented from being generated in the semiconductor device can be manufactured.

【0033】以上のように、中央部分の断面形状が凸状
になった異方導電性フィルム(ACF)を形成する工程
と、それを挟んで半導体チップ41とパッケージ基板4
3とを電気的に接続する工程とを同一工程で実行できる
ようにしたので、各パッケージ毎に異方導電性フィルム
(ACF)の在庫を持つ必要がなくなる。その結果、部材
管理を軽減することができる。
As described above, the step of forming an anisotropic conductive film (ACF) having a convex cross section at the central portion, the semiconductor chip 41 and the package substrate 4 sandwiching the step.
3 can be performed in the same step, so that it is not necessary to stock an anisotropic conductive film (ACF) for each package. As a result, member management can be reduced.

【0034】また、パッケージ基板43の温度を、半導
体チップ41とパッケージ基板43が接続する時の温度
に加熱しておけば、半導体チップを保持する機器47の
温度を下げることができるので、半導体チップ41とパ
ッケージ基板43の接合後の熱収縮により生じる応力を
緩和することができる。その結果、半導体チップ41や
パッケージ基板43の損傷や接続不良を防止することが
できる。
If the temperature of the package substrate 43 is heated to the temperature at which the semiconductor chip 41 and the package substrate 43 are connected, the temperature of the device 47 holding the semiconductor chip can be reduced. The stress caused by the thermal shrinkage after the bonding of the package 41 and the package substrate 43 can be reduced. As a result, damage and poor connection of the semiconductor chip 41 and the package substrate 43 can be prevented.

【0035】また、図5及び図6に示すように、基板に
複数の半導体チップを搭載するMCM(Multi Chip Modul
e)構造を持つ半導体装置を製造する場合にも、上記の
第1から第4の実施の形態を実行することができる。
As shown in FIGS. 5 and 6, an MCM (Multi Chip Module) having a plurality of semiconductor chips mounted on a substrate is provided.
e) When manufacturing a semiconductor device having a structure, the above-described first to fourth embodiments can be executed.

【0036】[0036]

【発明の効果】本発明に係る半導体装置の製造方法で
は、パッケージ基板上に設けられた凸部により、その凸
部上に接合した柔軟性に富む導電性物質(実施の形態に
おける異方導電性フィルム(ACF))は、半導体チップ
とパッケージ基板の接合時には半導体チップの中央部分
から周縁部分に向かって順に接合していくような形状に
なるので、半導体装置の中央部分から周縁部分に向かっ
て空気が押し出される。従って、半導体装置内における
巻き込みボイドの発生を防止し、半導体装置の耐湿信頼
性を向上させることができる。
According to the method of manufacturing a semiconductor device of the present invention, a flexible conductive material (anisotropically conductive material according to the embodiment) bonded on a convex portion provided on a package substrate by the convex portion provided on the package substrate. When the semiconductor chip and the package substrate are joined, the film (ACF) has a shape such that the semiconductor chip is joined in order from the center to the periphery of the semiconductor chip, so that air flows from the center to the periphery of the semiconductor device. Is extruded. Therefore, it is possible to prevent the occurrence of entrapment voids in the semiconductor device and improve the humidity resistance of the semiconductor device.

【0037】また、本発明に係る半導体装置の製造方法
では、半導体チップとパッケージ基板とを電気的に接続
する際に用いる封止部材として、一方の面の中央部分の
断面形状が凸状になっている異方導電性フィルム(AC
F)を使用することにより、半導体チップとパッケージ
基板の接合時に半導体チップの中央部分から周縁部分に
向かって異方導電性フィルム(ACF)が順に接合してい
く。この時、半導体装置の中央部分から周縁部分に向か
って空気が押し出されるので、半導体装置内における巻
き込みボイドの発生を防止することができる。その結
果、半導体装置の耐湿信頼性を向上させることができ
る。
In the method of manufacturing a semiconductor device according to the present invention, as a sealing member used for electrically connecting a semiconductor chip and a package substrate, the central portion of one surface has a convex sectional shape. Anisotropic conductive film (AC
By using F), the anisotropic conductive film (ACF) is sequentially bonded from the central portion of the semiconductor chip to the peripheral portion when the semiconductor chip is bonded to the package substrate. At this time, since air is pushed out from the central portion of the semiconductor device toward the peripheral portion, it is possible to prevent entrapment voids in the semiconductor device. As a result, the moisture resistance reliability of the semiconductor device can be improved.

【0038】その上、パッケージ基板の中央部分に凸部
を設けずに、異方導電性フィルム(ACF)の中央部分の
断面形状を凸状にしているので、その異方導電性フィル
ム(ACF)を半導体チップとパッケージ基板の間に挟め
ば、電極を半導体チップの片方の全面に配置したエリア
バンプ型の半導体チップをその半導体チップに対応した
パッケージ基板に接合しても、半導体装置内における巻
き込みボイドの発生を防止し、半導体装置の耐湿信頼性
を向上させることができる。
In addition, since the central portion of the anisotropic conductive film (ACF) has a convex sectional shape without providing a convex portion at the central portion of the package substrate, the anisotropic conductive film (ACF) Is sandwiched between the semiconductor chip and the package substrate, even if the area bump type semiconductor chip in which the electrodes are arranged on one entire surface of the semiconductor chip is bonded to the package substrate corresponding to the semiconductor chip, the entrapment void in the semiconductor device can be obtained. Can be prevented, and the moisture resistance reliability of the semiconductor device can be improved.

【0039】さらに、中央部分の断面形状が凸状になっ
た異方導電性フィルム(ACF)を形成する工程と、その
異方導電性フィルム(ACF)を間に挟んで半導体チップ
とパッケージ基板とを電気的に接続する工程を同一装置
内に組み込むことにより、各パッケージ毎に異方導電性
フィルム(ACF)の在庫を持つ必要がなくなる。その結
果、部材管理を軽減することができる。
Further, a step of forming an anisotropic conductive film (ACF) having a convex cross section at the center portion, and a step of forming a semiconductor chip and a package substrate with the anisotropic conductive film (ACF) interposed therebetween. Integrating the process of electrically connecting the ACFs in the same device eliminates the need to stock an anisotropic conductive film (ACF) for each package. As a result, member management can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態におけるパッケージ
基板上に凸部を設けた半導体装置の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device having a convex portion provided on a package substrate according to a first embodiment of the present invention.

【図2】本発明の第2の実施の形態における中央部分の
断面形状が凸状になった異方導電性フィルム(ACF)を
用いて製造する半導体装置の断面図である。
FIG. 2 is a cross-sectional view of a semiconductor device manufactured using an anisotropic conductive film (ACF) in which a cross-sectional shape of a central portion is convex in a second embodiment of the present invention.

【図3】本発明の第3の実施の形態における中央部分の
断面形状が凸状になった異方導電性フィルム(ACF)の
製造方法である。
FIG. 3 shows a method for manufacturing an anisotropic conductive film (ACF) having a convex central section in a third embodiment of the present invention.

【図4】本発明の第4の実施の形態における中央部分の
断面形状が凸状になった異方導電性フィルム(ACF)を
用いた半導体装置の製造方法である。
FIG. 4 shows a method for manufacturing a semiconductor device using an anisotropic conductive film (ACF) having a convex central section in a fourth embodiment of the present invention.

【図5】半導体チップ搭載面の中央部に凸部を設けたパ
ッケージ基板に複数の半導体チップを搭載する半導体装
置の製造方法である。
FIG. 5 is a diagram illustrating a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are mounted on a package substrate having a convex portion provided at the center of a semiconductor chip mounting surface.

【図6】中央部分の断面形状が凸状になった異方導電性
フィルム(ACF)を用いることによって複数の半導体チ
ップを搭載する半導体装置の製造方法である。
FIG. 6 shows a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are mounted by using an anisotropic conductive film (ACF) having a convex central section.

【符号の説明】 11,21,41,51,61:半導体チップ 12,22,42,52,62:電極(半導体チップ
側) 13,23,43,53,63:パッケージ基板 14,24,44,54,64:電極(パッケージ基板
側) 15,55:凸部 16,26,36,46,56,66:異方導電性フィ
ルム(ACF) 35,45,65:凸状異方導電性フィルム(ACF)形
成部 37:凸状異方導電性フィルム(ACF) 38:圧接と切り離しが同時にできる凸状異方導電性フ
ィルム(ACF)形成部 47:半導体チップを保持する機器
[Description of References] 11, 21, 41, 51, 61: Semiconductor chip 12, 22, 42, 52, 62: Electrode (semiconductor chip side) 13, 23, 43, 53, 63: Package substrate 14, 24, 44 , 54, 64: Electrodes (package substrate side) 15, 55: Convex parts 16, 26, 36, 46, 56, 66: Anisotropic conductive film (ACF) 35, 45, 65: Convex anisotropic conductive film (ACF) forming part 37: convex anisotropic conductive film (ACF) 38: convex anisotropic conductive film (ACF) forming part 47 capable of simultaneously pressing and separating 47: equipment for holding a semiconductor chip

Claims (17)

【特許請求の範囲】[Claims] 【請求項1】 電極を有する半導体チップと、前記半導
体チップを搭載する面上に前記半導体チップの電極に対
向する位置に形成された電極を有する基板との間に、柔
軟性に富む導電性物質を挟むことによって前記半導体チ
ップと前記基板とを電気的に接続する半導体装置の製造
方法において、 前記導電性物質が実質的に前記半導体チップの中央部分
とから接合し始め、その後前記導電性物質が順に前記半
導体チップの周縁部分に向かって接合していく工程を含
むことを特徴とする半導体装置の製造方法。
An electrically conductive material having high flexibility between a semiconductor chip having electrodes and a substrate having electrodes formed on a surface on which the semiconductor chip is mounted and opposed to electrodes of the semiconductor chip. In a method of manufacturing a semiconductor device for electrically connecting the semiconductor chip and the substrate by sandwiching the conductive chip, the conductive material starts to join substantially from a central portion of the semiconductor chip, and then the conductive material A method of manufacturing a semiconductor device, comprising a step of sequentially joining the semiconductor chip toward a peripheral portion of the semiconductor chip.
【請求項2】 請求項1記載の半導体装置の製造方法に
おいて、 前記導電性物質は、前記基板の前記半導体チップを搭載
する面の法線方向である第1の方向に対してその実質的
な中央部分の高さが最も高く、かつ前記法線方向に垂直
な第2の方向に進むに従って前記第1の方向の前記導電
性物質の高さが順に低くなっていることを特徴とする半
導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is substantially in a first direction that is a normal direction of a surface of the substrate on which the semiconductor chip is mounted. A semiconductor device, wherein the height of the central portion is the highest, and the height of the conductive material in the first direction decreases in order in the second direction perpendicular to the normal direction. Manufacturing method.
【請求項3】 請求項1記載の半導体装置の製造方法に
おいて、 前記基板は、前記半導体チップを搭載する面上の電極に
よって囲まれた部分の実質的に中央部分に、その最上部
と前記半導体チップとの間隔が、前記半導体チップの電
極と前記基板の電極との間隔よりも大きくなるように設
けられた凸部を有することを特徴とする半導体装置の製
造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate has a substantially central portion of a portion surrounded by an electrode on a surface on which the semiconductor chip is mounted, an uppermost portion thereof, and the semiconductor. A method of manufacturing a semiconductor device, comprising: a projection provided so that an interval between the chip and an electrode of the semiconductor chip is larger than an interval between an electrode of the substrate and the chip.
【請求項4】 請求項3記載の半導体装置の製造方法に
おいて、 前記凸部は、前記半導体チップを搭載する面からの高さ
が、実質的に中央部分が最も高く、前記半導体チップを
搭載する面の周縁部分に向かって順に低くなっているこ
とを特徴とする半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the height of the projection from a surface on which the semiconductor chip is mounted is substantially highest at a central portion, and the semiconductor chip is mounted. A method for manufacturing a semiconductor device, wherein the height of the semiconductor device is gradually reduced toward a peripheral portion of the surface.
【請求項5】 請求項3記載の半導体装置の製造方法に
おいて、 前記凸部は、前記半導体チップを搭載する面からの高さ
が、実質的に中央部分が最も高く、前記半導体チップを
搭載する面の周縁部分に向かって順に曲面あるいは平面
を形成しながら低くなっていることを特徴とする半導体
装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 3, wherein the height of the projection from a surface on which the semiconductor chip is mounted is substantially highest at a central portion, and the semiconductor chip is mounted. A method for manufacturing a semiconductor device, characterized in that the surface is lowered while forming a curved surface or a plane in order toward a peripheral portion of the surface.
【請求項6】 請求項3記載の半導体装置の製造方法に
おいて、 前記凸部は、ドーム状、蒲鉾状、円錐状、ピラミッド状
になっていることを特徴とする半導体装置の製造方法。
6. The method of manufacturing a semiconductor device according to claim 3, wherein the convex portion has a dome shape, a squab shape, a conical shape, or a pyramid shape.
【請求項7】 請求項1記載の半導体装置の製造方法に
おいて、 前記封止部材は、少なくとも一方の面の実質的に中央部
分の断面形状が凸状になっていることを特徴とする半導
体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 1, wherein the sealing member has a convex cross-sectional shape substantially at a central portion of at least one surface. Manufacturing method.
【請求項8】 請求項7記載の半導体装置の製造方法に
おいて、 前記封止部材は、その中央部分の厚さが最も厚く、周縁
部分に向かって厚さが順に薄くなっていることを特徴と
する半導体装置の製造方法。
8. The method of manufacturing a semiconductor device according to claim 7, wherein the thickness of the sealing member is the largest at a central portion, and is gradually reduced toward a peripheral portion. Semiconductor device manufacturing method.
【請求項9】 請求項7記載の半導体装置の製造方法に
おいて、 前記封止部材は、その中央部分の厚さが最も厚く、前記
封止部材の周縁部分に向かって曲面あるいは平面を形成
しながら厚さが順に薄くなっていることを特徴とする半
導体装置の製造方法。
9. The method for manufacturing a semiconductor device according to claim 7, wherein the sealing member has the largest thickness at a central portion thereof and forms a curved surface or a flat surface toward a peripheral portion of the sealing member. A method for manufacturing a semiconductor device, characterized in that the thickness is sequentially reduced.
【請求項10】 請求項7記載の半導体装置の製造方法
において、 前記封止部材は、少なくともその一方の表面がドーム
状、蒲鉾状、円錐状、ピラミッド状になっていることを
特徴とする半導体装置の製造方法。
10. The method of manufacturing a semiconductor device according to claim 7, wherein at least one surface of the sealing member has a dome shape, a semi-cylindrical shape, a conical shape, or a pyramid shape. Device manufacturing method.
【請求項11】 少なくとも一方の面の中央部断面形状
が凸状になっている封止部材の製造方法において、 前記封止部材を象る部分の形状が凹状になっている封止
部材製造装置を用いることを特徴とする封止部材の製造
方法。
11. A method for manufacturing a sealing member in which at least one surface has a convex central cross-sectional shape, wherein a sealing member manufacturing apparatus in which a shape of a portion of the sealing member is concave. A method for manufacturing a sealing member, characterized by using:
【請求項12】 請求項11記載の封止部材の製造方法
において、 前記封止部材製造装置を、前記封止部材がその軟化点温
度に保持されたまま前記封止部材に圧接することを特徴
とする封止部材の製造方法。
12. The method for manufacturing a sealing member according to claim 11, wherein the sealing member manufacturing apparatus is pressed against the sealing member while the sealing member is kept at its softening point temperature. Manufacturing method of a sealing member.
【請求項13】 請求項11記載の封止部材の製造方法
において、 前記封止部材製造装置は、前記封止部材を象る部分の形
状が、その周縁部分から中央部分に向かって窪んだ形状
になっていることを特徴とする封止部材の製造方法。
13. The sealing member manufacturing method according to claim 11, wherein in the sealing member manufacturing apparatus, a shape of a portion of the sealing member is depressed from a peripheral portion toward a central portion. A method for producing a sealing member, characterized in that:
【請求項14】 請求項11記載の封止部材の製造方法
において、 前記封止部材製造装置は、前記封止部材への接触部分
が、前記封止部材の凸部の表面が滑らかな形状に製造す
ることができるように加工されているか、あるいは前記
封止部材の凸部の表面が滑らかな形状に製造することが
できるような素材でできていることを特徴とする封止部
材の製造方法。
14. The method for manufacturing a sealing member according to claim 11, wherein in the sealing member manufacturing apparatus, a contact portion with the sealing member has a smooth surface with a convex portion of the sealing member. A method for manufacturing a sealing member, characterized in that the sealing member is processed so that it can be manufactured, or is made of a material capable of manufacturing a surface of a convex portion of the sealing member into a smooth shape. .
【請求項15】 請求項11記載の封止部材の製造方法
において、 少なくとも一方の面の中央部断面形状が凸状になってい
る封止部材を形成するための圧接をする工程と、切り離
す工程とを同時に行うことを特徴とする封止部材の製造
方法。
15. The method for manufacturing a sealing member according to claim 11, wherein a pressing step for forming a sealing member having a convex cross-sectional central portion of at least one surface is performed, and a separating step. And a method for manufacturing a sealing member.
【請求項16】 請求項1記載の半導体装置の製造方法
において、 前記半導体チップと前記基板との間に挟むために必要な
大きさの前記封止部材を形成する工程と、前記基板上に
前記封止部材を接合させる工程と、前記封止部材の前記
半導体チップと接合する方の面における中央部断面形状
を凸状に形成する工程と、前記半導体チップと前記基板
とを電気的に接続する工程を同一工程で行うことを特徴
とする半導体装置の製造方法。
16. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming the sealing member having a size necessary to sandwich the semiconductor chip between the semiconductor chip and the substrate; A step of joining a sealing member, a step of forming a central section cross-sectional shape of a surface of the sealing member to be joined to the semiconductor chip to be convex, and electrically connecting the semiconductor chip and the substrate. A method for manufacturing a semiconductor device, wherein the steps are performed in the same step.
【請求項17】 請求項1記載の半導体装置の製造方法
において、 前記封止部材を前記基板上に接合させる工程以降、前記
基板を、前記半導体チップと前記基板とが電気的に接続
できるように接合する時の前記基板の温度付近まで加熱
しておくことを特徴とする半導体装置の製造方法。
17. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of bonding the sealing member on the substrate, the substrate is electrically connected to the semiconductor chip and the substrate. A method for manufacturing a semiconductor device, comprising heating the substrate to a temperature close to the temperature of the substrate at the time of bonding.
JP19584797A 1997-07-22 1997-07-22 Method for manufacturing semiconductor device Expired - Fee Related JP3558498B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP19584797A JP3558498B2 (en) 1997-07-22 1997-07-22 Method for manufacturing semiconductor device

Related Child Applications (1)

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JPH1140607A true JPH1140607A (en) 1999-02-12
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091545A (en) * 2006-09-29 2008-04-17 Shinko Electric Ind Co Ltd Semiconductor device
KR101631293B1 (en) * 2015-11-27 2016-06-16 정종구 Method for substrate bonding of IC chip
CN107000422A (en) * 2015-09-30 2017-08-01 华为技术有限公司 Conducting film and conducting film cutter head

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091545A (en) * 2006-09-29 2008-04-17 Shinko Electric Ind Co Ltd Semiconductor device
CN107000422A (en) * 2015-09-30 2017-08-01 华为技术有限公司 Conducting film and conducting film cutter head
KR101631293B1 (en) * 2015-11-27 2016-06-16 정종구 Method for substrate bonding of IC chip

Also Published As

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