JP2001077295A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JP2001077295A JP2001077295A JP24947299A JP24947299A JP2001077295A JP 2001077295 A JP2001077295 A JP 2001077295A JP 24947299 A JP24947299 A JP 24947299A JP 24947299 A JP24947299 A JP 24947299A JP 2001077295 A JP2001077295 A JP 2001077295A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- bump
- semiconductor element
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/29082—Two-layer arrangements
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、２つの半導体素子
を互いに対向させてバンプ接合してなる半導体装置の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which two semiconductor elements are bump-bonded so as to face each other.
【０００２】[0002]
【従来の技術】一般に、多くの半導体装置では、１つの
パッケージ内に１つの半導体素子を組み込むようにして
いるが、最近では、半導体素子単体での高機能化、高集
積化の限界から、１つのパッケージ内に２つまたはそれ
以上の半導体素子を組み込むことで、実質的な多機能化
を実現したものが知られている。2. Description of the Related Art In general, in many semiconductor devices, one semiconductor element is incorporated in one package. However, recently, due to the limit of high functionality and high integration of a single semiconductor element, one semiconductor element has been developed. It is known that two or more semiconductor elements are incorporated in one package to realize substantial multifunction.
【０００３】この種の半導体装置としては、例えば２つ
の半導体素子を平面的に並べて共通のパッケージ基板に
実装し、該基板上の配線で２つの半導体素子を電気的に
接続したものがある。ところが、２つの半導体素子を平
面的に並べると、パッケージ全体が大型化するため、高
密度実装が出来なくなるという欠点がある。As this type of semiconductor device, for example, there is a semiconductor device in which two semiconductor elements are arranged in a plane and mounted on a common package substrate, and the two semiconductor elements are electrically connected by wiring on the substrate. However, when the two semiconductor elements are arranged in a plane, the entire package becomes large, so that high-density mounting cannot be performed.
【０００４】そこで近年においては、例えば特開平０１
−２９５４５４号公報に記載されているように、２つの
半導体素子を互いに対向させてバンプ接合することによ
り、パッケージサイズを拡大することなく、多機能化を
実現したものが提案されている。この公報に記載の技術
では、実際に半導体装置を製造するにあたって、２つの
半導体素子をバンプを介して接続した後、素子間の間隙
を液状封止樹脂で満たし、その後、封止樹脂を硬化させ
るようにしている。Therefore, in recent years, for example,
As described in Japanese Patent Application Laid-Open No. 295454/1990, there has been proposed a device which realizes multifunctionality without increasing the package size by bonding two semiconductor elements to each other and bump-bonding them. According to the technique described in this publication, in actually manufacturing a semiconductor device, after connecting two semiconductor elements via bumps, a gap between the elements is filled with a liquid sealing resin, and then the sealing resin is cured. Like that.
【０００５】[0005]
【発明が解決しようとする課題】ところで、２つの半導
体素子をバンプ接合する場合は、一方の半導体素子の電
極上にバンプを形成し、このバンプを、他方の半導体素
子の電極に接合（熱圧着）することになる。その際、２
つの半導体素子には発熱装置による加熱作用とボンディ
ングツールによる加圧作用が加えられ、これによって２
つの半導体素子の電極同士がバンプを介して電気的かつ
機械的に接続される。When two semiconductor elements are bump-bonded, a bump is formed on the electrode of one semiconductor element and this bump is bonded to the electrode of the other semiconductor element (thermocompression bonding). ). At that time, 2
One semiconductor element is subjected to a heating action by a heating device and a pressurizing action by a bonding tool.
The electrodes of the two semiconductor elements are electrically and mechanically connected via the bumps.
【０００６】しかしながら、２つの半導体素子を加熱加
圧するにあたっては、ボンディングツールの機械的なガ
タ等により、２つの半導体素子の間に若干の傾きが生じ
る場合がある。そうした場合、一方の半導体素子に形成
された各々のバンプに対して均一に荷重が加わらなくな
る。その結果、荷重の大きいところではバンプが潰れ過
ぎたり、荷重の小さいところでは接合状態が不十分にな
るなどの不具合が生じる。However, when the two semiconductor elements are heated and pressed, a slight inclination may occur between the two semiconductor elements due to mechanical play of a bonding tool or the like. In such a case, a load is not uniformly applied to each bump formed on one semiconductor element. As a result, there are problems such as the bumps being crushed excessively where the load is large, and the insufficient bonding state where the load is small.
【０００７】本発明は、上記課題を解決するためになさ
れたもので、その目的とするところは、２つの半導体素
子の間に多少の傾きが生じていても、各々のバンプに均
一に荷重を加えることができる半導体装置の製造方法を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to uniformly apply a load to each bump even if a slight inclination occurs between two semiconductor elements. It is another object of the present invention to provide a method for manufacturing a semiconductor device to which the present invention can be applied.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、２つの半導体素子を互い
に対向させてバンプ接合してなる半導体装置の製造方法
において、２つの半導体素子が相対向する面上に素子間
の傾きを補正するための傾き補正層を形成し、その後、
２つの半導体素子を互いに対向させて加熱加圧すること
によりバンプ接合するようにしたものである。SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object, and a method of manufacturing a semiconductor device in which two semiconductor elements are bump-bonded to each other so as to face each other. Form an inclination correction layer for correcting the inclination between the elements on the surfaces facing each other, and thereafter,
The bump bonding is performed by heating and pressing two semiconductor elements so as to face each other.
【０００９】この半導体装置の製造方法によれば、２つ
の半導体素子が相対向する面上に傾き補正層を形成して
おくことで、２つの半導体素子を加熱加圧したときに、
素子間の傾きが補正されるようになる。これにより、２
つの半導体素子の間に若干の傾きが生じていても、各々
のバンプに均一に荷重を加えることが可能となる。According to this method of manufacturing a semiconductor device, the tilt correction layer is formed on the surface where the two semiconductor elements face each other, so that when the two semiconductor elements are heated and pressed,
The inclination between the elements is corrected. This gives 2
Even if a slight inclination occurs between the two semiconductor elements, it is possible to apply a load uniformly to each bump.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しつつ詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１１】図１は本発明の実施形態で製造対象とした
半導体装置の構成を示す側断面図である。図示した半導
体装置１においては、リードフレームのダイパッド２上
に、外形寸法の異なる大小２つの半導体素子３，４が搭
載されている。これら２つの半導体素子３，４は、互い
の素子形成面を対向させた状態で上下に重ね合わされて
いる。FIG. 1 is a side sectional view showing a configuration of a semiconductor device to be manufactured in an embodiment of the present invention. In the illustrated semiconductor device 1, two large and small semiconductor elements 3 and 4 having different external dimensions are mounted on a die pad 2 of a lead frame. These two semiconductor elements 3 and 4 are vertically stacked with their element formation surfaces facing each other.
【００１２】このうち、外形寸法が大きい方の半導体素
子（以下、第１の半導体素子という）３は、図示せぬ導
電性ペースト（銀ペースト等）を用いてダイパッド２に
固着されている。これに対して、外形寸法が小さい方の
半導体素子（以下、第２の半導体素子という）には、そ
の素子形成面上に位置して樹脂層５が形成されている。
また、第１，第２の半導体素子３，４は、バンプ６を介
して接合され、かつそれらの素子間（間隙）に接着層７
が充填されている。The semiconductor element 3 having a larger outer dimension (hereinafter, referred to as a first semiconductor element) is fixed to the die pad 2 using a conductive paste (silver paste or the like) not shown. On the other hand, a resin layer 5 is formed on a semiconductor element having a smaller outer dimension (hereinafter, referred to as a second semiconductor element) on the element formation surface.
The first and second semiconductor elements 3 and 4 are joined via bumps 6 and an adhesive layer 7 is provided between the elements (gap).
Is filled.
【００１３】一方、第１の半導体素子３の周縁部には、
上記バンプ６に対応する電極よりも外側に位置して外部
接続用電極が形成されている。これに対して、第１の半
導体素子３の周辺部には複数のリード８が配置され、こ
れらのリード８と第１の半導体素子３の外部接続用電極
とが金線等のボンディングワイヤ９にて結線されてい
る。さらに、バンプ接合された第１，第２の半導体素子
３，４は、リードフレームのダイパッド２やボンディン
グワイヤ９とともにモールド樹脂１０にて一体に樹脂封
止されている。On the other hand, on the periphery of the first semiconductor element 3,
External connection electrodes are formed outside the electrodes corresponding to the bumps 6. On the other hand, a plurality of leads 8 are arranged around the first semiconductor element 3, and these leads 8 and the external connection electrodes of the first semiconductor element 3 are connected to bonding wires 9 such as gold wires. Connected. Further, the first and second semiconductor elements 3 and 4 which have been bump-bonded are integrally resin-sealed with the mold resin 10 together with the die pad 2 and the bonding wires 9 of the lead frame.
【００１４】続いて、上記構成からなる半導体装置１の
製造方法として、特に、第１，第２の半導体素子３，４
をバンプ接合する際の方法につき、図２及び図３を用い
て説明する。Subsequently, as a method of manufacturing the semiconductor device 1 having the above configuration, in particular, the first and second semiconductor elements 3 and 4
A method for bump bonding will be described with reference to FIGS.
【００１５】先ず、ウエハ上に区画形成された複数の第
２の半導体素子４に対して、図２（ａ）に示すように、
第２の半導体素子４の素子形成面上に傾き補正層１２を
形成する。傾き補正層１２は、後述するように第１，第
２の半導体素子３，４を加熱加圧するにあたって、素子
間の傾きを補正するためのものである。この傾き補正層
１２は、第２の半導体素子４の素子形成面に樹脂層５を
積層し、さらにその上に接着層７を積層することにより
得られる。First, as shown in FIG. 2A, a plurality of second semiconductor elements 4 partitioned on a wafer are formed as follows.
The tilt correction layer 12 is formed on the element formation surface of the second semiconductor element 4. The tilt correction layer 12 corrects the tilt between the first and second semiconductor elements 3 and 4 when heating and pressing the elements, as described later. The inclination correction layer 12 is obtained by laminating the resin layer 5 on the element formation surface of the second semiconductor element 4 and further laminating the adhesive layer 7 thereon.
【００１６】樹脂層５の具体的な形成方法としては、例
えば上述の如く複数の第２の半導体素子４が区画形成さ
れたウエハ上にスピンコート方式にて感光性ポリイミド
前駆体を塗布した後、その塗布膜の必要な部分（第２の
半導体素子４の素子形成面に対応する部分）を露光して
他の不要部を現像により除去し、最後に熱処理によるイ
ミド化を行うことで形成することができる。また、接着
層７については、第２の半導体素子４上に樹脂層５を形
成した後、その樹脂層５の表面に、熱硬化性又は熱可塑
性の接着樹脂（ペースト）を印刷方式等により塗布する
ことで形成することができる。As a specific method of forming the resin layer 5, for example, a photosensitive polyimide precursor is applied by spin coating on a wafer on which a plurality of second semiconductor elements 4 are formed as described above, A necessary portion of the coating film (a portion corresponding to the element forming surface of the second semiconductor element 4) is exposed to light to remove other unnecessary portions by development, and finally, is formed by imidization by heat treatment. Can be. As for the adhesive layer 7, after forming the resin layer 5 on the second semiconductor element 4, a thermosetting or thermoplastic adhesive resin (paste) is applied to the surface of the resin layer 5 by a printing method or the like. Can be formed.
【００１７】次に、図２（ｂ）に示すように、各々の第
２の半導体素子４に形成された電極（アルミパッド）１
１上に、例えば無電界めっき法等を用いてＮｉコアＡ
ｕ、またはＡｕのみからなるバンプ６を形成する。この
バンプ６は、ワイヤボンディングツール（キャピラリ）
を用いたスタッドバンプ法により得られるボールバンプ
でもよいし、ソルダリング法による得られるはんだバン
プ（ソルダバンプ）でもよい。また、転写バンプ法等に
よってバンプ６を形成してもよい。Next, as shown in FIG. 2B, an electrode (aluminum pad) 1 formed on each second semiconductor element 4 is formed.
1 on a Ni core A using, for example, an electroless plating method.
A bump 6 made of only u or Au is formed. The bump 6 is provided by a wire bonding tool (capillary)
Ball bumps obtained by a stud bump method using a solder bump or solder bumps (solder bumps) obtained by a soldering method. Further, the bump 6 may be formed by a transfer bump method or the like.
【００１８】こうして樹脂層５及び接着層７からなる傾
き補正層１２を形成し、かつバンプ６を形成したら、こ
の段階で第２の半導体素子４をウエハからチップ状に切
り出す。なお、傾き補正層１２とバンプ６の形成につい
ては、第２の半導体素子４をウエハから切り出した後
（チップ状態）で行うことも可能である。After forming the tilt correction layer 12 composed of the resin layer 5 and the adhesive layer 7 and forming the bumps 6, the second semiconductor element 4 is cut out from the wafer into chips at this stage. The formation of the tilt correction layer 12 and the bumps 6 can be performed after the second semiconductor element 4 is cut out from the wafer (in a chip state).
【００１９】続いて、ウエハ上に区画形成された複数の
第１の半導体素子３を、ウエハ状態のままで、予め加熱
された平らなステージの上にセットした後、光学カメラ
等を用いて第１の半導体素子３の位置出しを行う。次い
で、図３（ａ）に示すように、第２の半導体素子４をバ
ンプ６が下向きになるように（フェースダウン状態で）
ボンディングツール１３により保持するとともに、先ほ
ど位置出しした第１の半導体素子３の真上に第２の半導
体素子４を対向状態に配置する。因みに、図３（ａ）に
おいては、ボンディングツール１３の機械的なガタ等に
より、第１の半導体素子３と平行な仮想平面に対して第
２の半導体素子４が角度θだけ傾いた状態を示してい
る。Subsequently, after setting the plurality of first semiconductor elements 3 formed on the wafer in a wafer state on a flat stage which has been heated in advance, the first semiconductor elements 3 are formed using an optical camera or the like. Positioning of one semiconductor element 3 is performed. Next, as shown in FIG. 3A, the second semiconductor element 4 is placed so that the bumps 6 face down (in a face-down state).
While being held by the bonding tool 13, the second semiconductor element 4 is arranged directly above the first semiconductor element 3 located just before in a facing state. Incidentally, FIG. 3A shows a state in which the second semiconductor element 4 is inclined by an angle θ with respect to a virtual plane parallel to the first semiconductor element 3 due to mechanical play of the bonding tool 13 or the like. ing.
【００２０】次に、ボンディングツール１３を介して第
２の半導体素子４を加熱しつつ、ボンディングツール１
３を垂直に下降させる。そうすると、先ずは、図３
（ｂ）に示すように、第２の半導体素子４の素子形成面
上に形成された傾き補正層１２（接着層７）が、第１の
半導体素子３の素子形成面に接触し、さらにその状態か
らボンディングツール１３により加圧すると、図３
（ｃ）に示すように、加熱による接着層７の軟化ととも
に、一部（図では左側）のバンプ６が第１の半導体素子
３の電極１４に押し付けられて若干潰れる。Next, while heating the second semiconductor element 4 through the bonding tool 13, the bonding tool 1
Lower 3 vertically. Then, first, Figure 3
As shown in (b), the tilt correction layer 12 (adhesive layer 7) formed on the element formation surface of the second semiconductor element 4 contacts the element formation surface of the first semiconductor element 3, and furthermore, When pressurized by the bonding tool 13 from the state, FIG.
As shown in (c), as the adhesive layer 7 is softened by heating, a part (left side in the figure) of the bump 6 is pressed against the electrode 14 of the first semiconductor element 3 and slightly collapsed.
【００２１】このとき、ボンディングツール１３による
加圧力が上記一部のバンプ６だけでなく、素子間の樹脂
層５と接着層７でも受圧されるため、上記一部のバンプ
６が潰れすぎることはない。また、ボンディングツール
１３による加圧力を素子間の樹脂層５と接着層７で受圧
することにより、第２の半導体素子４上に形成された樹
脂層５が接着層７の軟化により第１の半導体素子３面に
馴染むかたちで、第２の半導体素子４の傾きが補正され
る。At this time, the pressing force of the bonding tool 13 is received not only by the above-mentioned part of the bumps 6 but also by the resin layer 5 and the adhesive layer 7 between the elements. Absent. Further, the resin layer 5 formed on the second semiconductor element 4 is softened by the first semiconductor by the pressure applied by the bonding tool 13 between the resin layer 5 and the adhesive layer 7 between the elements. The inclination of the second semiconductor element 4 is corrected in such a manner as to conform to the surface of the element 3.
【００２２】これにより、図３（ｄ）に示すように、ボ
ンディングツール１３の加圧力Ｐが各々のバンプ６に均
一な荷重ｐとなって加えられることから、上記一部のバ
ンプ６以外のバンプ６も、第１の半導体素子４３の電極
１４に押し付けられて若干潰れた状態となる。また、先
述の如く軟化した接着層７がボンディングツール１３に
よる加圧力によって次第に外側に広がる。As a result, as shown in FIG. 3D, the pressing force P of the bonding tool 13 is applied to each of the bumps 6 as a uniform load p. 6 is pressed slightly against the electrode 14 of the first semiconductor element 43 and slightly collapsed. Further, the adhesive layer 7 softened as described above gradually spreads outward by the pressing force of the bonding tool 13.
【００２３】さらに、図３（ｄ）の状態からボンディン
グツール１３の加圧力Ｐを規定圧まで高めることによ
り、図３（ｅ）に示すように、全て（四方）のバンプ６
が適度に潰されたかたちで第１の半導体素子４の電極１
４に圧着される。また、第１，第２の半導体素子３，４
の間には樹脂層５が介装され、かつ先述の如く軟化しか
つ外側に広がった接着層７が充填された状態となる。Further, by increasing the pressure P of the bonding tool 13 from the state shown in FIG. 3D to a specified pressure, as shown in FIG. 3E, all (square) bumps 6 are formed.
The electrode 1 of the first semiconductor element 4 is appropriately crushed.
4 is crimped. Further, the first and second semiconductor elements 3, 4
A resin layer 5 is interposed therebetween, and the state is filled with the adhesive layer 7 that has been softened and spread outward as described above.
【００２４】こうして第１，第２の半導体素子３，４を
バンプ６を介して接合したら、その後は、ウエハ上に設
定されている区画ラインに沿ってカッティングを行うこ
とにより、ウエハから第１の半導体素子３をチップ状に
切り出す。これにより、第１，第２の半導体素子３，４
を互いに対向させてバンプ接合してなる、一組のチップ
対が得られる。なお、ウエハからの第１の半導体素子３
の切り出し（カッティング）は、バンプ接合前に行って
もよい。After joining the first and second semiconductor elements 3 and 4 via the bumps 6 in this manner, thereafter, the first and second semiconductor elements 3 and 4 are cut along the dividing lines set on the wafer, so that the first and second semiconductor elements 3 and 4 are separated from the wafer. The semiconductor element 3 is cut into chips. Thereby, the first and second semiconductor elements 3, 4
Are opposed to each other and bump-bonded, thereby obtaining a pair of chip pairs. The first semiconductor element 3 from the wafer
May be performed before bump bonding.
【００２５】以降は、第１，第２の半導体素子３，４か
らなるチップ対のダイボンィング工程、ワイヤボンディ
ング工程、樹脂封止のためのモールド成形工程、リード
成形工程等の各工程を経ることにより、図１に示す半導
体装置１が得られる。The subsequent steps include a die bonding step for a chip pair composed of the first and second semiconductor elements 3 and 4, a wire bonding step, a molding step for resin sealing, a lead forming step, and the like. Thereby, the semiconductor device 1 shown in FIG. 1 is obtained.
【００２６】このように第１，第２の半導体素子３，４
をバンプ接合するにあたって、第２の半導体素子４の素
子形成面上に傾き補正層１２（樹脂層５，接着層７）を
形成し、この状態で第１，第２の半導体素子３，４を加
熱加圧することにより、それらの素子間に生じた傾きを
補正することができる。これにより、第２の半導体素子
４に形成された各々のバンプ６に対して、ボンディング
ツール１３による荷重を均一に加えることができるた
め、部分的なバンプ６の潰れすぎや荷重不足による接合
不良を防止することが可能となる。As described above, the first and second semiconductor elements 3 and 4
When bump bonding is performed, an inclination correction layer 12 (resin layer 5 and adhesive layer 7) is formed on the element formation surface of the second semiconductor element 4, and in this state, the first and second semiconductor elements 3 and 4 are formed. By applying heat and pressure, the inclination generated between these elements can be corrected. Thereby, the load by the bonding tool 13 can be uniformly applied to each of the bumps 6 formed on the second semiconductor element 4, thereby preventing the bonding failure due to partial crushing of the bump 6 or insufficient load. It is possible to do.
【００２７】なお、上記実施形態においては、第２の半
導体素子４の電極１１上にバンプ６を形成するようにし
たが、実際のバンプ接合では、第１，第２の半導体素子
３，４のどちら側にバンプ６を形成してあっても、両方
の半導体素子３，４にバンプを形成してあってもよい。
また、傾き補正層１２の形成状態としても、第１，第２
の半導体素子３，４のどちら側に形成してあっても、両
方に形成してあってもよく、種々の変形が可能である。In the above embodiment, the bump 6 is formed on the electrode 11 of the second semiconductor element 4. However, in the actual bump bonding, the bump 6 is formed on the first and second semiconductor elements 3 and 4. The bump 6 may be formed on either side, or the bumps may be formed on both the semiconductor elements 3 and 4.
In addition, the formation state of the inclination correction layer 12 is the first and second.
The semiconductor elements 3 and 4 may be formed on either side or both sides, and various modifications are possible.
【００２８】具体的には、例えば、図４（ａ）に示すよ
うに、第２の半導体素子４の素子形成面上に樹脂層５を
形成するとともに、第１の半導体素子３の素子形成面上
にディスペンサ等を用いて接着層７を形成し、これらの
樹脂層５と接着層７により傾き補正層１２を構成するも
のであってもよい。Specifically, for example, as shown in FIG. 4A, a resin layer 5 is formed on the element formation surface of the second semiconductor element 4 and the element formation surface of the first semiconductor element 3 is formed. The adhesive layer 7 may be formed thereon using a dispenser or the like, and the resin layer 5 and the adhesive layer 7 may constitute the tilt correction layer 12.
【００２９】また、図４（ｂ）に示すように、第１の半
導体素子３の素子形成面上に樹脂層５と接着層７からな
る傾き補正層１２を形成するものであってもよい。この
傾き補正層１２を採用した場合のバンプ接合後の状態を
図５（ａ）に示す。Further, as shown in FIG. 4B, an inclination correction layer 12 composed of a resin layer 5 and an adhesive layer 7 may be formed on the element forming surface of the first semiconductor element 3. FIG. 5A shows a state after bump bonding when the tilt correction layer 12 is employed.
【００３０】さらに、図４（ｃ）に示すように、第１の
半導体素子３の素子形成面上に第１の樹脂層５Ａを形成
するとともに、第２の半導体素子４の素子形成面上に第
２の樹脂層５Ｂ及び接着層７を形成し、これら第１，第
２の樹脂層５Ａ，５Ｂ及び接着層７により傾き補正層１
２を構成するものであってもよい。この傾き補正層１２
を採用した場合のバンプ接合後の状態を図５（ｂ）に示
す。なお、接着層７については、第１の半導体素子３側
に形成されていても、また第１，第２の半導体素子３，
４の両方に形成されていてもよい。Further, as shown in FIG. 4C, a first resin layer 5A is formed on the element formation surface of the first semiconductor element 3, and a first resin layer 5A is formed on the element formation surface of the second semiconductor element 4. A second resin layer 5B and an adhesive layer 7 are formed, and the tilt correction layer 1 is formed by the first and second resin layers 5A and 5B and the adhesive layer 7.
2 may be included. This tilt correction layer 12
FIG. 5 (b) shows a state after bump bonding in the case of employing. The adhesive layer 7 may be formed on the first semiconductor element 3 side, or may be formed on the first and second semiconductor elements 3 and 3.
4 may be formed.
【００３１】加えて、図４（ｄ）に示すように、第２の
半導体素子４の素子形成面上に、第１の接着層７Ａ、樹
脂層５及び第２の接着層７Ｂからなる傾き補正層１２を
形成するものであってもよい。この傾き補正層１２を採
用した場合のバンプ接合後の状態を図５（ｃ）に示す。
なお、第１の接着層７Ａ、樹脂層５及び第２の接着層７
Ｂからなる傾き補正層１２については、第１の半導体素
子４の素子形成面上に形成してもよい。In addition, as shown in FIG. 4D, on the element forming surface of the second semiconductor element 4, a tilt correction made up of the first adhesive layer 7A, the resin layer 5, and the second adhesive layer 7B is performed. The layer 12 may be formed. FIG. 5C shows a state after bump bonding when the inclination correction layer 12 is adopted.
The first adhesive layer 7A, the resin layer 5, and the second adhesive layer 7
The tilt correction layer 12 made of B may be formed on the element formation surface of the first semiconductor element 4.
【００３２】[0032]
【発明の効果】以上説明したように本発明によれば、２
つの半導体素子をバンプ接合するにあたって、素子間に
若干の傾きが生じていても、その傾きを補正して各々の
バンプに均一に荷重を加えることができるため、バンプ
の潰れ過ぎや荷重不足による接合不良の発生を防止する
ことが可能となる。As described above, according to the present invention, 2
When bump bonding two semiconductor elements, even if there is a slight inclination between the elements, the inclination can be corrected and a load can be uniformly applied to each bump, so that the bonding due to excessive crushing of the bump or insufficient load It is possible to prevent the occurrence of defects.
【図１】本発明の実施形態で製造対象とした半導体装置
の構成を示す側断面図である。FIG. 1 is a side sectional view showing a configuration of a semiconductor device to be manufactured in an embodiment of the present invention.
【図２】本発明の実施形態に係る半導体装置の製造方法
を説明するための図（その１）である。FIG. 2 is a view (No. 1) for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施形態に係る半導体装置の製造方法
を説明するための図（その２）である。FIG. 3 is a view (No. 2) for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention.
【図４】本発明の変形例を説明する図（その１）であ
る。FIG. 4 is a diagram (part 1) for explaining a modified example of the present invention.
【図５】本発明の変形例を説明する図（その２）であ
る。FIG. 5 is a diagram (part 2) for explaining a modified example of the present invention.
１…半導体装置、３，４…半導体素子、５…樹脂層、６
…バンプ、７…接着層、１１，１４…電極、１２…傾き
補正層、１３…ボンディングツールDESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 3, 4 ... Semiconductor element, 5 ... Resin layer, 6
... Bump, 7 ... Adhesive layer, 11, 14 ... Electrode, 12 ... Tilt correction layer, 13 ... Bonding tool
Claims (1)
ンプ接合してなる半導体装置の製造方法において、 前記２つの半導体素子が相対向する面上に素子間の傾き
を補正するための傾き補正層を形成し、その後、前記２
つの半導体素子を互いに対向させて加熱加圧することに
よりバンプ接合することを特徴とする半導体装置の製造
方法。1. A method for manufacturing a semiconductor device comprising two semiconductor elements opposed to each other and bump-bonded to each other, wherein an inclination correction layer for correcting an inclination between elements is provided on a surface where the two semiconductor elements are opposed to each other. And then the above 2
A method of manufacturing a semiconductor device, comprising: bonding two semiconductor elements to each other so as to be heated and pressed to perform bump bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24947299A JP2001077295A (en) | 1999-09-03 | 1999-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24947299A JP2001077295A (en) | 1999-09-03 | 1999-09-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001077295A true JP2001077295A (en) | 2001-03-23 |
Family
ID=17193478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24947299A Withdrawn JP2001077295A (en) | 1999-09-03 | 1999-09-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001077295A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1321966A1 (en) * | 2001-12-21 | 2003-06-25 | Esec Trading S.A. | Gripping tool for mounting semiconductor chips |
| US7511380B2 (en) | 2002-12-19 | 2009-03-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor chip and method manufacturing the same |
| CN106206505A (en) * | 2015-05-29 | 2016-12-07 | 株式会社东芝 | Semiconductor device and the manufacture method of semiconductor device |
| JP2019083353A (en) * | 2019-03-11 | 2019-05-30 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN113506781A (en) * | 2021-06-08 | 2021-10-15 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
1999
- 1999-09-03 JP JP24947299A patent/JP2001077295A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1321966A1 (en) * | 2001-12-21 | 2003-06-25 | Esec Trading S.A. | Gripping tool for mounting semiconductor chips |
| US7511380B2 (en) | 2002-12-19 | 2009-03-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor chip and method manufacturing the same |
| CN106206505A (en) * | 2015-05-29 | 2016-12-07 | 株式会社东芝 | Semiconductor device and the manufacture method of semiconductor device |
| JP2016225466A (en) * | 2015-05-29 | 2016-12-28 | 株式会社東芝 | Semiconductor device and semiconductor device manufacturing method |
| JP2019083353A (en) * | 2019-03-11 | 2019-05-30 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN113506781A (en) * | 2021-06-08 | 2021-10-15 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
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