JP3644678B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP3644678B2
JP3644678B2 JP2001021987A JP2001021987A JP3644678B2 JP 3644678 B2 JP3644678 B2 JP 3644678B2 JP 2001021987 A JP2001021987 A JP 2001021987A JP 2001021987 A JP2001021987 A JP 2001021987A JP 3644678 B2 JP3644678 B2 JP 3644678B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
recess
conductive film
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001021987A
Other languages
Japanese (ja)
Other versions
JP2002231878A (en
Inventor
康博 手嶋
康一郎 岡村
正明 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001021987A priority Critical patent/JP3644678B2/en
Publication of JP2002231878A publication Critical patent/JP2002231878A/en
Application granted granted Critical
Publication of JP3644678B2 publication Critical patent/JP3644678B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを異方性導電フィルムを用いたフリップチップ接続により基板に接続した半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
図３は、従来の一般的な半導体装置の封止方法を示す断面図である。図において、２は半導体チップ、３は半導体チップ２の端子（図示せず）とパッケージ７の端子（図示せず）を接続するワイヤ、８はキャップ、９は封止剤をそれぞれ示している。この従来方法は、半田や樹脂等の封止剤９を用いてキャップ８をパッケージ７に固定するものであり、キャップ８をパッケージ７上に載せた状態でキュアすることにより封止が完了する。また、図４は従来の他の半導体装置の封止方法を示す断面図である。図において、１は基板、３は半導体チップ２の端子と基板１の端子を接続するワイヤ、４は外部用の半田ボール、１０はポッティング剤を示している。この従来方法では、ワイヤ・ウエッジボンディングを行った半導体チップ２をポッティング剤１０により封止し、外部からの応力に対する強度を確保している。
【０００３】
さらに、図５は特開平１１−５４６４８号広報にて提示された複数の半導体チップを搭載したマルチチップモジュールを示している。図において、２は半導体チップ、５はバンプ、６は異方性導電フィルム（Anisotropic conductive film ）、１１はパッケージ基板、１２は外部バンプ、２２はマザーチップである。この例では、マザーチップ２２と半導体チップ２、及びマザーチップ２２とパッケージ基板１１が異方性導電フィルム６を用いてフリップチップ接続されており、フリップチップの接続部に対して封止材を用いた封止を行わなくて済むため、封止工程を簡略化することができる。
【０００４】
【発明が解決しようとする課題】
しかしながら、図３に示すような従来の封止方法では、キュア中にキャップ８のずれが生じることがあり、封止が完全に行われないという問題があった。また、図４に示す従来方法では、ポッティング剤１０の硬化に時間を要するという問題があった。さらに、ポッティング剤１０の量が少ない場合にはワイヤ３が露出し、量が多い場合には他の部分に流れてしまうという問題があり、厳密な調整が必要であった。さらに、これらの従来の封止方法では、半導体チップ２の実装と封止はそれぞれ別の工程で作業が行われており、コスト高となっていた。また、半導体装置に封止用のスペースを確保する必要があるため、半導体装置の小型化が困難であった。
また、特開平１１−５４６４８号広報にて提示されたマルチチップモジュールでは、マザーチップ２２の実装後でなければマザーチップ２２に実装された半導体チップ２の良否が判定できないという問題点があった。
【０００５】
本発明は、上記のような問題点を解消するためになされたもので、半導体装置の実装工程及び封止工程を簡略化しコストの低減を図ると共に、半導体装置の小型化を図ることを目的とする。
【０００６】
【課題を解決するための手段】
本発明に係わる半導体装置は、凹部を有する基板と、この基板の上記凹部内に搭載されワイヤまたは突起電極により基板に接続された第一の半導体チップと、基板の凹部周縁に配設された熱可塑性樹脂よりなる異方性導電フィルムと、裏面に突起電極を有し、基板上に凹部を覆うように搭載された第二の半導体チップを備え、第二の半導体チップは、突起電極及び異方性導電フィルムにより基板にフリップチップ接続されており、第一の半導体チップは、異方性導電フィルムにより封止されているものである。
【０００７】
また、本発明に係わる半導体装置の製造方法は、第一の半導体チップを基板の凹部内に載置し、第一の半導体チップの端子と基板の端子を接続する工程と、基板の凹部周縁に熱可塑性樹脂よりなる異方性導電フィルムを貼り付ける工程と、第二の半導体チップ裏面の所定箇所に突起電極を形成する工程と、第二の半導体チップを基板の凹部を覆うように載置し、突起電極及び異方性導電フィルムにより第二の半導体チップを基板にフリップチップ接続すると共に、異方性導電フィルムにて第一の半導体チップを封止する工程を含んで製造するようにしたものである。
【０００８】
【発明の実施の形態】
実施の形態１．
以下に、本発明の実施の形態を図面に基づいて説明する。図１は、本発明の実施の形態１である半導体装置を示す断面図である。図において、１は凹部１ａを有する基板、２ａは基板１の凹部１ａ内に搭載された第一の半導体チップで、本実施の形態では第一の半導体チップ２ａの端子（図示せず）と基板１の端子（図示せず）はワイヤ３にて接続されている。また、２ｂは裏面に突起電極であるバンプ５を有し、基板１上に凹部１ａを覆うように搭載された第二の半導体チップ、４は基板１の裏面に形成された外部用の半田ボール、６は基板１の凹部１ａ周縁に配設された熱可塑性樹脂よりなるフィルムで、本実施の形態では異方性導電フィルム（Anisotropic conductive film ）を用いている。
本実施の形態は、基板１の凹部１ａ内に搭載された第一の半導体チップ２ａと、基板１上に凹部１ａを覆うように搭載された第二の半導体チップ２ｂを備えた半導体装置において、第二の半導体チップ２ｂをバンプ５及び異方性導電フィルム６により基板１にフリップチップ接続すると共に、第一の半導体チップ２ａを異方性導電フィルム６により封止するものである。
【０００９】
本実施の形態における半導体装置の製造方法について説明する。まず、第一の半導体チップ２ａを基板１の凹部１ａ内に載置し、第一の半導体チップ２ａの端子と基板１の端子をワイヤ３にて接続する。次に、基板１の凹部１ａ周縁の所定箇所に異方性導電フィルム６を貼り付ける。続いて、第二の半導体チップ２ｂ裏面の所定箇所にバンプ５を形成する。その後、第二の半導体チップ２ｂを基板１の凹部１ａを覆うように載置し、バンプ５を基板１の凹部１ａ周縁に設けられた端子（図示せず）に整合した状態で加熱及び加圧する。これにより、熱可塑性樹脂よりなる異方性導電フィルム６が軟化し、フィルム内の導電性粒子同士が接触するため、第二の半導体チップ２ｂのバンプ５が基板１の端子に電気的に接続される。その後、異方性導電フィルム６は硬化し、第二の半導体チップ２ｂは基板１に機械的に接続された状態となる。その結果、バンプ５及び異方性導電フィルム６により第二の半導体チップ２ｂが基板１にフリップチップ接続されると共に、異方性導電フィルム６にて第一の半導体チップ２ａが封止される。
【００１０】
本実施の形態における半導体チップ２ａは、外部からの応力に弱いワイヤ・ウエッジボンディングにより基板１に接続されており、封止が必要である。本実施の形態によれば、基板１と半導体チップ２ｂの接続を完了すると同時に、半導体チップ２ａの封止を完了することができるため、従来の実装工程と封止工程が簡略化され、コストを低減することができる。また、封止用のスペースを確保する必要がないため、半導体装置の小型化が図られる。さらに、半導体チップ２ａの良否を確認後、半導体チップ２ｂを実装することができるため、複数の半導体チップを搭載する半導体装置としては高い歩留まりで製造できる。
【００１１】
実施の形態２．
図２は、本発明の実施の形態２である半導体装置を示す断面図である。図において、２ｃは第一の半導体チップ、５ｃは第一の半導体チップ２ｃの裏面に形成された突起電極であるバンプである。なお、図中、同一、相当部分には同一符号を付し、説明を省略する。本実施の形態は、第一の半導体チップ２ｃがバンプ５ｃにより基板１の端子（図示せず）に接続されていること以外は上記実施の形態１と同様の構造及び製造方法である。
上記実施の形態１では、外部からの応力に弱いワイヤ・ウエッジボンディングにより基板１に接続された第一の半導体チップ２ａを封止するために本発明を適用したが、本実施の形態のようにフリップチップ接続が用いられた第一の半導体チップ２ｃを封止する際にも同様に適用することができ、工程の簡略化によるコスト低減、半導体装置の小型化等の効果が得られる。
【００１２】
なお、上記実施の形態１及び実施の形態２では、第二の半導体チップ２ｂと基板１の接続及び第一の半導体チップ２ａ（２ｃ）の封止に用いる熱可塑性樹脂よりなるフィルムとして異方性導電フィルム６を用いたが、非導電性フィルム（Non conductive film ）を用いる半導体装置の場合にも本発明は適用可能であり、同様の効果が得られる。
【００１３】
【発明の効果】
以上のように、本発明によれば、基板の凹部内に搭載された第一の半導体チップと、基板上に凹部を覆うように搭載された第二の半導体チップを備えた半導体装置において、第二の半導体チップを突起電極及び熱可塑性樹脂よりなるフィルムにより基板にフリップチップ接続すると共に、第一の半導体チップをフィルムにより封止するようにしたので、従来の実装工程と封止工程が簡略化され、コストを低減することができる。さらに、封止用のスペースを確保する必要がないため、半導体装置の小型化が図られる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１である半導体装置を示す断面図である。
【図２】 本発明の実施の形態２である半導体装置を示す断面図である。
【図３】 従来の半導体装置を示す断面図である。
【図４】 従来の他の半導体装置を示す断面図である。
【図５】 従来の他の半導体装置を示す断面図である。
【符号の説明】
１ 基板、１ａ 凹部、２ 半導体チップ、
２ａ、２ｃ 第一の半導体チップ、２ｂ 第二の半導体チップ、
３ ワイヤ、４ 半田ボール、５、５ｃ バンプ、６ 異方性導電フィルム、
７ パッケージ、８ キャップ、９ 封止剤、１０ ポッティング剤、
１１ パッケージ基板、１２ 外部バンプ、２２ マザーチップ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor chip is connected to a substrate by flip chip connection using an anisotropic conductive film and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 3 is a cross-sectional view showing a conventional general semiconductor device sealing method. In the figure, 2 is a semiconductor chip, 3 is a wire connecting a terminal (not shown) of the semiconductor chip 2 and a terminal (not shown) of the package 7, 8 is a cap, and 9 is a sealing agent. In this conventional method, the cap 8 is fixed to the package 7 by using a sealing agent 9 such as solder or resin, and the sealing is completed by curing the cap 8 on the package 7. FIG. 4 is a sectional view showing another conventional method for sealing a semiconductor device. In the figure, 1 is a substrate, 3 is a wire connecting a terminal of the semiconductor chip 2 and a terminal of the substrate 1, 4 is a solder ball for external use, and 10 is a potting agent. In this conventional method, the semiconductor chip 2 subjected to wire / wedge bonding is sealed with a potting agent 10 to ensure strength against external stress.
[0003]
Further, FIG. 5 shows a multi-chip module on which a plurality of semiconductor chips provided in Japanese Patent Application Laid-Open No. 11-54648 are mounted. In the figure, 2 is a semiconductor chip, 5 is a bump, 6 is an anisotropic conductive film, 11 is a package substrate, 12 is an external bump, and 22 is a mother chip. In this example, the mother chip 22 and the semiconductor chip 2, and the mother chip 22 and the package substrate 11 are flip-chip connected using the anisotropic conductive film 6, and a sealing material is used for the connection part of the flip chip. Therefore, the sealing process can be simplified.
[0004]
[Problems to be solved by the invention]
However, the conventional sealing method as shown in FIG. 3 has a problem that the cap 8 may be displaced during the curing, and the sealing is not performed completely. Further, the conventional method shown in FIG. 4 has a problem that it takes time to cure the potting agent 10. Further, there is a problem that when the amount of the potting agent 10 is small, the wire 3 is exposed, and when the amount is large, the wire 3 flows to other portions, and strict adjustment is necessary. Furthermore, in these conventional sealing methods, the mounting and sealing of the semiconductor chip 2 are performed in separate steps, which increases the cost. In addition, since it is necessary to secure a sealing space in the semiconductor device, it is difficult to reduce the size of the semiconductor device.
Further, the multi-chip module presented in Japanese Patent Application Laid-Open No. 11-54648 has a problem that the quality of the semiconductor chip 2 mounted on the mother chip 22 can be determined only after the mother chip 22 is mounted.
[0005]
The present invention has been made to solve the above-described problems, and aims to simplify the mounting process and the sealing process of the semiconductor device, reduce the cost, and reduce the size of the semiconductor device. To do.
[0006]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes a substrate having a recess, a first semiconductor chip mounted in the recess of the substrate and connected to the substrate by a wire or a protruding electrode, and a heat disposed on the periphery of the recess of the substrate. an anisotropic conductive film made of a thermoplastic resin, has a protruding electrode on the back surface comprises a second semiconductor chip mounted so as to cover the recess on the substrate, the second semiconductor chip, the projection electrodes and anisotropic Seishirubeden are flip-chip connected to the substrate by the film, the first semiconductor chip are those which are sealed by the anisotropic conductive film.
[0007]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: placing a first semiconductor chip in a recess of a substrate; connecting a terminal of the first semiconductor chip to a terminal of the substrate; A process of attaching an anisotropic conductive film made of a thermoplastic resin, a process of forming a protruding electrode at a predetermined position on the back surface of the second semiconductor chip, and a second semiconductor chip placed so as to cover the concave portion of the substrate In addition, the second semiconductor chip is flip-chip connected to the substrate by the protruding electrode and the anisotropic conductive film, and the first semiconductor chip is sealed by the anisotropic conductive film. It is.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In the figure, 1 is a substrate having a recess 1a, 2a is a first semiconductor chip mounted in the recess 1a of the substrate 1, and in this embodiment, a terminal (not shown) and a substrate of the first semiconductor chip 2a. One terminal (not shown) is connected by a wire 3. 2b has a bump 5 which is a protruding electrode on the back surface, a second semiconductor chip mounted on the substrate 1 so as to cover the recess 1a, and 4 an external solder ball formed on the back surface of the substrate 1. , 6 is a film made of a thermoplastic resin disposed on the periphery of the concave portion 1a of the substrate 1, and an anisotropic conductive film is used in this embodiment.
The present embodiment is a semiconductor device including a first semiconductor chip 2a mounted in the recess 1a of the substrate 1 and a second semiconductor chip 2b mounted on the substrate 1 so as to cover the recess 1a. The second semiconductor chip 2 b is flip-chip connected to the substrate 1 by the bumps 5 and the anisotropic conductive film 6, and the first semiconductor chip 2 a is sealed by the anisotropic conductive film 6.
[0009]
A method for manufacturing a semiconductor device in the present embodiment will be described. First, the first semiconductor chip 2 a is placed in the recess 1 a of the substrate 1, and the terminal of the first semiconductor chip 2 a and the terminal of the substrate 1 are connected by the wire 3. Next, the anisotropic conductive film 6 is affixed to a predetermined location on the periphery of the recess 1 a of the substrate 1. Subsequently, bumps 5 are formed at predetermined locations on the back surface of the second semiconductor chip 2b. Thereafter, the second semiconductor chip 2b is placed so as to cover the concave portion 1a of the substrate 1, and the bumps 5 are heated and pressed in a state of being aligned with terminals (not shown) provided on the peripheral edge of the concave portion 1a of the substrate 1. . As a result, the anisotropic conductive film 6 made of thermoplastic resin is softened and the conductive particles in the film come into contact with each other, so that the bumps 5 of the second semiconductor chip 2b are electrically connected to the terminals of the substrate 1. The Thereafter, the anisotropic conductive film 6 is cured, and the second semiconductor chip 2 b is mechanically connected to the substrate 1. As a result, the second semiconductor chip 2 b is flip-chip connected to the substrate 1 by the bumps 5 and the anisotropic conductive film 6, and the first semiconductor chip 2 a is sealed by the anisotropic conductive film 6.
[0010]
The semiconductor chip 2a in the present embodiment is connected to the substrate 1 by wire / wedge bonding which is weak against external stress and needs to be sealed. According to the present embodiment, since the connection between the substrate 1 and the semiconductor chip 2b can be completed simultaneously with the sealing of the semiconductor chip 2a, the conventional mounting process and the sealing process are simplified, and the cost is reduced. Can be reduced. Further, since it is not necessary to secure a sealing space, the semiconductor device can be reduced in size. Furthermore, since the semiconductor chip 2b can be mounted after confirming the quality of the semiconductor chip 2a, a semiconductor device on which a plurality of semiconductor chips are mounted can be manufactured with a high yield.
[0011]
Embodiment 2. FIG.
FIG. 2 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. In the figure, reference numeral 2c denotes a first semiconductor chip, and 5c denotes a bump which is a protruding electrode formed on the back surface of the first semiconductor chip 2c. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof is omitted. The present embodiment is the same structure and manufacturing method as in the first embodiment except that the first semiconductor chip 2c is connected to the terminal (not shown) of the substrate 1 by the bump 5c.
In the first embodiment, the present invention is applied to seal the first semiconductor chip 2a connected to the substrate 1 by wire / wedge bonding which is weak against external stress. However, as in the present embodiment, The same can be applied to the sealing of the first semiconductor chip 2c using the flip chip connection, and effects such as cost reduction by simplification of the process and size reduction of the semiconductor device can be obtained.
[0012]
In the first and second embodiments, the film made of a thermoplastic resin used for the connection between the second semiconductor chip 2b and the substrate 1 and the sealing of the first semiconductor chip 2a (2c) is anisotropic. Although the conductive film 6 is used, the present invention can also be applied to a semiconductor device using a non-conductive film, and similar effects can be obtained.
[0013]
【The invention's effect】
As described above, according to the present invention, in the semiconductor device including the first semiconductor chip mounted in the recess of the substrate and the second semiconductor chip mounted on the substrate so as to cover the recess, Since the second semiconductor chip is flip-chip connected to the substrate with a film made of protruding electrodes and thermoplastic resin, and the first semiconductor chip is sealed with the film, the conventional mounting process and sealing process are simplified. The cost can be reduced. Further, since it is not necessary to secure a sealing space, the semiconductor device can be downsized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a conventional semiconductor device.
FIG. 4 is a cross-sectional view showing another conventional semiconductor device.
FIG. 5 is a cross-sectional view showing another conventional semiconductor device.
[Explanation of symbols]
1 substrate, 1a recess, 2 semiconductor chip,
2a, 2c first semiconductor chip, 2b second semiconductor chip,
3 wire, 4 solder ball, 5 5c bump, 6 anisotropic conductive film,
7 package, 8 cap, 9 sealant, 10 potting agent,
11 Package substrate, 12 External bump, 22 Mother chip.

Claims (2)

凹部を有する基板と、この基板の上記凹部内に搭載されワイヤまたは突起電極により上記基板に接続された第一の半導体チップと、上記基板の上記凹部周縁に配設された熱可塑性樹脂よりなる異方性導電フィルムと、裏面に突起電極を有し、上記基板上に上記凹部を覆うように搭載された第二の半導体チップを備え、上記第二の半導体チップは、上記突起電極及び上記異方性導電フィルムにより上記基板にフリップチップ接続されており、上記第一の半導体チップは、上記異方性導電フィルムにより封止されていることを特徴とする半導体装置。A substrate having a concave portion, a first semiconductor chip connected to the substrate by wire or protruding electrodes are mounted on the inside recess of the substrate, different made of a thermoplastic resin disposed on the recess periphery of the substrate and anisotropic conductive film has a protruding electrode on the back surface comprises a second semiconductor chip mounted so as to cover the recess on the substrate, the second semiconductor chip, the protruding electrodes and the anisotropically the Seishirubeden film are flip-chip connected to the substrate, said first semiconductor chip, the semiconductor device characterized in that it is sealed by the anisotropic conductive film. 第一の半導体チップを基板の凹部内に載置し、上記第一の半導体チップの端子と上記基板の端子を接続する工程、
上記基板の上記凹部周縁に熱可塑性樹脂よりなる異方性導電フィルムを貼り付ける工程、
第二の半導体チップ裏面の所定箇所に突起電極を形成する工程、
上記第二の半導体チップを上記基板の上記凹部を覆うように載置し、上記突起電極及び上記異方性導電フィルムにより上記第二の半導体チップを上記基板にフリップチップ接続すると共に、上記異方性導電フィルムにて上記第一の半導体チップを封止する工程を含むことを特徴とする半導体装置の製造方法。Placing the first semiconductor chip in the recess of the substrate and connecting the terminal of the first semiconductor chip and the terminal of the substrate;
A step of attaching an anisotropic conductive film made of a thermoplastic resin to the periphery of the recess of the substrate;
Forming a protruding electrode at a predetermined location on the back surface of the second semiconductor chip;
Said second semiconductor chip is placed so as to cover the recess portion of the substrate, the second semiconductor chip with flip-chip connected to the substrate by the projection electrodes and the anisotropic conductive film, the anisotropic A method for manufacturing a semiconductor device, comprising: sealing the first semiconductor chip with a conductive conductive film.
JP2001021987A 2001-01-30 2001-01-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3644678B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001021987A JP3644678B2 (en) 2001-01-30 2001-01-30 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001021987A JP3644678B2 (en) 2001-01-30 2001-01-30 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2002231878A JP2002231878A (en) 2002-08-16
JP3644678B2 true JP3644678B2 (en) 2005-05-11

Family

ID=18887458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001021987A Expired - Fee Related JP3644678B2 (en) 2001-01-30 2001-01-30 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3644678B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4835058B2 (en) * 2005-07-26 2011-12-14 パナソニック電工株式会社 Sensor package
JP4901458B2 (en) * 2006-12-26 2012-03-21 新光電気工業株式会社 Electronic component built-in substrate

Also Published As

Publication number Publication date
JP2002231878A (en) 2002-08-16

Similar Documents

Publication Publication Date Title
KR100219791B1 (en) Semiconductor device manufacture thereof and manufacture of leadframe
TWI527175B (en) Etch-back type semiconductor package, substrate and manufacturing method thereof
US6515357B2 (en) Semiconductor package and semiconductor package fabrication method
JPH11260856A (en) Semiconductor device and its manufacture and mounting structure of the device
US6002171A (en) Integrated heat spreader/stiffener assembly and method of assembly for semiconductor package
KR20040100997A (en) Semiconductor device and manufacturing method thereof
JP3418385B2 (en) Method of forming semiconductor integrated circuit package and method of manufacturing the same
US20060214308A1 (en) Flip-chip semiconductor package and method for fabricating the same
JP2003197853A (en) Method and apparatus of manufacturing semiconductor device
JP3644678B2 (en) Semiconductor device and manufacturing method thereof
JP2002110856A (en) Manufacturing method of semiconductor device
JP2000114426A (en) Single-sided resin sealing type semiconductor device
JPH10125734A (en) Semiconductor unit and manufacturing method thereof
JP3715861B2 (en) Assembling method of semiconductor device
JP3014577B2 (en) Method for manufacturing semiconductor device
JP2001267366A (en) Method of packaging semiconductor and printed circuit board
JP4441090B2 (en) Method of mounting a semiconductor chip on a printed wiring board
JPH09246464A (en) Semiconductor device and manufacture thereof
US6537858B1 (en) Method for manufacturing semiconductor device
TWI277184B (en) Flip-chip leadframe type package and fabrication method thereof
JP2002124627A (en) Semiconductor device and its manufacturing method
US20040157359A1 (en) Method for planarizing bumped die
JP2001077295A (en) Manufacture of semiconductor device
JP3147106B2 (en) Semiconductor device
JPH06209071A (en) Resin sealed type semiconductor device and its manufacture

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040618

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040629

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040818

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050125

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050131

LAPS Cancellation because of no payment of annual fees