JP3147106B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3147106B2 JP3147106B2 JP33346698A JP33346698A JP3147106B2 JP 3147106 B2 JP3147106 B2 JP 3147106B2 JP 33346698 A JP33346698 A JP 33346698A JP 33346698 A JP33346698 A JP 33346698A JP 3147106 B2 JP3147106 B2 JP 3147106B2
- Authority
- JP
- Japan
- Prior art keywords
- interposer substrate
- semiconductor chip
- bump
- semiconductor device
- hollow portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、ＧａＡｓＦＥＴのような高周波デバイスであ
り、かつ小型パッケージ化が望まれる半導体装置におい
て、半導体チップとインターポーザ基板との間を中空構
造とし、かつフリップチップ実装構造とすることによ
り、小型化を達成すると共に、高周波特性と信頼性を向
上した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which is a high-frequency device such as a GaAs FET and requires a small package, and has a hollow structure between a semiconductor chip and an interposer substrate. In addition, the present invention relates to a semiconductor device which achieves miniaturization and has improved high frequency characteristics and reliability by adopting a flip chip mounting structure.
【０００２】[0002]
【従来の技術】フリップチップ実装構造を持ち、かつ中
空構造を有する半導体装置の従来例としては、例えば、
特開平５−２１８２２２号公報に開示された半導体装置
とその組立て方法がある。この発明では、チップ部を包
み込んでいたエポキシ樹脂が、モールド樹脂封止時の熱
によってモールド樹脂部材に吸収されることによって中
空構造を造りだす手段を実施例としている。2. Description of the Related Art As a conventional example of a semiconductor device having a flip chip mounting structure and a hollow structure, for example,
There is a semiconductor device disclosed in JP-A-5-218222 and a method of assembling the same. In this embodiment, a means for creating a hollow structure by absorbing the epoxy resin that has wrapped the chip portion into the mold resin member by the heat at the time of molding resin sealing is taken as an embodiment.
【０００３】また、特開平５−２１８２３０号公報に開
示された半導体装置では、半導体素子と光透過用ガラス
基板の間を中空にし、少なくとも該半導体素子を樹脂に
より被覆することを開示しているが、その実施例として
は、樹脂をポッティングにより滴下する手段としてい
る。Further, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 5-218230, it is disclosed that a space is provided between a semiconductor element and a glass substrate for light transmission, and at least the semiconductor element is covered with a resin. As an example, a means for dropping a resin by potting is used.
【０００４】また、特開平１０−１２５８２５号公報に
開示されている構造があるが、この封止構造では、封止
用フィルムを、接着剤を用いて誘電体基板に接着してい
る。なお、高周波用半導体装置として発明された先願の
特開平３−６４０３３号公報に開示された構造において
は、上記封止用フィルムと誘電体基板との接続に、ワイ
ヤボンディングを使用している。Further, there is a structure disclosed in Japanese Patent Application Laid-Open No. 10-125825. In this sealing structure, a sealing film is bonded to a dielectric substrate using an adhesive. In the structure disclosed in Japanese Patent Application Laid-Open No. 3-64033, which was invented as a high-frequency semiconductor device, wire bonding is used to connect the sealing film and the dielectric substrate.
【０００５】[0005]
【発明が解決しようとする課題】ところで、先顔の特開
平１０−１２５８２５号公報、特開平３−６４０３３号
公報に開示されている構造の場合、（１）接着界面の耐
湿性が問題である点、（２）フィルム接着の為の費用
（フィルム材料費及び供給・接着加工費）分だけ製造原
価が増加してしまう点、（３）アンダーフィルが無いた
め、熱応力の緩和が出来ず、ペレットクラックが発生し
易い点、等が問題点となる。また、アンダーフィルを用
いる他の従来のフリップチップ構造の場合、半導体チッ
プのアクティブ回路面が基板の回路と接近していること
が問題点となる。すなわち、その寄生容量に係わる誘電
率は、アンダーフィルの比誘電率に依存しており、本発
明に係る半導体装置のような中空構造に比べて、誘電率
が高くなくなることが避けられず、従って、寄生容量を
大きくすることにより、高周波特性を悪くしていた。However, in the case of the structures disclosed in Japanese Patent Application Laid-Open Nos. 10-125825 and 3-64033, (1) the moisture resistance of the bonding interface is a problem. Point, (2) the cost of film bonding (film material cost and supply / adhesion processing cost) increases manufacturing costs, and (3) thermal stress cannot be reduced because there is no underfill. Pellet cracks tend to occur, which is a problem. In the case of another conventional flip-chip structure using underfill, there is a problem that the active circuit surface of the semiconductor chip is close to the circuit of the substrate. That is, the dielectric constant related to the parasitic capacitance depends on the relative dielectric constant of the underfill, and it is inevitable that the dielectric constant becomes higher than that of a hollow structure such as a semiconductor device according to the present invention. In addition, the high frequency characteristics are deteriorated by increasing the parasitic capacitance.
【０００６】また、高周波用としての中空構造を有する
半導体装置としては、従来セラミック等の基板に半導体
チップをダイボンドし、金線を用いてワイヤボンディン
グした後、接着剤付きのキャップを被せたりしていた
が、この場合、ワイヤボンディングしているので、フリ
ップチップ実装構造に比べると、（１）小型化が図れな
い点、（２）ワイヤ長分の寄生抵抗及び寄生リアクタン
スが大きくなってしまう点、（３）接着剤にて封止して
いるので、接着界面の耐湿性が問題である点が欠点とな
る。Further, as a semiconductor device having a hollow structure for high frequency, a semiconductor chip is conventionally die-bonded to a substrate such as a ceramic, wire-bonded with a gold wire, and then covered with a cap with an adhesive. However, in this case, since wire bonding is performed, (1) a reduction in size cannot be achieved, (2) a parasitic resistance and a parasitic reactance corresponding to a wire length increase in comparison with the flip-chip mounting structure, (3) Since it is sealed with an adhesive, there is a disadvantage in that the moisture resistance of the bonding interface is a problem.
【０００７】上記の寄生容量の問題点は、セラミック・
パッケージを使用すれば、改善することができる。それ
故、超高周波用半導体装置のパッケージには、セラミッ
ク・パッケージが使用されている。しかし、セラミック
・パッケージの使用は、民生用用途の半導体としてはコ
ストアップとなる。[0007] The problem of the parasitic capacitance is that ceramic
Using packages can help. Therefore, a ceramic package is used for a package of a semiconductor device for ultrahigh frequency. However, the use of the ceramic package increases the cost as a semiconductor for consumer use.
【０００８】また、特開平５−２１８２２２号公報に開
示された封止手段では、中空部の容積にムラが生じ、均
一な特性が確保できない。さらに、特開平５−２１８２
３０号公報に開示された封止方法では、封止樹脂の厚み
が一定しないし、封止に要する時間が長くなる。Further, in the sealing means disclosed in Japanese Patent Application Laid-Open No. 5-218222, unevenness occurs in the volume of the hollow portion, and uniform characteristics cannot be secured. Further, Japanese Unexamined Patent Application Publication No.
In the sealing method disclosed in Japanese Patent Publication No. 30, the thickness of the sealing resin is not constant, and the time required for sealing becomes long.
【０００９】本発明は、以上のような従来の半導体装置
における問題点に鑑みてなされたものであり、フリップ
チップ方式等の実装構造を用いて小型化される樹脂パッ
ケージ型の半導体装置において、高周波特性と耐湿性を
向上し、かつ均一特性を得ることができる半導体装置と
その簡単な製造方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional semiconductor device, and has been developed in a resin package type semiconductor device which is miniaturized by using a mounting structure such as a flip chip method. It is an object of the present invention to provide a semiconductor device capable of improving characteristics and moisture resistance and obtaining uniform characteristics, and a simple manufacturing method thereof.
【００１０】[0010]
【課題を解決するための手段】上記の課題を解決するた
めに、本発明に係る半導体装置は、「インターポーザ基
板と、該インターポーザ基板上に中空部と該中空部内の
バンプとを介してフリップチップ実装された半導体チッ
プを有する高周波用の半導体装置において、前記半導体
チップの電極部に前記パンプを形成することにより、該
形成されたバンプを前記半導体チップのバンプ電極とす
る手段と、前記インターポーザ基板内の前記バンプ電極
の直下にＶＩＡホールを設け、前記バンプ電極を該ＶＩ
Ａホールに通して前記インターポーザ基板裏面に設置し
たランドに接続することにより、該ランドを前記半導体
チップの外部電極とする手段と、前記インターポーザ基
板の水平を保ちながら、高粘度のアンダーフィル材を前
記バンプ周辺を含む前記半導体チップ周辺に塗布するこ
とにより、前記中空部を所定の形状と所定の容積と所定
の機械的強度を持たせて確保する手段と、前記半導体チ
ップ以下の前記インターポーザ基板上の構造物全体を、
前記インターポーザ基板上に樹脂封止する手段とにより
製造したことを特徴とする半導体装置」（請求項１）を
特徴とし、これにより上記目的を達成することができ
る。In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises an interposer substrate, a flip chip on the interposer substrate, with a hollow portion and a bump in the hollow portion interposed therebetween. A high-frequency semiconductor device having a mounted semiconductor chip, wherein the pump is formed in an electrode portion of the semiconductor chip so that the formed bump is used as a bump electrode of the semiconductor chip; A VIA hole is provided immediately below the bump electrode, and the bump electrode is connected to the VIA hole.
By connecting the land to the land provided on the back surface of the interposer substrate through the A hole, the land is used as an external electrode of the semiconductor chip, and a high-viscosity underfill material is formed while keeping the interposer substrate horizontal. Means for securing the hollow portion to have a predetermined shape, a predetermined volume, and a predetermined mechanical strength by applying to the periphery of the semiconductor chip including the periphery of the bump; and a means for securing the hollow portion on the interposer substrate below the semiconductor chip. The whole structure,
A semiconductor device manufactured by means of resin sealing on the interposer substrate "(claim 1), whereby the above object can be achieved.
【００１１】また、上記の課題を解決するために、本発
明に係る半導体装置は、「インターポーザ基板と、該イ
ンターポーザ基板上に中空部と該中空部内のバンプとを
介してフリップチップ実装された半導体チップを有する
高周波用の半導体装置において、前記半導体チップの電
極部に前記パンプを形成することにより、該形成された
バンプを前記半導体チップのバンプ電極とする手段と、
前記インターポーザ基板の上部周辺部に熱硬化性樹脂を
印刷又はディスプペンスして塗布する手段と、前記熱硬
化性樹脂が印刷又はディスプペンスして塗布された前記
インターポーザ基板の上面に、前記バンプ電極が形成さ
れた半導体チップを、前記バンプ電極を下にしてフェイ
スダウンした後、前記熱硬化性樹脂をキュアすることに
より、前記中空部を所定の形状と所定の容積と所定の機
械的強度を持たせて確保する手段と、前記半導体チップ
以下の前記インターポーザ基板上の構造物全体を、前記
インターポーザ基板上に樹脂封止する手段とにより製造
したことを特徴とする半導体装置」（請求項２）を特徴
とし、これにより上記目的を達成することができる。According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor device mounted on an interposer substrate by flip-chip mounting via a hollow portion and a bump in the hollow portion on the interposer substrate; In a high-frequency semiconductor device having a chip, by forming the pump in the electrode portion of the semiconductor chip, means for forming the formed bumps as bump electrodes of the semiconductor chip,
Means for printing or dispensing and applying a thermosetting resin to the upper peripheral portion of the interposer substrate, and the bump electrode is formed on the upper surface of the interposer substrate on which the thermosetting resin is printed or dispensed and applied. After the formed semiconductor chip is face-down with the bump electrodes facing down, the thermosetting resin is cured so that the hollow portion has a predetermined shape, a predetermined volume, and a predetermined mechanical strength. A semiconductor device which is manufactured by means for securing the entire structure on the interposer substrate below the semiconductor chip by means of resin sealing on the interposer substrate. Thereby, the above object can be achieved.
【００１２】さらに、上記半導体装置において、 ・前記樹脂封止手段として、トランスファーモールドを
使用したこと（請求項３）、 ・前記バンプを形成する手段として、拡散形成又はボン
ダーを使用したこと（請求項４）、 ・前記バンプの材質を、金又は半田材としたこと（請求
項５）、 ・前記インターポーザ基板の材質を、樹脂系又はセラミ
ック系としたこと（請求項６）、 を特徴とする。Further, in the above semiconductor device, a transfer mold is used as the resin sealing means (Claim 3); and a diffusion forming or a bonder is used as a means for forming the bumps (Claim 3). 4) The material of the bumps is gold or solder (Claim 5). The material of the interposer substrate is resin or ceramic (Claim 6).
【００１３】また、上記の課題を解決するために、本発
明に係る半導体装置は、「インターポーザ基板と、該イ
ンターポーザ基板上に中空部と該中空部内のバンプとを
介してフリップチップ実装された半導体チップを有する
高周波用の半導体装置の製造方法において、前記半導体
チップの電極部に前記パンプを形成することにより、該
形成されたバンプを前記半導体チップのバンプ電極とす
るステップと、前記インターポーザ基板内の前記バンプ
電極の直下にＶＩＡホールを設け、前記バンプ電極を該
ＶＩＡホールに通して前記インターポーザ基板裏面に設
置したランドに接続することにより、該ランドを前記半
導体チップの外部電極とするステップと、前記インター
ポーザ基板の水平を保ちながら、高粘度のアンダーフィ
ル材を前記バンプ周辺を含む前記半導体チップ周辺に塗
布することにより、前記中空部を所定の形状と所定の容
積と所定の機械的強度を持たせて確保するステップと、
前記半導体チップ以下の前記インターポーザ基板上の構
造物全体を、前記インターポーザ基板上に樹脂封止する
ステップとを有することを特徴とする半導体装置の製造
方法」（請求項７）を特徴とし、これにより上記目的を
達成することができる。According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor device mounted on an interposer substrate by flip-chip mounting on the interposer substrate via a hollow portion and a bump in the hollow portion; In the method of manufacturing a high-frequency semiconductor device having a chip, the step of forming the bump on an electrode portion of the semiconductor chip to use the formed bump as a bump electrode of the semiconductor chip; Providing a VIA hole immediately below the bump electrode, connecting the bump electrode to a land provided on the back surface of the interposer substrate through the VIA hole, and setting the land as an external electrode of the semiconductor chip; While maintaining the level of the interposer substrate, apply a high-viscosity underfill material to the bumps. By applying the semiconductor chip periphery comprising sides, a step of securing the hollow portion to have a predetermined mechanical strength and a predetermined shape and a predetermined volume,
And a step of resin-sealing the entire structure on the interposer substrate below the semiconductor chip on the interposer substrate ”(claim 7). The above object can be achieved.
【００１４】さらに、上記の課題を解決するために、本
発明に係る半導体装置は、「インターポーザ基板と、該
インターポーザ基板上に中空部と該中空部内のバンプと
を介してフリップチップ実装された半導体チップを有す
る高周波用の半導体装置の製造方法において、前記半導
体チップの電極部に前記パンプを形成することにより、
該形成されたバンプを前記半導体チップのバンプ電極と
するステップと、前記インターポーザ基板の上部周辺部
に熱硬化性樹脂を印刷又はディスプペンスして塗布する
ステップと、前記熱硬化性樹脂が印刷又はディスプペン
スして塗布された前記インターポーザ基板の上面に、前
記バンプ電極が形成された半導体チップを、前記バンプ
電極を下にしてフェイスダウンした後、前記熱硬化性樹
脂をキュアすることにより、前記中空部を所定の形状と
所定の容積と所定の機械的強度を持たせて確保するステ
ップと、前記半導体チップ以下の前記インターポーザ基
板上の構造物全体を、前記インターポーザ基板上に樹脂
封止するステップとを有することを特徴とする半導体装
置の製造方法」（請求項８）を特徴とし、これにより上
記目的を達成することができる。Further, in order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a semiconductor device which is mounted on an interposer substrate by flip-chip mounting on the interposer substrate via a hollow portion and a bump in the hollow portion. In the method of manufacturing a high-frequency semiconductor device having a chip, by forming the pump in the electrode portion of the semiconductor chip,
Using the formed bumps as bump electrodes of the semiconductor chip; printing or dispensing a thermosetting resin on an upper peripheral portion of the interposer substrate; and printing or dispensing the thermosetting resin on the interposer substrate. On the upper surface of the interposer substrate, which has been applied by applying, the semiconductor chip having the bump electrodes formed thereon is face-down with the bump electrodes facing down, and then the thermosetting resin is cured to cure the hollow portion. Securing a predetermined shape, a predetermined volume and a predetermined mechanical strength, and a step of resin-sealing the entire structure on the interposer substrate below the semiconductor chip on the interposer substrate. A method for manufacturing a semiconductor device characterized by having "(claim 8), thereby achieving the above object. Door can be.
【００１５】請求項１に係る半導体装置の作用を説明す
ると、ＧａＡｓＦＥＴのような高周波デバイスに適用さ
れ、かつ小型パッケージ化が望まれる半導体装置におい
て、図１に示す様に、半導体チップとインターポーザ基
板との間を中空構造にして、かつ、半導体チップをフリ
ップチップ実装構造とし、高粘度のアンダーフィル材を
バンプ周辺を含む半導体チップ周辺に塗布することによ
り、中空部を所定の形状と所定の容積と所定の機械的強
度を持たせて確保し、さらに上記構造物全体の外側を樹
脂封止する事により高信頼性と小型パッケージ化を達成
している。The operation of the semiconductor device according to the first aspect will be described. In a semiconductor device which is applied to a high-frequency device such as a GaAs FET and is desired to be miniaturized in a package, as shown in FIG. The hollow portion has a hollow structure, and the semiconductor chip has a flip-chip mounting structure, and a high-viscosity underfill material is applied to the periphery of the semiconductor chip including the periphery of the bump, so that the hollow portion has a predetermined shape and a predetermined volume. High reliability and a small package are achieved by securing a predetermined mechanical strength and securing the outside of the entire structure with a resin.
【００１６】請求項２に係る半導体装置の作用を説明す
ると、請求項１に係る半導体装置における高粘度のアン
ダーフィル材をバンプ周辺を含む半導体チップ周辺に塗
布する手段に代えて、予め、インターポーザ基板の上部
周辺部に熱硬化性樹脂を印刷又はディスプペンスして塗
布する手段を実施することにより、大量生産への移行を
可能にしている。請求項２に係る半導体装置の作用は、
トランスファ・モールドによる樹脂封止手段の採用によ
り、均質な半導体装置を短時間で製造することである。
請求項３乃至６に係る半導体装置の作用は、製造工程の
自由度を拡げることである。The operation of the semiconductor device according to the second aspect will be described. In place of the means for applying a high-viscosity underfill material around the semiconductor chip including the periphery of the bump in the semiconductor device according to the first aspect, an interposer substrate is previously provided. By implementing means for printing or dispensing and applying a thermosetting resin to the upper peripheral portion of the device, it is possible to shift to mass production. The operation of the semiconductor device according to claim 2 is as follows.
An object of the present invention is to manufacture a homogeneous semiconductor device in a short time by employing a resin sealing means by transfer molding.
The function of the semiconductor device according to claims 3 to 6 is to increase the degree of freedom of the manufacturing process.
【００１７】[0017]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。 （第１の実施の形態）図１は、本発明の第１の実施の形
態に係る半導体装置の構造を示す断面図である。図２
は、本発明の第１の実施の形態に係る半導体装置のバン
プ電極が形成された半導体チップの平面図である。Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG.
FIG. 2 is a plan view of a semiconductor chip on which bump electrodes of the semiconductor device according to the first embodiment of the present invention are formed.
【００１８】本実施の形態に係る半導体装置の構造は、
図１と図２に示すように、バンプ３周辺にバンプ電極２
を配した半導体チップ１と、インターポーザ基板４と
が、フリップチップ接続され、アンダーフィル５は、半
導体チップ１の周辺部にのみ塗布されており、半導体チ
ップ１の中央部は中空構造になっていて、さらにインタ
ーポーザ基板４の上部にのみ、樹脂６によるトランスフ
ァーモールド等の樹脂封止手段により封止された構造と
なっている。また、インターポーザ基板４には、予めＶ
ＩＡホール７が形成されており、その延長上の裏面にラ
ンド８を形成し、該ランド８が外部電極となる。The structure of the semiconductor device according to this embodiment is as follows.
As shown in FIG. 1 and FIG.
And the interposer substrate 4 are flip-chip connected, the underfill 5 is applied only to the peripheral portion of the semiconductor chip 1, and the central portion of the semiconductor chip 1 has a hollow structure. Further, only the upper portion of the interposer substrate 4 is sealed by a resin sealing means such as transfer molding with the resin 6. The interposer substrate 4 has a V
An IA hole 7 is formed, and a land 8 is formed on the back surface on the extension thereof, and the land 8 becomes an external electrode.
【００１９】以下、本発明の実施の形態に係る半導体装
置の製造方法を説明する。まず、図２に示すように、ペ
レット状の半導体チップ１の電極部２に、バンプ３を形
成する。その半導体チップ１を、図２に示す状態から、
バンプ３が下になるように反転し、フェイスダウンの状
態で、図１に示すようにインターポーザ基板４上にフリ
ップチップ実装する。Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. First, as shown in FIG. 2, bumps 3 are formed on the electrode portions 2 of the pellet-shaped semiconductor chip 1. The semiconductor chip 1 is moved from the state shown in FIG.
The flip 3 is flip-chip mounted on the interposer substrate 4 in a face-down state as shown in FIG.
【００２０】その後、高粘度のアンダーフィル５を半導
体チップ１の下部の四方より、バンプ３の周辺を含めて
半導体チップ１の周辺部にのみ塗布する。この時、高粘
度のアンダーフィル材を用いることと、アンダーフィル
塗布時にインターポーザ基板４をどの方向にも傾けず、
水平を保って塗布することによって、半導体チップ１の
中央部のアクティブ回路形成面の直下が、所定の形状で
所定の容積で所定の機械的強度を有した中空状態になる
ようにする。すなわち、上記の手段により、（製造され
る）どの半導体装置についても均質に、中空部９が形成
されることが保証される。その後、トランスファーモー
ルド等の封止手段により、半導体チップ１以下のインタ
ーポーザ基板４上の構造物全体（最外周）を、樹脂６に
よって封止して完成する。Thereafter, a high-viscosity underfill 5 is applied only from the four sides below the semiconductor chip 1 to the periphery of the semiconductor chip 1 including the periphery of the bumps 3. At this time, a high-viscosity underfill material is used, and the interposer substrate 4 is not tilted in any direction during underfill application.
By applying horizontally, the semiconductor chip 1 is placed in a hollow state having a predetermined shape, a predetermined volume, and a predetermined mechanical strength just below the active circuit forming surface at the center of the semiconductor chip 1. In other words, the above means assures that the hollow portion 9 is uniformly formed in any (manufactured) semiconductor device. Thereafter, the entire structure (outermost periphery) of the interposer substrate 4 below the semiconductor chip 1 is sealed with a resin 6 by a sealing means such as transfer molding to complete the structure.
【００２１】（第２の実施の形態）図３は、本発明の第
２の実施の形態に係る半導体装置の他の製造方法を示す
ための工程順断面図である。まず図３（ａ）の工程に示
す様に、インターポーザ基板４上の周辺部に、熱硬化性
樹脂１０を、予めロの字型に印刷またはディスペンスし
て塗布する。その後、図２に示す様なバンプ３が形成さ
れた半導体チップ１を、図３（ｂ）の工程に示すよう
に、フェイスダウンの状態で、インターポーザ基板４に
フリップチップ実装することにより、中空部９を形成
し、熱硬化性樹脂１０をキュアする（元の状態に戻す）
ことにより熱硬化性樹脂１０を硬化させる。(Second Embodiment) FIGS. 3A to 3E are cross-sectional views in the order of steps showing another method of manufacturing a semiconductor device according to a second embodiment of the present invention. First, as shown in the step of FIG. 3A, a thermosetting resin 10 is applied to the peripheral portion on the interposer substrate 4 in advance by printing or dispensing in a square shape. Thereafter, the semiconductor chip 1 on which the bumps 3 as shown in FIG. 2 are formed is flip-chip mounted on the interposer substrate 4 in a face-down state as shown in the step of FIG. 9 is formed, and the thermosetting resin 10 is cured (return to the original state)
Thereby, the thermosetting resin 10 is cured.
【００２２】上記手段により、中空部９は、所定の形状
と所定の容積と所定の機械的強度を持って確保される。
その後、第１の実施の形態と同様に、トランスファーモ
ールド等の封止手段により、半導体チップ１以下のイン
ターポーザ基板４上の構造物全体（最外周）を、図１に
示す樹脂６と同様の樹脂によって封止して完成する。By the above means, the hollow portion 9 is secured with a predetermined shape, a predetermined volume and a predetermined mechanical strength.
Thereafter, similarly to the first embodiment, the entire structure (outermost periphery) of the interposer substrate 4 below the semiconductor chip 1 is sealed with a resin similar to the resin 6 shown in FIG. To complete.
【００２３】上記の各実施の形態において、 （１）半導体チップ１上のバンプ３の形成は、拡散形成
でもボンダーによるバンプ形成でも構わない。 （２）半導体チップ１上のバンプ３の材質は、Ａｕでも
半田でも構わない。 （３）インターポーザ基板４の材質は、樹脂系でもセラ
ミック系基板でも構わない。In each of the above-described embodiments, (1) The bump 3 on the semiconductor chip 1 may be formed by diffusion or bump formation using a bonder. (2) The material of the bumps 3 on the semiconductor chip 1 may be Au or solder. (3) The material of the interposer substrate 4 may be a resin-based or ceramic-based substrate.
【００２４】[0024]
【発明の効果】以上に説明したとおり、本発明に係る半
導体装置に依れば、フリップチップ実装構造を採用して
いるので、従来のワイヤボンディングに比べて、寄生抵
抗及び寄生リアクタンスが小さくなり、かつ、半導体チ
ップのアクティブ回路面直下が中空構造であるため、従
来のアンダーフィルを充填する場合に比べても、寄生容
量が小さくなる。従って、総合的に損失の小さいパッケ
ージ構造を実現することができ、高周波特性が従来に比
べ向上する。As described above, according to the semiconductor device of the present invention, since the flip-chip mounting structure is employed, the parasitic resistance and the parasitic reactance are reduced as compared with the conventional wire bonding. In addition, since the semiconductor chip has a hollow structure immediately below the active circuit surface, the parasitic capacitance is smaller than in the case where a conventional underfill is filled. Therefore, a package structure with a small loss can be realized overall, and the high-frequency characteristics are improved as compared with the related art.
【００２５】また、構造物全体（最外周）をトランスフ
ァーモールド等により樹脂封止することにより、封止用
フィルムを接着剤で貼り付けていた従来方法に比べて、
接着剤塗布部の界面からの水分侵入を防ぐことが可能と
なり、耐湿性の面から見た信頼性の向上が可能となっ
た。また、フリップチップ実装構造を採用し、インター
ポーザ基板裏面にランドを形成して、これを外部電極と
しているので、セラミック基板上に半導体チップをダイ
ボンドし、金線にてワイヤボンディングした後に接着剤
付きのキャップを貼付けていた従来の中空構造の半導体
装置に比べて、装置の小型化が図れる。In addition, by sealing the entire structure (outermost periphery) with a resin by transfer molding or the like, a sealing film is attached with an adhesive as compared with the conventional method.
This makes it possible to prevent moisture from intruding from the interface of the adhesive application portion, and to improve reliability in terms of moisture resistance. In addition, since a flip-chip mounting structure is used, lands are formed on the back surface of the interposer substrate, and these are used as external electrodes, a semiconductor chip is die-bonded on a ceramic substrate, wire-bonded with a gold wire, and an adhesive The size of the device can be reduced as compared with a conventional semiconductor device having a hollow structure to which a cap is attached.
【００２６】また、高粘度のアンダーフィル材を用いる
ことと、アンダーフィル塗布時にインターポーザ基板を
傾けずに塗布することとによって、どの半導体装置につ
いても、均質な中空部を形成することができる。さら
に、トランスファーモールド等の封止手段を使用するこ
とにより、ムラの無い封止を短時間に実施することが可
能となった。In addition, by using a high-viscosity underfill material and applying the interposer substrate without tilting during underfill application, a uniform hollow portion can be formed in any semiconductor device. Furthermore, by using a sealing means such as transfer molding, it has become possible to perform sealing without unevenness in a short time.
【図１】本発明の第１の実施の形態に係る半導体装置の
構造を示す断面図である。FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態に係る半導体装置の
バンプ電極が形成された半導体チップの平面図である。FIG. 2 is a plan view of a semiconductor chip on which bump electrodes are formed in the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の第２の実施の形態に係る半導体装置の
他の製造方法を示すための工程順断面図である。FIG. 3 is a cross-sectional view in a process order for illustrating another method for manufacturing a semiconductor device according to a second embodiment of the present invention.
１ 半導体チップ ２ 電極部（バンプ電極） ３ バンプ ４ インターポーザ基板 ５ アンダーフィル ６ 樹脂 ７ ＶＩＡホール ８ ランド ９ 中空部 １０ 熱硬化性樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode part (bump electrode) 3 Bump 4 Interposer substrate 5 Underfill 6 Resin 7 VIA hole 8 Land 9 Hollow part 10 Thermosetting resin
Claims (8)
基板上に中空部と該中空部内のバンプとを介してフリッ
プチップ実装された半導体チップを有する高周波用の半
導体装置において、 前記半導体チップの電極部に前記パンプを形成すること
により、該形成されたバンプを前記半導体チップのバン
プ電極とする手段と、 前記インターポーザ基板内の前記バンプ電極の直下にＶ
ＩＡホールを設け、前記バンプ電極を該ＶＩＡホールに
通して前記インターポーザ基板裏面に設置したランドに
接続することにより、該ランドを前記半導体チップの外
部電極とする手段と、 前記インターポーザ基板の水平を保ちながら、高粘度の
アンダーフィル材を前記バンプ周辺を含む前記半導体チ
ップ周辺に塗布することにより、前記中空部を所定の形
状と所定の容積と所定の機械的強度を持たせて確保する
手段と、 前記半導体チップ以下の前記インターポーザ基板上の構
造物全体を、前記インターポーザ基板上に樹脂封止する
手段とにより製造したこと、 を特徴とする半導体装置。1. A high-frequency semiconductor device having an interposer substrate and a semiconductor chip flip-chip mounted on said interposer substrate via a hollow portion and a bump in said hollow portion, wherein said electrode portion of said semiconductor chip has Means for using the formed bumps as bump electrodes of the semiconductor chip by forming a pump; and forming a bump directly below the bump electrodes in the interposer substrate.
Providing an IA hole and connecting the bump electrode to a land provided on the back surface of the interposer substrate by passing the bump electrode through the VIA hole to maintain the interposer substrate horizontal; Meanwhile, by applying a high-viscosity underfill material to the periphery of the semiconductor chip including the periphery of the bump, means for securing the hollow portion with a predetermined shape, a predetermined volume, and a predetermined mechanical strength, Means for manufacturing the entire structure on the interposer substrate below the semiconductor chip by means of resin sealing on the interposer substrate.
基板上に中空部と該中空部内のバンプとを介してフリッ
プチップ実装された半導体チップを有する高周波用の半
導体装置において、 前記半導体チップの電極部に前記パンプを形成すること
により、該形成されたバンプを前記半導体チップのバン
プ電極とする手段と、 前記インターポーザ基板の上部周辺部に熱硬化性樹脂を
印刷又はディスプペンスして塗布する手段と、 前記熱硬化性樹脂が印刷又はディスプペンスして塗布さ
れた前記インターポーザ基板の上面に、前記バンプ電極
が形成された半導体チップを、前記バンプ電極を下にし
てフェイスダウンした後、前記熱硬化性樹脂をキュアす
ることにより、前記中空部を所定の形状と所定の容積と
所定の機械的強度を持たせて確保する手段と、 前記半導体チップ以下の前記インターポーザ基板上の構
造物全体を、前記インターポーザ基板上に樹脂封止する
手段とにより製造したこと、 を特徴とする半導体装置。2. A high-frequency semiconductor device comprising: an interposer substrate; and a semiconductor chip flip-chip mounted on the interposer substrate via a hollow portion and a bump in the hollow portion. Means for forming the bumps to be used as bump electrodes of the semiconductor chip by forming a pump; means for printing or dispensing and applying a thermosetting resin to an upper peripheral portion of the interposer substrate; After the semiconductor chip having the bump electrodes formed thereon is face-down with the bump electrodes facing down, the thermosetting resin is cured on the upper surface of the interposer substrate on which the curable resin is printed or dispensed. By doing so, the hollow portion is secured with a predetermined shape, a predetermined volume, and a predetermined mechanical strength. Stage and, to the entire structure on the interposer substrate of less than the semiconductor chip, produced by means of resin sealing the interposer substrate, wherein a.
モールドを使用したこと、 を特徴とする請求項１又は請求項２記載の半導体装置。3. The semiconductor device according to claim 1, wherein a transfer mold is used as said resin sealing means.
成又はボンダーを使用したこと、 を特徴とする請求項１乃至３のいずれか１項に記載の半
導体装置。4. The semiconductor device according to claim 1, wherein a means for forming the bumps is a diffusion formation or a bonder.
こと、 を特徴とする請求項１乃至４のいずれか１項に記載の半
導体装置。5. The semiconductor device according to claim 1, wherein a material of the bump is gold or a solder material.
又はセラミック系としたこと、 を特徴とする請求項１乃至５のいずれか１項に記載の半
導体装置。6. The semiconductor device according to claim 1, wherein said interposer substrate is made of a resin or ceramic material.
基板上に中空部と該中空部内のバンプとを介してフリッ
プチップ実装された半導体チップを有する高周波用の半
導体装置の製造方法において、 前記半導体チップの電極部に前記パンプを形成すること
により、該形成されたバンプを前記半導体チップのバン
プ電極とするステップと、 前記インターポーザ基板内の前記バンプ電極の直下にＶ
ＩＡホールを設け、前記バンプ電極を該ＶＩＡホールに
通して前記インターポーザ基板裏面に設置したランドに
接続することにより、該ランドを前記半導体チップの外
部電極とするステップと、 前記インターポーザ基板の水平を保ちながら、高粘度の
アンダーフィル材を前記バンプ周辺を含む前記半導体チ
ップ周辺に塗布することにより、前記中空部を所定の形
状と所定の容積と所定の機械的強度を持たせて確保する
ステップと、 前記半導体チップ以下の前記インターポーザ基板上の構
造物全体を、前記インターポーザ基板上に樹脂封止する
ステップとを有すること、 を特徴とする半導体装置の製造方法。7. A method for manufacturing a high-frequency semiconductor device having an interposer substrate and a semiconductor chip flip-chip mounted on the interposer substrate via a hollow portion and a bump in the hollow portion, the method comprising: Forming the bumps on the portion to use the formed bumps as the bump electrodes of the semiconductor chip; and forming V in the interposer substrate immediately below the bump electrodes.
Providing an IA hole and connecting the bump electrode to a land provided on the back surface of the interposer substrate by passing the bump electrode through the VIA hole to maintain the land of the interposer substrate horizontal; Meanwhile, applying a high-viscosity underfill material around the semiconductor chip including the periphery of the bump to secure the hollow portion with a predetermined shape, a predetermined volume, and a predetermined mechanical strength; Sealing the whole structure on the interposer substrate below the semiconductor chip with the resin on the interposer substrate.
基板上に中空部と該中空部内のバンプとを介してフリッ
プチップ実装された半導体チップを有する高周波用の半
導体装置の製造方法において、 前記半導体チップの電極部に前記パンプを形成すること
により、該形成されたバンプを前記半導体チップのバン
プ電極とするステップと、 前記インターポーザ基板の上部周辺部に熱硬化性樹脂を
印刷又はディスプペンスして塗布するステップと、 前記熱硬化性樹脂が印刷又はディスプペンスして塗布さ
れた前記インターポーザ基板の上面に、前記バンプ電極
が形成された半導体チップを、前記バンプ電極を下にし
てフェイスダウンした後、前記熱硬化性樹脂をキュアす
ることにより、前記中空部を所定の形状と所定の容積と
所定の機械的強度を持たせて確保するステップと、 前記半導体チップ以下の前記インターポーザ基板上の構
造物全体を、前記インターポーザ基板上に樹脂封止する
ステップとを有すること、 を特徴とする半導体装置の製造方法。8. A method for manufacturing a high-frequency semiconductor device having an interposer substrate and a semiconductor chip flip-chip mounted on the interposer substrate via a hollow portion and a bump in the hollow portion, the method comprising: Forming the bumps on the portion to make the formed bumps the bump electrodes of the semiconductor chip; and printing or dispensing a thermosetting resin on the upper peripheral portion of the interposer substrate, and applying the thermosetting resin to the interposer substrate. On the upper surface of the interposer substrate on which the thermosetting resin is printed or dispensed, the semiconductor chip having the bump electrodes formed thereon is face-down with the bump electrodes facing down, and then the thermosetting resin is formed. By curing the resin, the hollow portion has a predetermined shape, a predetermined volume, and a predetermined mechanical strength. A method of securing it to have, a method of manufacturing a semiconductor device wherein the entire structure of the semiconductor chip below the interposer substrate, having a step of resin encapsulation in the interposer substrate, and wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33346698A JP3147106B2 (en) | 1998-11-25 | 1998-11-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33346698A JP3147106B2 (en) | 1998-11-25 | 1998-11-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000164635A JP2000164635A (en) | 2000-06-16 |
| JP3147106B2 true JP3147106B2 (en) | 2001-03-19 |
Family
ID=18266401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33346698A Expired - Fee Related JP3147106B2 (en) | 1998-11-25 | 1998-11-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3147106B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005436A1 (en) * | 2001-07-03 | 2003-01-16 | Fujitsu Limited | Coating material of semiconductor chip for controlling magnetic disc drive and method of coating semiconductor chip for controlling magnetic disc drive |
| JP3860000B2 (en) | 2001-09-07 | 2006-12-20 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006081985A (en) | 2004-09-15 | 2006-03-30 | Seiko Epson Corp | Pattern-forming method, electronic instrument making method and substrate making method |
-
1998
- 1998-11-25 JP JP33346698A patent/JP3147106B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000164635A (en) | 2000-06-16 |
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