JPH0797596B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0797596B2 JPH0797596B2 JP63196551A JP19655188A JPH0797596B2 JP H0797596 B2 JPH0797596 B2 JP H0797596B2 JP 63196551 A JP63196551 A JP 63196551A JP 19655188 A JP19655188 A JP 19655188A JP H0797596 B2 JPH0797596 B2 JP H0797596B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- insulating resin
- weight
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置、特に多端子狭ピッチの半導体装置
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a multi-terminal narrow pitch.
従来の技術 半導体素子をフェイスダウンで直接回路基板に面実装す
る技術としてマイクロバンプボンディング実装技術（M.
B.B.実装技術）がある。Conventional technology Micro bump bonding mounting technology (M.
BB mounting technology).
この技術の１例を第３図に示した工程図とともに説明す
る。まず、第３図ａに示した様に導体配線22を有する回
路基板21の半導体素子25を搭載する箇所にUV線硬化性の
絶縁性樹脂23を塗布する。導体配線22はCr−Au,Al,Cu,I
TO等から成り、回路基板21はガラス，セラミック，ガラ
スエポキシ等から成り、絶縁性樹脂23はエポキシ系，シ
リコン系，アクリル系等のUV線硬化性の樹脂を用いる。
次いで第３図ｂに示した様に突起電極24を有する半導体
素子25を、半導体素子25の突起電極24と回路基板21の導
体配線22を向き合わせて搭載し、突起電極24と導体配線
22とを位置合わせする。突起電極24はAu,Al等から成
る。次に第３図ｃに示す様にして半導体素子25を加圧治
具26を用いて回路基板21に加圧する。この際、突起電極
24と導体配線22との間の絶縁性樹脂23は加圧により周囲
に押し出され、突起電極24と導体配線22とは電気的に接
続する。この状態のままUV線を照射し、絶縁性樹脂23を
硬化させる。UV線は回路基板21がガラス等の透明基板の
場合は基板側から照射し、セラミック等の不透明基板の
場合は側面より照射する。絶縁性樹脂23が硬化したら第
３図ｄに示す様に加圧を除去する。加圧を除去しても樹
脂の硬化により半導体素子25は回路基板21に固定されて
おり、導体配線22と突起電極24との電気的接続は保たれ
る。An example of this technique will be described with reference to the process chart shown in FIG. First, as shown in FIG. 3A, a UV ray curable insulating resin 23 is applied to a portion of the circuit board 21 having the conductor wiring 22 on which the semiconductor element 25 is mounted. Conductor wiring 22 is Cr-Au, Al, Cu, I
The circuit board 21 is made of TO or the like, the circuit board 21 is made of glass, ceramics, glass epoxy, or the like, and the insulating resin 23 is made of epoxy-based, silicon-based, acrylic-based, or other UV-curable resin.
Next, as shown in FIG. 3B, the semiconductor element 25 having the protruding electrode 24 is mounted so that the protruding electrode 24 of the semiconductor element 25 and the conductor wiring 22 of the circuit board 21 face each other.
Align 22 with. The protruding electrode 24 is made of Au, Al or the like. Next, as shown in FIG. 3c, the semiconductor element 25 is pressed against the circuit board 21 using the pressing jig 26. At this time, the protruding electrode
The insulating resin 23 between the conductor wire 22 and the conductor wire 22 is pushed out by pressure to electrically connect the protruding electrode 24 and the conductor wire 22. In this state, UV rays are irradiated to cure the insulating resin 23. The UV rays are emitted from the substrate side when the circuit board 21 is a transparent substrate such as glass, and from the side surface when the circuit board 21 is an opaque substrate such as ceramic. When the insulating resin 23 is cured, the pressure is removed as shown in FIG. Even if the pressure is removed, the semiconductor element 25 is fixed to the circuit board 21 by curing the resin, and the electrical connection between the conductor wiring 22 and the protruding electrode 24 is maintained.
発明が解決しようとする課題 かかる構成で半導体素子を回路基板に実装する場合、絶
縁性樹脂の硬化の際に絶縁性樹脂の収縮により、半導体
装置内に内部応力が発生し、半導体装置の信頼性を低下
させる。Problems to be Solved by the Invention When a semiconductor element is mounted on a circuit board with such a configuration, internal stress is generated in the semiconductor device due to contraction of the insulating resin when the insulating resin is cured, and the reliability of the semiconductor device is improved. Lower.
課題を解決するための手段 上記問題を解決するため、第１の発明では絶縁性樹脂の
硬化を２段階にわけ、突起電極を有する半導体素子を導
体配線を有する回路基板に搭載した後、まず第１の加重
で半導体素子を回路基板に第１の加圧を行い突起電極と
導体配線の電気的接続を行わせ、このままの状態で絶縁
性樹脂の内部を硬化させずに外周部の樹脂を硬化させた
後、第１の加重より高い第２の加重で半導体素子を回路
基板に第２の加圧を行い、突起電極を圧縮変形により高
さを縮めさせて半導体素子と回路基板との間隔を狭め、
絶縁性樹脂を圧縮させた状態で内部の未硬化部を硬化さ
せるものとし、また第２の発明では、硬化は一度に行
い、半導体素子を回路基板に搭載し第１の加重で第１の
加圧で突起電極と導体配線を電気的に接続した状態で絶
縁性樹脂を全部硬化させた後、第１の加重より高加重の
第２の加重による加圧を行い、第１の発明と同様に突起
電極を圧縮変形させ、半導体素子と回路基板との間隔を
狭めるものである。Means for Solving the Problems In order to solve the above problems, in the first invention, the curing of the insulating resin is divided into two steps, and after mounting the semiconductor element having the protruding electrodes on the circuit board having the conductor wiring, first, The semiconductor element is first pressed against the circuit board by the weight of 1 to electrically connect the protruding electrode and the conductor wiring, and the resin in the outer peripheral portion is cured without curing the inside of the insulating resin in this state. After that, the semiconductor element is subjected to a second pressure on the circuit board by a second weight higher than the first weight, and the height of the protruding electrode is reduced by compressive deformation, so that the distance between the semiconductor element and the circuit board is reduced. Narrow,
It is assumed that the uncured portion inside is cured while the insulating resin is compressed, and in the second invention, the curing is performed at one time, the semiconductor element is mounted on the circuit board, and the first weight is applied to the first load. After completely curing the insulating resin in a state in which the protruding electrode and the conductor wiring are electrically connected by pressure, pressure is applied by the second weight having a higher weight than the first weight, and the same as in the first invention. The protruding electrode is compressed and deformed to narrow the gap between the semiconductor element and the circuit board.
作用 第１の発明では第１の加圧の際絶縁性樹脂の外周部のみ
を硬化させて内部の樹脂を未硬化のまま第２の加圧によ
りあらかじめ圧縮した状態で絶縁性樹脂を硬化させるこ
とにより、絶縁性樹脂が硬化する際に発生する収縮応力
を緩和できる。また、第２の発明では、樹脂の硬化収縮
により一度発生した内部応力を、第２の加圧により突起
電極を圧縮変形させて半導体素子と絶縁性基板との間隔
を狭めることにより低減できる。Function In the first invention, during the first pressurization, only the outer peripheral portion of the insulating resin is cured, and the insulating resin is cured while being pre-compressed by the second pressurization while the internal resin is uncured. Thereby, the shrinkage stress generated when the insulating resin is cured can be relaxed. Further, in the second invention, the internal stress once generated by the curing shrinkage of the resin can be reduced by compressing and deforming the protruding electrode by the second pressurization to narrow the gap between the semiconductor element and the insulating substrate.
実 施 例 第１の発明の１実施例を第１図とともに説明する。まず
第１図ａに示した様に導体配線２を有する回路基板１の
半導体素子５を搭載する箇所にUV線硬化性の絶縁性樹脂
３を塗布する。導体配線２はCr−Au,Al,Cu,ITO等から成
り、回路基板１はガラス等の透明基板を用い絶縁性樹脂
３はエポキシ系、シリコン系、アクリル系のUV線硬化性
の樹脂を用いる。次いで第１図ｂに示した様に突起電極
４を有する半導体素子５を半導体素子５の突起電極４と
回路基板１の導体配線２を向き合わせて搭載し、突起電
極４と導体配線２を位置合わせをする。突起電極４はA
u,Al,等から成る。次に第１図ｃに示す様にして半導体
素子５を回路基板１に加圧治具６を用いて第１の加重F1
で加圧をする。この際、突起電極４と導体配線２とは電
気的に接触する。この状態のまま半導体素子５の裏面側
からUV線を照射し、絶縁性樹脂３のうち、加圧により半
導体素子５の周囲に押し出された周縁部の絶縁性樹脂７
を硬化させる。この際、絶縁性樹脂３のうち半導体素子
５と回路基板１とに挟まれた部分はUV線が照射されず、
未硬化のまま残される。半導体素子５の裏面側からUV線
を照射することは加圧治具６に石英等を用いて、この石
英越しにUV線を照射させれば簡単に為し得る。Example 1 An example of the first invention will be described with reference to FIG. First, as shown in FIG. 1A, a UV ray curable insulating resin 3 is applied to a portion of the circuit board 1 having the conductor wiring 2 on which the semiconductor element 5 is mounted. The conductor wiring 2 is made of Cr-Au, Al, Cu, ITO or the like, the circuit board 1 is a transparent substrate such as glass, and the insulating resin 3 is an epoxy-based, silicon-based, or acrylic UV-curable resin. . Next, as shown in FIG. 1b, the semiconductor element 5 having the protruding electrode 4 is mounted so that the protruding electrode 4 of the semiconductor element 5 and the conductor wiring 2 of the circuit board 1 face each other, and the protruding electrode 4 and the conductor wiring 2 are positioned. Make a match. The protruding electrode 4 is A
u, Al, etc. Next, as shown in FIG. 1c, the semiconductor element 5 is applied to the circuit board 1 by using the pressing jig 6 and the first load F 1 is applied.
Pressurize with. At this time, the protruding electrode 4 and the conductor wiring 2 are in electrical contact with each other. In this state, UV rays are radiated from the back surface side of the semiconductor element 5, and the insulating resin 7 in the peripheral portion of the insulating resin 3 which is extruded to the periphery of the semiconductor element 5 by pressurization.
Cure. At this time, the portion of the insulating resin 3 sandwiched between the semiconductor element 5 and the circuit board 1 is not irradiated with UV rays,
It remains uncured. Irradiation of UV rays from the back surface side of the semiconductor element 5 can be easily performed by using quartz or the like for the pressing jig 6 and irradiating UV rays through the quartz.
次いで加圧を第１の加重よりも高加重である第２の加重
F2に上げて半導体素子５を回路基板１に更に加圧する。
突起電極４は第１の加重による塑性変形によりすでにそ
の高さを低くしてはいるが、更に高加重である第２の加
重を加えることにより、更に塑性変形を起こし、更にそ
の高さを低くする。今仮りに、加圧以前の突起電極４を
高さをｈ、第１の加重F1による突起電極４の変形量をl1
又、絶縁性樹脂３の硬化の際の収縮率をα％とするな
ら、第２の加重F2はそれにより突起電極４が新たに変形
する変形量l2が なる式を満たす分だけ第１の加重F1より高く設定する。
この際第２の加重による加圧で半導体素子５とその周辺
部の絶縁性樹脂７と回路基板１とに囲まれ存在する未硬
化の内部の絶縁性樹脂８は圧縮されて応力のかかった状
態となっている。次にこのままの状態で第１図ｄに示し
た様に、回路基板１側からUV線を照射し、半導体素子５
と回路基板１との間に残留する絶縁性樹脂３の未硬化の
部分を硬化させる。Then pressurization is applied to a second weight which is higher than the first weight.
It is raised to F 2 and the semiconductor element 5 is further pressed onto the circuit board 1.
Although the height of the bump electrode 4 has already been lowered by the plastic deformation due to the first weighting, by further applying the second weight having a higher weight, the plastic deformation is further caused and the height thereof is further lowered. To do. Now, suppose that the height of the protruding electrode 4 before pressurization is h, and the deformation amount of the protruding electrode 4 due to the first load F 1 is l 1
Further, if the shrinkage rate of the insulating resin 3 at the time of curing is α%, the second weight F 2 has a deformation amount l 2 by which the protruding electrode 4 is newly deformed. The first weight F 1 is set higher than the first weight F 1 by the following equation.
At this time, the uncured internal insulating resin 8 that is surrounded by the semiconductor element 5, the insulating resin 7 around the semiconductor element 5, and the circuit board 1 is compressed and stressed by the second pressure. Has become. Then, in this state, as shown in FIG. 1d, UV rays are radiated from the side of the circuit board 1 so that the semiconductor element 5
The uncured portion of the insulating resin 3 remaining between the wiring board and the circuit board 1 is cured.
従来のプロセスで作成した場合ではこの際、絶縁性樹脂
硬化収縮による応力が発生するが、本発明においては絶
縁性樹脂の硬化による収縮量だけあらかじめ絶縁性樹脂
を圧縮してあるので硬化収縮により調度つり合いが取
れ、内部応力は発生しない。絶縁性樹脂３の未硬化部の
硬化終了後は第１図ｅに示す様に加圧を取り去る。加圧
を取り去っても半導体素子５は絶縁性樹脂３により回路
基板１に固定されており両者の電気的接続は保持され
る。In the case where the insulating resin is produced by the conventional process, stress is generated due to the curing shrinkage of the insulating resin, but in the present invention, the insulating resin is compressed in advance by the amount of shrinkage caused by the curing of the insulating resin. Balanced and no internal stress is generated. After the curing of the uncured portion of the insulating resin 3 is completed, the pressure is removed as shown in FIG. Even if the pressure is removed, the semiconductor element 5 is fixed to the circuit board 1 by the insulating resin 3 and the electrical connection between the two is maintained.
なお本発明では であってF2＞F1で当プロセスを行いさえすれば少くとも
絶縁性樹脂13の硬化収縮の際に発生する内部応力の低減
には有効である。In the present invention, Therefore, if this process is performed with F 2 > F 1 , it is effective at least for reducing the internal stress generated during the curing shrinkage of the insulating resin 13.
続いて第２の発明の実施例について第２図と共に説明す
る。まず第２図ａ〜ｂに示した様にして第１の発明と同
様に突起電極14を有する半導体素子15をガラス等から成
る透明の回路基板11に搭載し、加圧治具16を用いて第１
の荷重F1により半導体素子15を回路基板11に加圧し、つ
いで第２図ｃに示した様にして回路基板11側よりUV線を
照射し絶縁性樹脂13を硬化させ、半導体素子15の突起電
極14と回路基板11の導体配線12とを接触により電気的に
接続する。この際、絶縁性樹脂13の硬化収縮により半導
体装置内に内部応力が発生する。本発明ではこの後第２
図ｄに示した様にして半導体素子15及び回路基板11に第
１の加重F1より高加重の第２の荷重F2を加えることによ
り、第１の発明同様に突起電極14を更に塑性変形させて
その高さを低くし、結果として絶縁性樹脂13の収縮を可
能とし、内部応力を低減させることができる。この際、
第２の加重F2はそれによる突起電極14の新たなる変形量
が第１の発明同様 なる関係式を満たす分だけ第１の加重F1より高く設定し
てやれば一度発生した内部応力を０とすることができ、
また であってもF2＞F1で当プロセスを行えば少くとも内部応
力の低減には効果がある。Next, an embodiment of the second invention will be described with reference to FIG. First, as shown in FIGS. 2A and 2B, the semiconductor element 15 having the protruding electrode 14 is mounted on the transparent circuit board 11 made of glass or the like as in the first invention, and the pressing jig 16 is used. First
The semiconductor element 15 is pressed against the circuit board 11 by the load F 1 of, and then the insulating resin 13 is cured by irradiating UV rays from the side of the circuit board 11 as shown in FIG. The electrode 14 and the conductor wiring 12 of the circuit board 11 are electrically connected by contact. At this time, internal stress is generated in the semiconductor device due to the curing shrinkage of the insulating resin 13. In the present invention, the second
As shown in FIG. 3D, by applying a second load F 2 that is higher than the first load F 1 to the semiconductor element 15 and the circuit board 11, the bump electrode 14 is further plastically deformed as in the first invention. As a result, the height can be reduced, and as a result, the insulating resin 13 can be contracted and internal stress can be reduced. On this occasion,
The second weight F 2 has the same new deformation amount of the bump electrode 14 as that of the first invention. The internal stress once generated can be set to 0 by setting it higher than the first weight F 1 by the amount satisfying the relational expression
Also However, if this process is performed with F 2 > F 1 , it is effective in reducing internal stress at least.
発明の効果 半導体素子と回路基板の接続に用いる絶縁性樹脂の硬化
収縮により半導体装置内に発生する内部応力を低減する
ことができ、半導体装置の信頼性を大幅に向上すること
が可能となる。Effects of the Invention Internal stress generated in the semiconductor device due to curing shrinkage of the insulating resin used for connecting the semiconductor element and the circuit board can be reduced, and the reliability of the semiconductor device can be significantly improved.
第１図は第１の発明の実施例の工程断面図、第２図は第
２の発明の実施例の工程断面図、第３図は従来の方法の
工程断面図である。 1,11……回路基板、2,12……導体配線、 3,13……絶縁性樹脂、4,14……突起電極、 5,15……半導体素子、6,16……加圧治具。FIG. 1 is a process sectional view of an embodiment of the first invention, FIG. 2 is a process sectional view of an embodiment of the second invention, and FIG. 3 is a process sectional view of a conventional method. 1,11 ...... Circuit board, 2,12 ...... Conductor wiring, 3,13 …… Insulating resin, 4,14 …… Projective electrode, 5,15 …… Semiconductor element, 6,16 …… Pressure jig .
Claims (3)
前記半導体素子と前記回路基板との間に絶縁性樹脂を介
して前記半導体素子の電極と前記回路基板の前記導体配
線が向き合う様にして搭載する工程と、前記半導体素子
と前記回路基板に第１の加重で第１の加圧を行い前記半
導体素子の前記電極と前記回路基板の導体配線を電気的
に接触させる工程と、前記第１の加圧を行った状態で前
記絶縁性樹脂のうち前記半導体素子と前記回路基板との
間に挟まれた部分は硬化させずに、前記半導体素子の周
囲に存在する部分のみを硬化させる工程と、前記半導体
素子と前記回路基板を前記第１の加重より高い第２の加
重で第２の加圧を行い前記絶縁性樹脂を圧縮した状態で
前記絶縁性樹脂のうち前記半導体素子と前記回路基板と
の間に挟まれた部分を硬化させ前記半導体素子の前記電
極と前記回路基板の前記導体配線を電気的に接続する工
程を備えてなることを特徴とする半導体装置の製造方
法。1. A semiconductor element on a circuit board having conductor wiring, wherein electrodes of the semiconductor element and the conductor wiring of the circuit board face each other with an insulating resin interposed between the semiconductor element and the circuit board. A step of mounting, a step of applying a first pressure to the semiconductor element and the circuit board with a first weight to electrically contact the electrode of the semiconductor element and a conductor wiring of the circuit board; A step of curing only the portion existing around the semiconductor element without curing the portion sandwiched between the semiconductor element and the circuit board in the insulating resin in the state where the pressure is applied. , The semiconductor element and the circuit board among the insulating resin in a state where the second pressure is applied to the semiconductor element and the circuit board with a second weight higher than the first weight to compress the insulating resin. The part sandwiched between The method of manufacturing a semiconductor device characterized by comprising comprises a step of electrically connecting the conductor wire of the electrode and the circuit board of the semiconductor device to cure the.
前記半導体素子と前記回路基板との間に絶縁性樹脂を介
して前記半導体素子の電極と前記回路基板の前記導体配
線が向き合う様にして搭載する工程と、前記半導体素子
と前記回路基板を第１の加重で第１の加圧を行い、前記
半導体素子の前記電極と前記回路基板の前記導体配線を
電気的に接触させる工程と、前記第１の加圧で加圧した
状態で前記絶縁性樹脂を硬化させ、前記半導体素子と前
記回路基板とを電気的に接続する工程と、前記絶縁性樹
脂の硬化終了後前記半導体素子と前記回路基板を第１の
加重より高い第２の加重で第２の加圧を行い前記半導体
素子と前記回路基板との間隔を狭めさせる工程を備えて
なることを特徴とする半導体装置の製造方法。2. A semiconductor element is arranged on a circuit board having conductor wiring such that the electrodes of the semiconductor element and the conductor wiring of the circuit board face each other with an insulating resin interposed between the semiconductor element and the circuit board. A step of mounting the semiconductor element and the circuit board by applying a first pressure with a first weight to electrically contact the electrode of the semiconductor element and the conductor wiring of the circuit board; A step of curing the insulating resin under pressure with the first pressure to electrically connect the semiconductor element and the circuit board; and, after the insulating resin has been cured, the semiconductor element and the circuit. A method of manufacturing a semiconductor device, comprising a step of applying a second pressure to the substrate with a second weight higher than the first weight to reduce a gap between the semiconductor element and the circuit board.
徴とする特許請求の範囲第１項又は第２項記載の半導体
装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating resin is a UV curable resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63196551A JPH0797596B2 (en) | 1988-08-05 | 1988-08-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63196551A JPH0797596B2 (en) | 1988-08-05 | 1988-08-05 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0244742A JPH0244742A (en) | 1990-02-14 |
| JPH0797596B2 true JPH0797596B2 (en) | 1995-10-18 |
Family
ID=16359618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63196551A Expired - Fee Related JPH0797596B2 (en) | 1988-08-05 | 1988-08-05 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797596B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2547895B2 (en) * | 1990-03-20 | 1996-10-23 | シャープ株式会社 | Semiconductor device mounting method |
| JP2532726B2 (en) * | 1990-07-17 | 1996-09-11 | 松下電器産業株式会社 | Semiconductor device and image sensor using the same |
| US5811317A (en) * | 1995-08-25 | 1998-09-22 | Texas Instruments Incorporated | Process for reflow bonding a semiconductor die to a substrate and the product produced by the product |
-
1988
- 1988-08-05 JP JP63196551A patent/JPH0797596B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0244742A (en) | 1990-02-14 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |