JP2797669B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2797669B2 JP2797669B2 JP2189045A JP18904590A JP2797669B2 JP 2797669 B2 JP2797669 B2 JP 2797669B2 JP 2189045 A JP2189045 A JP 2189045A JP 18904590 A JP18904590 A JP 18904590A JP 2797669 B2 JP2797669 B2 JP 2797669B2
- Authority
- JP
- Japan
- Prior art keywords
- lsi chip
- resin film
- conductor wiring
- reinforcing plate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、IC,LSIチップ等の実装方法に関するもので
ある。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an IC, an LSI chip, and the like.
従来の技術 従来の技術を、第４図及び第５図を用いて説明する。
まず初めに第４図（ａ）に示す様に、ポリイミド，ポリ
エステル等よりなる樹脂フィルム21の導体配線22を有す
る面にディスペンサー等により絶縁性樹脂25を塗布す
る。導体配線22は、Cu,Au等であり、絶縁性樹脂25は、
紫外線硬化型あるいは熱硬化型のエポキシあるいはアク
リル型である。次に、第４図（ｂ）に示す様に、LSIチ
ップ26のバンプ27と導体配線22を位置合わせし、LSIチ
ップ26を絶縁性樹脂フィルム21に設置し、加圧ツール28
でLSIチップ26を加圧する。この時、導体配線22とバン
プ27の絶縁性樹脂25は押圧され、バンプ27と導体配線22
は、電気的に接触する。次にLSIチップ26を加圧した状
態で、絶縁性樹脂25を硬化する。絶縁性樹脂25の硬化の
方法は、絶縁性樹脂25が紫外線硬化の場合は、樹脂フィ
ルムの裏面あるいはLSIチップ26の側面より、紫外線29
を照射し硬化する。また、熱硬化の場合は、加圧ツール
28に加熱機構を設け、LSIチップ26を介して硬化する。
次に、第４図（ｃ）に示す様に、加圧を解除することに
より、LSIチップ26が、樹脂フィルム21に固着されると
ともに、導体配線22とLSIチップ26が電気的に接続され
るものである。2. Description of the Related Art A conventional technique will be described with reference to FIGS.
First, as shown in FIG. 4 (a), an insulating resin 25 is applied to the surface of the resin film 21 made of polyimide, polyester or the like having the conductor wiring 22 by a dispenser or the like. The conductor wiring 22 is made of Cu, Au, or the like, and the insulating resin 25 is
An ultraviolet or thermosetting epoxy or acrylic type. Next, as shown in FIG. 4 (b), the bumps 27 of the LSI chip 26 are aligned with the conductor wiring 22, the LSI chip 26 is set on the insulating resin film 21, and the pressing tool 28
Pressurizes the LSI chip 26. At this time, the insulating resin 25 of the conductor wiring 22 and the bump 27 is pressed, and the bump 27 and the conductor wiring 22 are pressed.
Make electrical contact. Next, the insulating resin 25 is cured while the LSI chip 26 is pressed. The method of curing the insulating resin 25 is as follows: when the insulating resin 25 is cured by ultraviolet light, the ultraviolet light 29 is applied from the back surface of the resin film or the side surface of the LSI chip 26.
To cure. In case of thermosetting, pressurizing tool
28 is provided with a heating mechanism, and is cured via the LSI chip 26.
Next, as shown in FIG. 4 (c), by releasing the pressure, the LSI chip 26 is fixed to the resin film 21, and the conductor wiring 22 and the LSI chip 26 are electrically connected. Things.
発明が解決しようとする課題 前記従来の技術では、絶縁性樹脂を用いてLSIチップ
を配線基板に接続する方法であるため、非常に微細な電
極ピッチのLSIの接続に有利な方法であるか、配線基板
が樹脂フィルムの場合、次に示す様な問題点を有してい
ることが判明した。The problem to be solved by the invention is that in the conventional technique, a method of connecting an LSI chip to a wiring board using an insulating resin is advantageous for connecting an LSI having a very fine electrode pitch, It has been found that when the wiring substrate is a resin film, it has the following problems.
（１）樹脂フィルムは、フレキシビリティーがある為、
容易に変形し、第５図に示す様に、樹脂フィルムは、LS
Iチップに対して容易に剥離し、導体配線とLSIチップの
バンプは電気的に接続不良となり、信頼性の低いもので
ある。(1) Because the resin film has flexibility,
It is easily deformed, and as shown in FIG.
It easily peels off from the I chip, and the conductor wiring and the bump of the LSI chip become electrically poorly connected, resulting in low reliability.
（２）樹脂フィルムは吸温性がある為、空気中の水分
は、樹脂フィルムを介して、容易にLSIチップを固着し
ている絶縁性樹脂に到達し、絶縁性樹脂が膨張すること
により、接続不良が発生する。(2) Since the resin film has a heat-absorbing property, moisture in the air easily reaches the insulating resin to which the LSI chip is fixed via the resin film, and the insulating resin expands. Connection failure occurs.
（３）LSIチップのバンプと導体配線の電気的な接触はL
SIチップを樹脂フィルム間にある絶縁性樹脂の硬化収縮
力により保持されているが、樹脂フィルムは弾性力が非
常に小さい為、絶縁性樹脂の硬化収縮力により容易に変
形し、LSIチップと樹脂フィルム間の収縮力が小さく、
信頼性の低いものである。(3) The electrical contact between the bumps on the LSI chip and the conductor wiring is L
The SI chip is held by the curing shrinkage of the insulating resin between the resin films, but since the resin film has a very small elastic force, it is easily deformed by the curing shrinkage of the insulating resin, and the LSI chip and the resin The shrinkage force between the films is small,
It is of low reliability.
したがって、本発明はLSIチップに対して剥離のない
半導体実装体を提供することを目的とする。また本発明
は、耐湿性にすぐれ、信頼性の高い半導体実装体を得る
ことを目的とする。Therefore, an object of the present invention is to provide a semiconductor package that does not peel off from an LSI chip. Another object of the present invention is to obtain a highly reliable semiconductor package having excellent moisture resistance.
課題を解決するための手段 本発明は、一主面に導体配線を有する長尺状の絶縁性
フィルムをリール供給し、前記絶縁性フィルムの裏面側
に補強板を接着する工程と、絶縁性フィルムの導体配線
を有した面に絶縁性樹脂を塗布する工程と、前記絶縁性
フィルムの導体配線と前記半導体素子の突起電極を位置
合わせし、前記半導体素子を前記絶縁性フィルムに加圧
しその状態で前記絶縁性樹脂を硬化させ前記突起電極と
前記導体配線を電気的に接続する工程と、前記半導体素
子が接続された長尺状の絶縁性フィルムを順次リールで
巻き取る工程とを有する半導体装置の製造方法を提供す
る。また一主面に導体配線を有する長尺状の絶縁性フィ
ルムをリール供給し、前記絶縁性フィルムの裏面側に補
強板を接着する工程において、前記補強板は樹脂フィル
ムに接続する半導体素子と同等以上の大きさの補強板を
接着する工程である半導体装置の製造方法を提供する。Means for Solving the Problems The present invention provides a step of supplying a long insulating film having conductor wiring on one main surface to a reel, and bonding a reinforcing plate to the back side of the insulating film; Applying an insulating resin to the surface having the conductive wiring, aligning the conductive wiring of the insulating film with the protruding electrode of the semiconductor element, and pressing the semiconductor element against the insulating film in that state. A step of curing the insulating resin to electrically connect the protruding electrode and the conductor wiring, and a step of sequentially winding a long insulating film to which the semiconductor element is connected by a reel. A manufacturing method is provided. In the step of supplying a reel of a long insulating film having conductor wiring on one main surface and bonding a reinforcing plate to the back surface side of the insulating film, the reinforcing plate is equivalent to a semiconductor element connected to a resin film. A method of manufacturing a semiconductor device, which is a step of bonding a reinforcing plate having the above size, is provided.
作用 上記手段によれば、LSIチップ等の半導体素子が固着
された領域における樹脂フィルムは、補強板で支持され
ている為、曲り等の変形が生じず、LSIチップに対する
剥離の力は作用しない、また、耐湿性も向上し信頼性の
高いものとなる。すなわち、本発明では、 （１）樹脂フィルムとしてTAB用のテープを用いてLSIチ
ップの接続後にリールに巻き取っても、LSIチップの領
域には樹脂フィルムの曲りが生じず、LSIチップに剥離
の力は作用せず、信頼性の高い接続が得られる。According to the above means, the resin film in the region where the semiconductor element such as the LSI chip is fixed is supported by the reinforcing plate, so that no deformation such as bending occurs, and no peeling force acts on the LSI chip. In addition, the moisture resistance is improved and the reliability is high. That is, according to the present invention, (1) even if a tape for TAB is used as a resin film and then wound on a reel after the connection of the LSI chip, the resin film does not bend in the area of the LSI chip, and the LSI chip does not peel off. No force acts and a reliable connection is obtained.
（２）補強板により、絶縁性樹脂への水分の浸入を低減
できる為、耐湿性が向上する。(2) Moisture resistance is improved because penetration of moisture into the insulating resin can be reduced by the reinforcing plate.
（３）絶縁性樹脂の硬化収縮による、樹脂フィルムの変
形が生じない為、LSIチップと樹脂フィルムの間には、
十分な収縮力が作用し、LSIチップのバンプと導体配線
の接触の保持が非常に信頼性の高いものとなる。(3) Since the resin film does not deform due to the shrinkage of the insulating resin upon curing, there is a gap between the LSI chip and the resin film.
Sufficient contraction force acts, and the contact between the bumps of the LSI chip and the conductor wiring is highly reliable.
（４）TAB用のテープを用い、リールに巻き取ることが
できる為、生産性に富み非常にコストの安いものとな
る。(4) Since the tape for TAB can be wound on a reel, the productivity is high and the cost is very low.
実施例 本発明の一実施例を第１図，第２図とともに説明す
る。まず、第１図（ａ）に示す様に、ポリイシド，ポリ
エステルフィルム等よりなる樹脂フィルム１の後にLSI
チップを固着する面と反対の面に、補強板４を接着剤３
を用いて固着する。補強板４は、ガラス,Al,Cu,セラミ
ック等よりなり、その厚みは、0.2〜1.0mm程度であり寸
法は、LSIチップ１を同等以上の寸法を有する。接着剤
３は、エポキシ，アクリル等である。導体配線２は、Cu
にNi,Auめっきを施したものを用いる。樹脂フィルム１
は、長尺状、短尺状どちらでもよく、長尺の場合は、巻
き取られたリールから供給されるTAB方式のテーブを用
いることができる。Embodiment An embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 1 (a), after a resin film 1 composed of a polyisid, polyester film, etc., an LSI is formed.
On the surface opposite to the surface to which the chip is fixed, a reinforcing plate 4 is
It is fixed using. The reinforcing plate 4 is made of glass, Al, Cu, ceramic, or the like, has a thickness of about 0.2 to 1.0 mm, and has dimensions equal to or larger than those of the LSI chip 1. The adhesive 3 is epoxy, acrylic, or the like. The conductor wiring 2 is made of Cu
Used is Ni, Au plated. Resin film 1
May be long or short, and in the case of long, a TAB type tape supplied from a wound reel can be used.
次に第１図（ｂ）に示す様に、樹脂フィルム１の導体
配線２を有する面に、絶縁性樹脂５をディスペンサー等
により塗布する。絶縁性樹脂５はアクリル，エポキシ，
シリコーン等の紫外線硬化型あるいは、熱硬化型の樹脂
である。本実施例では、絶縁性樹脂５は、樹脂フィルム
１側に塗布したが、後に搭載するLSIチップ側に塗布し
てもよい。Next, as shown in FIG. 1 (b), an insulating resin 5 is applied to the surface of the resin film 1 having the conductor wiring 2 by a dispenser or the like. The insulating resin 5 is made of acrylic, epoxy,
It is an ultraviolet curable or thermosetting resin such as silicone. In the present embodiment, the insulating resin 5 is applied to the resin film 1 side, but may be applied to an LSI chip to be mounted later.
次に第１図（ｃ）に示す様に、LSIチップ６のバンプ
７を導体配線２を位置合わせし、LSIチップ６を樹脂フ
ィルム１に設置し、その後、加圧ツール８にてLSIチッ
プ６を加圧する。この時、バンプ７と導体配線２の間の
絶縁性樹脂５は周囲に押し出され、バンプ７と導体配線
２は電気的に接触する。バンプ７は、Au,Cu,In等よりな
り、その厚みは２〜10μm,サイズは、10〜50μｍφ程度
である。Next, as shown in FIG. 1 (c), the bumps 7 of the LSI chip 6 are aligned with the conductor wiring 2, and the LSI chip 6 is placed on the resin film 1. Press. At this time, the insulating resin 5 between the bump 7 and the conductor wiring 2 is pushed out to the periphery, and the bump 7 and the conductor wiring 2 are electrically contacted. The bump 7 is made of Au, Cu, In, or the like, has a thickness of 2 to 10 μm, and a size of about 10 to 50 μmφ.
次に、LSIチップ６を加圧した状態で、絶縁性樹脂５
を硬化する。硬化の方法は、絶縁性樹脂５が紫外線硬化
型の場合は、樹脂フィルム１の補強板４側、または、補
強板４が不透明な場合は、LSIチップ６の側面より、紫
外線９を照射し硬化させる。また、絶縁性樹脂５が熱硬
化型の場合は、加圧ツールに加熱機構を設け、LSIチッ
プ６を介して加熱硬化する。いづれの場合でも、硬化時
間は、数秒〜数十秒程度である。この時、絶縁性樹脂５
は硬化収縮するが、樹脂フィルム１には、補強板４が固
着されている為、樹脂フィルム１には、硬化収縮よる変
形が生じず、LSIチップ６と樹脂フィルム１の間には十
分な収縮力が作用し、後に加圧ツール８を取り除いて
も、バンプ７と導体配線２の接触は保持される。Next, with the LSI chip 6 pressed, the insulating resin 5
To cure. When the insulating resin 5 is an ultraviolet curing type, the curing is performed by irradiating ultraviolet rays 9 from the reinforcing plate 4 side of the resin film 1 or from the side surface of the LSI chip 6 when the reinforcing plate 4 is opaque. Let it. When the insulating resin 5 is of a thermosetting type, a heating mechanism is provided in the pressing tool, and the heating is performed via the LSI chip 6. In any case, the curing time is about several seconds to several tens of seconds. At this time, the insulating resin 5
Is cured and contracted, but since the reinforcing plate 4 is fixed to the resin film 1, the resin film 1 is not deformed by curing contraction, and there is sufficient contraction between the LSI chip 6 and the resin film 1. Even if a force acts and the pressing tool 8 is later removed, the contact between the bump 7 and the conductor wiring 2 is maintained.
次に、第１図（ｄ）に示す様に、加圧ツール８を解除
し、LSIチップ６を樹脂フィルム１に固着するととも
に、バンプ７と導体配線２を電気的に接続する。Next, as shown in FIG. 1 (d), the pressing tool 8 is released, the LSI chip 6 is fixed to the resin film 1, and the bump 7 and the conductor wiring 2 are electrically connected.
また、樹脂フィルム１としてTAB用のテープを用いた
場合のLSIチップ６接続後外観図を第２図に示す。樹脂
フィルム１には、搬送のためのガイド孔10が設けられ、
LSIチップ６の樹脂フィルム１への接続は連続的に行わ
れる。また、接続が終了した樹脂フィルム１は、第３図
に示す様なリール11に巻き取られる。この時、樹脂フィ
ルム１は容易に曲がるか、LSIチップ６が固着された裏
面には、補強板４が固着されている為、LSIチップ６の
領域の樹脂フィルム１には曲りが生じない為、LSIチッ
プ６からの樹脂フィルム１の剥離は生じない。このよう
に、樹脂フィルムと半導体素子を直接樹脂で固着・接続
した半導体実装体の大量製造において、本発明の方法に
よる効果は極めて大である。FIG. 2 shows an external view after connecting the LSI chip 6 when a TAB tape is used as the resin film 1. The resin film 1 is provided with a guide hole 10 for conveyance,
The connection of the LSI chip 6 to the resin film 1 is performed continuously. The resin film 1 after the connection is wound up on a reel 11 as shown in FIG. At this time, since the resin film 1 is easily bent or the reinforcing plate 4 is fixed to the back surface to which the LSI chip 6 is fixed, the resin film 1 in the area of the LSI chip 6 does not bend. No peeling of the resin film 1 from the LSI chip 6 occurs. As described above, the effect of the method of the present invention is extremely large in mass production of a semiconductor package in which a resin film and a semiconductor element are directly fixed and connected with a resin.
発明の効果 以上のように本発明では、樹脂フィルムの裏面に補強
板を固着している為、次に示す効果がある。Effects of the Invention As described above, in the present invention, since the reinforcing plate is fixed to the back surface of the resin film, the following effects are obtained.
（１）樹脂フィルムにTAB用のテープを用いLSIチップの
接続後にリールに巻き取っても、LSIチップの領域には
樹脂フィルムの曲りが生じず、LSIチップに剥離の力は
作用せず、信頼性の高い接続が得られる。(1) Even if a tape for TAB is used for the resin film and the chip is wound on a reel after the connection of the LSI chip, the resin film does not bend in the area of the LSI chip and the peeling force does not act on the LSI chip. A highly reliable connection is obtained.
（２）補強板により、絶縁性樹脂への水分の浸入を低減
できる為、耐熱性が向上する。(2) Since the penetration of moisture into the insulating resin can be reduced by the reinforcing plate, heat resistance is improved.
（３）絶縁性樹脂の硬化収縮による、樹脂フィルムの変
形が生じない為、LSIチップと樹脂フィルム間には、十
分な収縮力が作用し、LSIチップのバンプと導体配線の
接触の保持が非常に信頼性の高いものとなる。(3) Since the resin film is not deformed due to the curing shrinkage of the insulating resin, a sufficient shrinkage force acts between the LSI chip and the resin film, and the contact between the bumps of the LSI chip and the conductor wiring is extremely maintained. Will be more reliable.
（４）TAB用のテープを用い、リールに巻き取ることが
できる為、生産性に富み非常にコストの安いものとな
る。(4) Since the tape for TAB can be wound on a reel, the productivity is high and the cost is very low.
第１図は本発明の一実施例の実装工程別断面図、第２図
はTAB用テープへのLSIチップの接続状態を示す図、第３
図はTAB用テープのリールを示す図、第４図は従来の実
装工程断面図、第５図は従来の実装体の断面図である。 １……樹脂フィルム、２……導体配線、３……接着剤、
４……補強板、５……絶縁性樹脂、６……LSIチップ、
７……バンプ、８……加圧ツール、９……紫外線、10…
…ガイド孔、11……リール。FIG. 1 is a sectional view showing a mounting process according to an embodiment of the present invention, FIG. 2 is a diagram showing a connection state of an LSI chip to a TAB tape, FIG.
FIG. 4 shows a TAB tape reel, FIG. 4 is a cross-sectional view of a conventional mounting process, and FIG. 5 is a cross-sectional view of a conventional mounted body. 1 ... resin film, 2 ... conductor wiring, 3 ... adhesive,
4 Reinforcement plate 5 Insulating resin 6 LSI chip
7 ... Bump, 8 ... Pressure tool, 9 ... UV, 10 ...
... guide holes, 11 ... reels.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311
Claims (2)
フィルムをリール供給し、前記絶縁性フィルムの裏面側
に補強板を接着する工程と、絶縁性フィルムの導体配線
を有した面に絶縁性樹脂を塗布する工程と、前記絶縁性
フィルムの導体配線と前記半導体素子の突起電極を位置
合わせし、前記半導体素子を前記絶縁性フィルムに加圧
しその状態で前記絶縁性樹脂を硬化させ前記突起電極と
前記導体配線を電気的に接続する工程と、前記半導体素
子が接続された長尺状の絶縁性フィルムを順次リールで
巻き取る工程とを有することを特徴とする半導体装置の
製造方法。A step of supplying a reel of a long insulating film having conductor wiring on one main surface thereof, and bonding a reinforcing plate to the back side of the insulating film; and providing a conductor wiring of the insulating film. Applying an insulating resin to the surface, aligning the conductor wiring of the insulating film with the protruding electrode of the semiconductor element, pressing the semiconductor element against the insulating film, and curing the insulating resin in that state Manufacturing a semiconductor device, comprising: a step of electrically connecting the protruding electrode to the conductor wiring; and a step of sequentially winding a long insulating film to which the semiconductor element is connected by a reel. Method.
フィルムをリール供給し、前記絶縁性フィルムの裏面側
に補強板を接着する工程において、前記補強板は接続す
る半導体素子と同等以上の大きさの補強板を接着する工
程であることを特徴とする請求項１記載の半導体装置の
製造方法。2. A step of supplying a long insulating film having conductor wiring on one main surface to a reel and bonding a reinforcing plate to a back surface of the insulating film, wherein the reinforcing plate is connected to a semiconductor element to be connected. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of bonding a reinforcing plate having a size equal to or greater than the size of the reinforcing plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189045A JP2797669B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189045A JP2797669B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0474447A JPH0474447A (en) | 1992-03-09 |
| JP2797669B2 true JP2797669B2 (en) | 1998-09-17 |
Family
ID=16234369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2189045A Expired - Fee Related JP2797669B2 (en) | 1990-07-16 | 1990-07-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2797669B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5499970A (en) * | 1978-01-24 | 1979-08-07 | Suwa Seikosha Kk | Electronic circuit |
-
1990
- 1990-07-16 JP JP2189045A patent/JP2797669B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0474447A (en) | 1992-03-09 |
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