JPS63293840A - Packaging body - Google Patents
Packaging bodyInfo
- Publication number
- JPS63293840A JPS63293840A JP62129324A JP12932487A JPS63293840A JP S63293840 A JPS63293840 A JP S63293840A JP 62129324 A JP62129324 A JP 62129324A JP 12932487 A JP12932487 A JP 12932487A JP S63293840 A JPS63293840 A JP S63293840A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor element
- circuit board
- electrode
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title description 2
- 239000011347 resin Substances 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 abstract description 39
- 238000000034 method Methods 0.000 abstract description 11
- 238000003825 pressing Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008451 emotion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の実装体に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor device package.
従来の技術
半導体装置を高密度に実装する方法として、フェイスダ
ウン方式が実用化されている。この方法は、半導体素子
の電極上に半田バンプを形成し、この半田バンプと相対
する位置に半田処置された電極配線を有する回路基板と
を重ね合わせ、半導体素子上の半田バンクと回路基板の
電極配線とを半田づけ固定するものである。2. Description of the Related Art A face-down method has been put into practical use as a method for packaging semiconductor devices with high density. In this method, solder bumps are formed on the electrodes of a semiconductor element, and a circuit board having soldered electrode wiring is placed in a position opposite to the solder bumps. The wiring is fixed by soldering.
この方法においては、接合部が固定されているため、熱
や機械的ストレスが半導体素子もしくは回路基板に作用
した際、前記接合部が破断する不良が発生するばかりか
、電極間の接合部を半田づけ固定するために、半導体素
子の電極もしくは回路基板の電極配線のピッチを小さく
できず、今後、益々、多ピンで、微小ピッチ化していく
実装方法にとってはひとつの課題であった。In this method, the joints are fixed, so when heat or mechanical stress acts on the semiconductor element or circuit board, not only does the joint break, but also the joints between the electrodes are soldered. In order to secure the pins in place, it is not possible to reduce the pitch of the electrodes of the semiconductor element or the electrode wiring of the circuit board, which has been a problem for mounting methods that will increasingly require more pins and smaller pitches in the future.
これを解決する実装体として、第３図以降に示す方法が
提案されている。As an implementation to solve this problem, the method shown in FIG. 3 and subsequent figures has been proposed.
半導体素子１の周縁に６〜２０μｍのＡｕ突起を持つ電
極１ｏが形成される（第３図）。前記半導体素子１の電
極１ｏと相対する位置に配線電極４ｆ、有する回路基板
３上の前記配線電極４上に光硬化性絶縁樹脂８を塗布し
、前記半導体素子１の電極１０と回路基板３の配線電極
４とを位置合せし、加圧治具７で加圧しながら、紫外光
９１照射し、前記樹脂８を硬化せしめ、硬化が終れば、
加王治具７ｉ取去る。この様にして、実装体が完成する
わけであるが、この方法は樹脂の硬化収縮時の圧縮応力
によって、半導体素子の電極と回路基板の配線電極とを
圧接するメカニズムによって、電気的接合と、半導体素
子と回路基板とを機械的に保持するものである（第４図
）。An electrode 1o having Au protrusions of 6 to 20 μm is formed on the periphery of the semiconductor element 1 (FIG. 3). A photocurable insulating resin 8 is applied onto the wiring electrode 4 on the circuit board 3 having a wiring electrode 4f at a position facing the electrode 1o of the semiconductor element 1, and the wiring electrode 4f of the semiconductor element 1 and the circuit board 3 are The resin 8 is aligned with the wiring electrode 4 and is irradiated with ultraviolet light 91 while being pressurized with the pressure jig 7 to harden the resin 8. Once the hardening is completed,
Remove Kao jig 7i. In this way, the package is completed, and this method uses a mechanism in which the electrodes of the semiconductor element and the wiring electrodes of the circuit board are brought into pressure contact with each other by compressive stress when the resin hardens and contracts. It mechanically holds the semiconductor element and the circuit board (Fig. 4).
光硬化性絶縁樹脂はアクリル系、エポキシ系を用い、加
圧力は電極当り６〜１００９８度で、紫外光は１００
ｍ Ｗ ／Ｃｒ７Ｌで６〜２０秒程度を照射するもので
ある。The photocurable insulating resin is acrylic or epoxy, the pressure is 6 to 10098 degrees per electrode, and the ultraviolet light is 100 degrees.
Irradiation is performed at m W /Cr7L for about 6 to 20 seconds.
また、回路基板がガラスの如く透明であれば、回路基板
側より紫外光を照射するが、セラミックや樹脂の如く不
透明であれば、半導体素子側より、樹脂の露出領域のみ
を照射、硬化させ、影になって照射されなかった領域は
、常温で経時的に硬化させるものである。Also, if the circuit board is transparent like glass, ultraviolet light is irradiated from the circuit board side, but if it is opaque like ceramic or resin, only the exposed area of the resin is irradiated from the semiconductor element side and cured. The areas that are in the shadow and are not irradiated are to be cured over time at room temperature.
この様な方式においては、電極間に絶縁樹脂を介在させ
ているため、数μｍピッチの電極の接続が実施でき、か
つ電極の接続部が機械的に固定されず、樹ノ盾の応力を
利用し、電極同志全圧接した構成であるために、半導体
素子や配線基板の熱膨張等によるストレスに対して強い
ものである。In this type of method, since an insulating resin is interposed between the electrodes, it is possible to connect electrodes with a pitch of several micrometers, and the connecting part of the electrodes is not mechanically fixed, so the stress of the tree shield can be used. However, since the electrodes are in full pressure contact with each other, they are resistant to stress caused by thermal expansion of semiconductor elements and wiring boards.
発明が解決しようとする問題点 ところが、この方法においては次の様な課題があった。The problem that the invention seeks to solve However, this method had the following problems.
この方法は半導体素子と回路基板との間に介在させた樹
脂を硬化させる時に、お互いを加圧して、互いの電極同
志の表面を押しつけ、平面度を出す必要がある。この時
の加圧によって、第５図の如く半導体素子１は凹状にそ
ってしまう。In this method, when curing the resin interposed between the semiconductor element and the circuit board, it is necessary to apply pressure to each other to press the surfaces of the electrodes against each other to achieve flatness. Due to the pressure applied at this time, the semiconductor element 1 warps into a concave shape as shown in FIG.
これは半導体素子もしくは配線基板側に設けた電極１ｏ
を支点として、電極１０の存在しない中央部に背圧力が
集中するためである。第６図の如く、加圧時に半導体素
子もしくは配線基板がそってしまうと、電極同志の接合
が不完全となり電気的接合不良を発生させるばかりか、
信頼性のレベルも低下するものである。This is the electrode 1o provided on the semiconductor element or wiring board side.
This is because the back pressure is concentrated in the central part where the electrode 10 is not present, with the fulcrum being the fulcrum. As shown in Fig. 6, if the semiconductor element or wiring board warps when pressurized, not only will the bonding between the electrodes be incomplete, resulting in poor electrical bonding.
The level of reliability is also reduced.
本発明は、加圧時に半導体素子もしくは回路基板のそり
を積極的に防止し、信頼性の高い接合を得んとするもの
である。The present invention aims to actively prevent warping of a semiconductor element or a circuit board during pressurization and to obtain highly reliable bonding.
問題点を解決するための手段
本発明は、半導体素子もしくは回路基板の中央領域にも
電極を形成した構成とするものである。Means for Solving the Problems The present invention has a structure in which electrodes are also formed in the central region of the semiconductor element or circuit board.
作 用
このような本発明によれば、樹脂の硬化時に加わる圧力
によって、半導体素子もしくは回路基板の中央に応力が
集中しても、中央領域に設けた電極により、半導体素子
もしくは回路基板の四部状の変形を防止できる作用があ
る。According to the present invention, even if stress is concentrated at the center of the semiconductor element or circuit board due to the pressure applied during curing of the resin, the four parts of the semiconductor element or circuit board are fixed by the electrodes provided in the central region. It has the effect of preventing deformation.
実施例
本発明に用いる半導体素子の電極の配置を第１図に示す
。半導体素子１０表面には、その周縁に形成した電極２
０と周縁で囲まれた表面の中央部領域に電極２１が形成
されている。EXAMPLE FIG. 1 shows the arrangement of electrodes of a semiconductor element used in the present invention. On the surface of the semiconductor element 10, there are electrodes 2 formed around its periphery.
An electrode 21 is formed in the central region of the surface surrounded by the periphery.
先ず、回路基板３の配線電極４上もしくは半導体素子１
の表面に光硬化性絶縁樹脂２３を塗布し、配線電極４と
半導体素子１の電極２０，２１とを位置合せし、半導体
素子を加圧しながら、紫外線を照射し、前記光硬化性絶
縁樹脂を硬化させる。First, on the wiring electrode 4 of the circuit board 3 or on the semiconductor element 1
A photocurable insulating resin 23 is applied to the surface of the wiring electrode 4 and the electrodes 20 and 21 of the semiconductor element 1 are aligned, and ultraviolet rays are irradiated while applying pressure to the semiconductor element to cure the photocurable insulating resin. Let it harden.
硬化が終れば、加圧を取り去９第２図の構成を得る事が
できる。すなわち、半導体素子１の電極２０゜２１と回
路基板３の配線電極４とが前記光硬化性絶縁樹脂の硬化
時の応力によって圧接され、電気的接合を得るものであ
る。第２図に実装体の断面図を示す。Once curing is complete, the pressure is removed and the structure shown in FIG. 2 can be obtained. That is, the electrodes 20.degree. 21 of the semiconductor element 1 and the wiring electrodes 4 of the circuit board 3 are brought into pressure contact with each other by the stress generated when the photocurable insulating resin is cured, thereby obtaining an electrical connection. FIG. 2 shows a cross-sectional view of the mounting body.
半導体素子１に形成した電極２０．２１は高さ２〜２ｏ
μｍでＡｕ、Ｃｕ 等の電気的良導体で構成され、中央
部領域に形成する電極２１は、複数個を等間隔に配列し
ても良いが、寸法の大きい電極を半導体素子の中央部に
一個形成しても良い。The electrodes 20.21 formed on the semiconductor element 1 have a height of 2 to 2o.
The electrodes 21, which are made of a good electrical conductor such as Au or Cu in μm, and formed in the central region may be arranged in a plurality at equal intervals, but one large-sized electrode is formed in the central region of the semiconductor element. You may do so.
また、中央部領域に形成した電極２１は、実際に回路基
板の配線電極と電気的に接続され、回路を形成しても良
いし、いわゆるダミー電極であっても良い。実施例にお
いては、半導体素子側に突起状の電極を形成した例をの
べたが、逆に回路基板の配線電極上に突起状の電極を形
成する事もできる。Further, the electrode 21 formed in the central region may be actually electrically connected to a wiring electrode of a circuit board to form a circuit, or may be a so-called dummy electrode. In the embodiment, an example is described in which a protruding electrode is formed on the semiconductor element side, but conversely, a protruding electrode can also be formed on a wiring electrode of a circuit board.
この様な構成であれば、半導体素子の中央部領域に設け
た電極２１が加圧、硬化時に回路基板３の表面に接する
ため、半導体素子１や回路基板３がたわみ、そりあがる
のを阻止する事ができるものである。With this configuration, the electrode 21 provided in the central region of the semiconductor element comes into contact with the surface of the circuit board 3 during pressurization and curing, thereby preventing the semiconductor element 1 and the circuit board 3 from bending and warping. It is something that can be done.
発明の効果
以上のように本発明によれば次のような効果を得ること
ができる。Effects of the Invention As described above, according to the present invention, the following effects can be obtained.
■ 本発明の構成であれば加圧、硬化時に半導体素子や
回路基板が凹状に変形しようとしても半導体素子もしく
は回路基板の中央領域にも電極が形成されているので、
加圧、硬化時の変形が生じず、高い接続率と高信頼性を
得る事ができる。■ With the structure of the present invention, even if the semiconductor element or circuit board tries to deform into a concave shape during pressurization and curing, the electrode is also formed in the central area of the semiconductor element or circuit board.
No deformation occurs during pressurization and curing, providing high connection rate and high reliability.
■ また、半導体素子や回路基板が加圧、硬化時に変形
しないので、変形によるこれらの特性を損なう事がない
。■ Also, since semiconductor elements and circuit boards do not deform during pressurization and curing, their properties are not impaired due to deformation.
第１図は本発明の一実施例における実装体に用いる半導
体素子表面上の電極配置を示す平面図、第２図は本実施
例の実装体の断面図、第３図は従来の実装体に用いる半
導体素子の電極配置を示す平面図、第４図は従来の実装
体の製造方法を示す断面図、第５図は従来の実装体の断
面図である。
１・・・・・・半導体素子、３・・・・・・回路基板、
４・・・・・・配線電極、２０．２１・・・・・・電極
、２３・・・・・・樹脂。
代理人の氏名 弁理士 中 尾 敏 男 １１か１名第
１図
ｆ−一・ｆ算イト皇３−
第２図 ３−回悶仮
４・−一ぬ乙裸情ζオ壱に
第４図
第５図FIG. 1 is a plan view showing the arrangement of electrodes on the surface of a semiconductor element used in a package according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the package according to this embodiment, and FIG. FIG. 4 is a plan view showing the electrode arrangement of the semiconductor element used, FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional mounting body, and FIG. 5 is a cross-sectional view of the conventional mounting body. 1... Semiconductor element, 3... Circuit board,
4... Wiring electrode, 20.21... Electrode, 23... Resin. Name of agent Patent attorney Toshi Nakao 11 or 1 person Figure 1 f-1, f calculation ito 3- Figure 2 3-Time agony 4--Inu nude emotion ζ O 1 Figure 4 Figure 5
Claims (2)
電極を有した第１、第２の基板間に絶縁樹脂を介在させ
、加圧、硬化し電極同志を接続してなる実装体。(1) A mounting body in which an insulating resin is interposed between a first and second substrate having protruding electrodes provided at the periphery and central region of the surface of the substrate, and the electrodes are connected by pressurization and curing.
特許請求の範囲第１項記載の実装体。(2) The package according to claim 1, wherein the insulating resin is cured with light or heat while being pressurized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62129324A JPS63293840A (en) | 1987-05-26 | 1987-05-26 | Packaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62129324A JPS63293840A (en) | 1987-05-26 | 1987-05-26 | Packaging body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63293840A true JPS63293840A (en) | 1988-11-30 |
Family
ID=15006770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62129324A Pending JPS63293840A (en) | 1987-05-26 | 1987-05-26 | Packaging body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63293840A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5811317A (en) * | 1995-08-25 | 1998-09-22 | Texas Instruments Incorporated | Process for reflow bonding a semiconductor die to a substrate and the product produced by the product |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173849A (en) * | 1984-02-20 | 1985-09-07 | Fujitsu Ltd | Mounting method for semiconductor chip |
| JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-05-26 JP JP62129324A patent/JPS63293840A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173849A (en) * | 1984-02-20 | 1985-09-07 | Fujitsu Ltd | Mounting method for semiconductor chip |
| JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5811317A (en) * | 1995-08-25 | 1998-09-22 | Texas Instruments Incorporated | Process for reflow bonding a semiconductor die to a substrate and the product produced by the product |
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