JP3531580B2 - Bonding method - Google Patents
Bonding methodInfo
- Publication number
- JP3531580B2 JP3531580B2 JP2000129186A JP2000129186A JP3531580B2 JP 3531580 B2 JP3531580 B2 JP 3531580B2 JP 2000129186 A JP2000129186 A JP 2000129186A JP 2000129186 A JP2000129186 A JP 2000129186A JP 3531580 B2 JP3531580 B2 JP 3531580B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- wire
- semiconductor chip
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップをボ
ンディングする方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of bonding a semiconductor chip.
【０００２】[0002]
【従来の技術】半導体チップを基板又はパッケージにダ
イボンディングしてさらに半導体チップの電極と基板又
はパッケージの電極とをワイヤーボンディングにより接
続する場合、通常、半導体チップを接着剤等を介して基
板又はパッケージ上に載置して、その接着剤を硬化した
後、電極間をワイヤーボンディングにより接続してい
る。When a semiconductor chip is die-bonded to a substrate or a package and electrodes of the semiconductor chip and electrodes of the substrate or the package are connected by wire bonding, the semiconductor chip is usually attached to the substrate or the package with an adhesive or the like. After being placed on top of the adhesive and cured, the electrodes are connected by wire bonding.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、ボンデ
ィングワイヤーが接合された部分の接合強度が十分出な
い部分が発生し、それにより製造歩留まりが悪化すると
いう問題点があった。特に２番目に接合される第２ボン
ド部は、非常に薄く（４〜７μｍ程度）伸ばされて接合
されていることから、このような問題が顕著に生じてい
た。However, there is a problem in that a portion where the bonding wire is joined does not have a sufficient joining strength, which causes a decrease in manufacturing yield. In particular, since the second bond portion to be second bonded is stretched and bonded very thinly (about 4 to 7 μm), such a problem remarkably occurs.
【０００４】そこで、本発明はボンディングワイヤーが
接合された部分において十分な接合強度が得られるボン
ディング方法を提供することを目的とする。Therefore, it is an object of the present invention to provide a bonding method capable of obtaining a sufficient bonding strength at a portion where a bonding wire is bonded.
【０００５】[0005]
【課題を解決するための手段】以上の目的を達成するた
めに、本発明に係る第１のボンディング方法は、基体上
に半導体チップを熱硬化性樹脂からなる接着剤によりダ
イボンディングして、半導体チップの電極と上記基体に
形成された電極とをワイヤーボンディングにより接続す
るボンディング方法において、上記半導体チップを上記
基体上に上記接着剤を介して載置して、その接着剤を硬
化温度より低い温度で仮硬化することと、上記仮硬化し
た後にワイヤーボンディングをすることと、上記ワイヤ
ーボンディング後に上記接着剤を上記硬化温度で本硬化
することを含むことを特徴とする。以上のように構成さ
れた本発明に係るボンディング方法では、半導体チップ
をダイボンディングする熱硬化性樹脂からなる接着剤
を、硬化温度より低い温度で仮硬化した後に、必要なワ
イヤーボンディングをし、その後に、所定の硬化温度で
本硬化するようにしているので、電極表面が汚染されて
いない状態でボンディングをすることができ、ボンディ
ング部分の接合強度を向上させることができる。In order to achieve the above object, a first bonding method according to the present invention is a semiconductor bonding method, in which a semiconductor chip is die-bonded on a substrate with an adhesive made of a thermosetting resin to form a semiconductor. In a bonding method for connecting an electrode of a chip and an electrode formed on the base by wire bonding, the semiconductor chip is placed on the base via the adhesive, and the adhesive is heated to a temperature lower than a curing temperature. And temporary bonding, wire bonding after the temporary hardening, and main hardening of the adhesive at the hardening temperature after the wire bonding. In the bonding method according to the present invention configured as described above, an adhesive made of a thermosetting resin for die-bonding a semiconductor chip is temporarily cured at a temperature lower than the curing temperature, and then necessary wire bonding is performed. In addition, since the main curing is performed at a predetermined curing temperature, the bonding can be performed in a state where the electrode surface is not contaminated, and the bonding strength of the bonding portion can be improved.
【０００６】また、本発明に係る第２のボンディング方
法は、基体上に半導体チップを接着剤によりダイボンデ
ィングして、半導体チップの電極と上記基体に形成され
た電極とをワイヤーボンディングにより接続するボンデ
ィング方法において、上記半導体チップの電極にワイヤ
ーの一端を接合し、そのワイヤーの他端を上記基体の電
極とを接合した後に、そのワイヤーの他端と上記基体の
電極との接合部分を合金化を促進するように加熱するこ
とを含むことを特徴とする。以上の第２のボンディング
方法では、ボンディングをした後に、ワイヤーと電極と
の間の合金化が促進されるようにボンディング接合部分
を加熱しているので、ボンディング部分の接合強度を向
上させることができる。A second bonding method according to the present invention is a bonding method in which a semiconductor chip is die-bonded on a base with an adhesive, and an electrode of the semiconductor chip and an electrode formed on the base are connected by wire bonding. In the method, one end of the wire is joined to the electrode of the semiconductor chip, the other end of the wire is joined to the electrode of the base body, and the joint portion between the other end of the wire and the electrode of the base body is alloyed. It is characterized by including heating so as to accelerate. In the second bonding method described above, the bonding joint portion is heated after the bonding so as to promote alloying between the wire and the electrode, so that the joint strength of the bonding portion can be improved. .
【０００７】[0007]
【発明の実施の形態】以下、図面を参照しながら本発明
に係る実施の形態について説明する。本発明に係る実施
の形態のボンディング方法は、基板又はパッケージ等の
基体上に半導体チップを熱硬化性樹脂からなる接着剤に
よりダイボンディングして、半導体チップの電極と基板
又はパッケージに形成された電極とをワイヤーボンディ
ングするボンディング方法において、以下のようなステ
ップでボンディングすることを特徴としている。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. A bonding method according to an embodiment of the present invention is a method in which a semiconductor chip is die-bonded onto a substrate such as a substrate or a package with an adhesive made of a thermosetting resin, and an electrode of the semiconductor chip and an electrode formed on the substrate or the package. In the bonding method of wire-bonding to and, the bonding is characterized by the following steps.
【０００８】本方法においては、まず、半導体チップを
基板又はパッケージ上の半導体チップを搭載する部分
に、例えばエポキシ樹脂からなる熱硬化性接着剤を塗布
して、その熱硬化性接着剤の上に半導体チップを載置し
て必要に応じて加圧する（第１ステップ）。次に、その
熱硬化性接着剤をその硬化温度以下の温度で仮硬化（プ
リキュア）することにより、半導体チップを少なくとも
ワイヤーボンディングが可能になる程度に仮固定する
（第２ステップ）。次いで、半導体チップ上に形成され
た電極と基板又はパッケージに形成された電極とをワイ
ヤーボンディングすることにより接続する（第３ステッ
プ）。そして、ワイヤーボンディング後に半導体チップ
を基板又はパッケージに仮固定している熱硬化性接着剤
を決められた硬化温度で本硬化（ポストキュア）させ
る。In this method, first, a semiconductor chip is applied to a portion of a substrate or a package on which the semiconductor chip is mounted by applying a thermosetting adhesive made of, for example, an epoxy resin, and the thermosetting adhesive is applied onto the thermosetting adhesive. A semiconductor chip is placed and pressure is applied as necessary (first step). Next, the thermosetting adhesive is temporarily cured (pre-cured) at a temperature equal to or lower than the curing temperature to temporarily fix the semiconductor chip to the extent that wire bonding is possible (second step). Next, the electrodes formed on the semiconductor chip and the electrodes formed on the substrate or the package are connected by wire bonding (third step). Then, after wire bonding, the thermosetting adhesive that temporarily fixes the semiconductor chip to the substrate or package is fully cured (post-cured) at a determined curing temperature.
【０００９】すなわち、本実施の形態のボンディング方
法は、半導体チップをダイボンディングする熱硬化性接
着剤を、硬化温度より低い温度で仮硬化する工程と所定
の（又は所定の範囲の）硬化温度で本硬化する工程の２
回に分けて硬化させ、その仮硬化と本硬化の間で、必要
なワイヤーボンディングをすることを特徴とし、これに
よりワイヤーボンディング部分における十分な接合強度
を確保している。すなわち、熱硬化性樹脂は、硬化温度
で硬化させる時に溶媒の揮発や架橋に伴ってガスが発生
し、そのガスにより電極表面が汚染されてボンディング
部分の接合強度を悪化させる。しかしながら、本実施の
形態では、ガスの発生、特に架橋に伴うガスの発生を抑
制できる、硬化温度より低い温度で仮硬化した後に、必
要なワイヤーボンディングを行っているので、電極表面
が汚染されていない状態でボンディングをすることがで
き、ボンディング部分の接合強度を向上させることがで
きる。尚、本明細書でいう、熱硬化性樹脂の硬化温度と
は、熱硬化性樹脂において架橋反応を起こさせるのに適
した温度であって、その熱硬化性樹脂を最も効果的に硬
化させるための特定又は一定の幅を持った温度をいう。That is, in the bonding method of this embodiment, a thermosetting adhesive for die-bonding a semiconductor chip is temporarily cured at a temperature lower than the curing temperature and a predetermined (or a predetermined range) curing temperature. Step 2 of main curing
It is characterized in that it is cured separately and the necessary wire bonding is performed between the temporary curing and the main curing, whereby sufficient bonding strength in the wire bonding portion is secured. That is, when the thermosetting resin is cured at the curing temperature, a gas is generated due to volatilization and crosslinking of the solvent, and the gas contaminates the electrode surface to deteriorate the bonding strength of the bonding portion. However, in the present embodiment, generation of gas, in particular, generation of gas associated with cross-linking can be suppressed, and since necessary wire bonding is performed after temporary curing at a temperature lower than the curing temperature, the electrode surface is contaminated. Bonding can be performed in the absence of the bonding, and the bonding strength of the bonding portion can be improved. Incidentally, the curing temperature of the thermosetting resin as referred to herein is a temperature suitable for causing a crosslinking reaction in the thermosetting resin, and in order to cure the thermosetting resin most effectively. The temperature that has a specific or constant range.
【００１０】以下、実施例及び種々の実験検討の結果を
基に、本発明の効果を説明する。図１には、異なるボン
ディング方法により作製したサンプルにおける、ボンデ
ィング接合部分の強度を示すグラフである。尚、この図
１の表に示した接合強度は、半導体チップの電極パッド
を最初にワイヤーを接続し（第１ボンディング）、次に
基板に形成された電極をワイヤーに接続（第２ボンディ
ング）した場合の、第２ボンディング部分の接続強度を
示したものである。また、評価した部分接合部分の総数
は、７０ポイントであり、グラフにはその平均値と±３
σ（σは標準偏差）の幅を示している。The effects of the present invention will be described below based on the examples and the results of various experimental studies. FIG. 1 is a graph showing the strength of a bonding joint portion in samples manufactured by different bonding methods. The bonding strength shown in the table of FIG. 1 was obtained by connecting the electrode pad of the semiconductor chip to the wire first (first bonding) and then connecting the electrode formed on the substrate to the wire (second bonding). In this case, the connection strength of the second bonding portion is shown. Also, the total number of evaluated partial joints is 70 points, and the graph shows the average value and ± 3.
The width of σ (σ is standard deviation) is shown.
【００１１】具体的には、以下のような工程により各試
料を作成した。
（１）比較例．
本比較例は、基板と半導体チップをダイボンディングす
るための熱硬化性樹脂を、仮硬化することなく、１８０
℃、１．５時間の条件で硬化させた後に、半導体チップ
の電極パッドと基板の電極とをワイヤーボンディングし
た従来例の方法によるものである。
（２）検討１．
本検討１は、基板と半導体チップをダイボンディングす
るための熱硬化性樹脂を、所定の硬化温度より低い１５
０℃、１．５時間の条件で硬化させた後に、半導体チッ
プの電極パッドと基板の電極とをワイヤーボンディング
した従来例の方法によるものである。尚、本検討１は実
験のために行ったものであり、熱硬化性樹脂は十分硬化
されていないため、実際の製造方法としては採用できな
いものである。
（３）検討２．
本検討２は、基板と半導体チップをダイボンディングす
るための熱硬化性樹脂を、仮硬化することなく、１８０
℃、１．５時間で真空高温槽により硬化した後に、半導
体チップの電極パッドと基板の電極とをワイヤーボンデ
ィングした方法によるものである。
（４）実施例．
本実施例は、基板と半導体チップをダイボンディングす
るための熱硬化性樹脂を、所定の硬化温度より低い１５
０℃、１．５時間の条件で仮硬化した後に、半導体チッ
プの電極パッドと基板の電極とをワイヤーボンディング
し、その後で所定の硬化温度である１８０℃で１時間の
条件で熱硬化性樹脂を本硬化した本実施の形態の方法に
より作成したものである。Specifically, each sample was prepared by the following steps. (1) Comparative example. In this comparative example, a thermosetting resin for die-bonding a substrate and a semiconductor chip is used for 180
This is a conventional method in which the electrode pads of the semiconductor chip and the electrodes of the substrate are wire-bonded after curing at 1.5 ° C. for 1.5 hours. (2) Study 1. In this study 1, a thermosetting resin for die-bonding a substrate and a semiconductor chip is used at a temperature lower than a predetermined curing temperature.
This is a conventional method in which the electrode pad of the semiconductor chip and the electrode of the substrate are wire-bonded after being cured at 0 ° C. for 1.5 hours. This Study 1 was conducted for an experiment, and the thermosetting resin is not sufficiently cured, and therefore cannot be adopted as an actual manufacturing method. (3) Study 2. In this study 2, a thermosetting resin for die-bonding a substrate and a semiconductor chip was used for 180
This is a method in which the electrode pad of the semiconductor chip and the electrode of the substrate are wire-bonded after being cured in a vacuum high temperature tank at 1.5 ° C. for 1.5 hours. (4) Example. In this embodiment, a thermosetting resin for die-bonding a substrate and a semiconductor chip is used at a temperature lower than a predetermined curing temperature.
After temporary curing at 0 ° C. for 1.5 hours, the electrode pads of the semiconductor chip and the electrodes of the substrate are wire-bonded, and then a thermosetting resin at 180 ° C. which is a predetermined curing temperature for 1 hour. It is produced by the method of the present embodiment in which the above is fully cured.
【００１２】以上の図１のグラフに示した結果から明ら
かなように、本実施の形態の方法（実施例）によれば、
従来例（比較例）に比較して、第２ボンディング部分の
接合強度は平均値で約１．５倍強に向上させることがで
きた。また、図１のグラフに示した結果によれば、本実
施の形態の方法（実施例）は検討１の方法で作製した試
料に比較しても接合強度を向上させることができること
が明らかになった（この理由は後述する。）。尚、真空
高温槽により硬化させた検討２は、４つの例のうち最も
優れた結果を示し、本検討２の方法は装置が大掛かりに
なる等の課題があるものの、より接合強度が要求される
場合には十分適用可能な方法である。As is clear from the results shown in the graph of FIG. 1, according to the method (example) of this embodiment,
As compared with the conventional example (comparative example), the bonding strength of the second bonding portion could be improved to about 1.5 times as an average value. In addition, according to the results shown in the graph of FIG. 1, it is clear that the method of this embodiment (Example) can improve the bonding strength even when compared with the sample manufactured by the method of Study 1. (The reason for this will be described later.) Note that Study 2 which was cured in a vacuum high temperature tank showed the best result among the four examples, and although the method of Study 2 has problems such as a large scale of the apparatus, more bonding strength is required. It is a method that is sufficiently applicable in some cases.
【００１３】第１ボンディング部分の接合強度は、実施
例の試料が平均値で約８０ｇｆであったのに対して、比
較例の試料は平均値で約５０ｇｆであり、本実施の形態
の方法によれば、第１ボンディング部分の接合強度も従
来に比較して大幅に向上させることができることが確認
された。The bonding strength of the first bonding portion was about 80 gf on average for the sample of the example, whereas it was about 50 gf on average for the sample of the comparative example. According to this, it was confirmed that the bonding strength of the first bonding portion can be significantly improved as compared with the conventional one.
【００１４】また、図３は、比較例、検討１，２及び実
施例にしたがって作製した試料を、ワイヤーボンディン
グした後に所定の位置でワイヤーを引っ張って破壊試験
を行ったときの破壊された部分の割合を示すグラフであ
る。尚、図３のグラフにおいて、Ａ〜Ｆの記号で示す部
分は、図２において示したＡ〜Ｆの部分で破壊されたも
のの割合を示している。また、図２において、Ｘの符号
を付して示す部分は、破壊試験に際してワイヤー１を引
っ張った位置を示し、半導体チップ５は基板３上に形成
された電極２上にダイボンディングされ、半導体チップ
５の電極が基板３上の電極２にワイヤーボンディングさ
れている。この図３から明らかなように、実施例におい
てＦの位置で破壊されたもの割合は、比較例においてＦ
の位置で破壊されたものの割合より少なく、この破壊試
験においても、第２ボンディング部分の接合強度が向上
したことが示された。Further, FIG. 3 shows a broken portion of a sample manufactured according to Comparative Examples, Examinations 1 and 2, and an example, which was subjected to wire bonding and then subjected to a breaking test by pulling a wire at a predetermined position. It is a graph which shows a ratio. In the graph of FIG. 3, the portions indicated by the symbols A to F show the proportions of those destroyed in the portions A to F shown in FIG. In addition, in FIG. 2, the portion indicated by the symbol X indicates the position where the wire 1 is pulled during the destructive test, and the semiconductor chip 5 is die-bonded onto the electrode 2 formed on the substrate 3, The electrode 5 is wire-bonded to the electrode 2 on the substrate 3. As is clear from this FIG. 3, the ratio of those destroyed at the position of F in the example is F in the comparative example.
It was smaller than the proportion of those that were broken at the position of, and it was shown in this breaking test that the bonding strength of the second bonding portion was improved.
【００１５】また、図４、図５は、図１のグラフに示し
た結果において、本実施の形態の方法（実施例）が検討
１の方法で作製した試料に比較してさらに接合強度を向
上させることができる理由を説明するための図である。
図４（ａ）に示した写真は、基板と半導体チップをダイ
ボンディングするための熱硬化性樹脂を所定の硬化温度
より低い１５０℃、１時間の条件で仮硬化した後に、半
導体チップの電極パッドと基板の電極とをワイヤーボン
ディングし、その後で所定の硬化温度である１８０℃で
０．５時間の条件で熱硬化性樹脂を本硬化した本実施の
形態の方法により作成した試料において、第２ボンディ
ング部分においてワイヤーをはがした後の、基板上の電
極の状態を示すものである。図５（ａ）に示した写真
は、基板と半導体チップをダイボンディングするための
熱硬化性樹脂を所定の硬化温度より低い１５０℃、０．
５時間の条件で仮硬化した後に、半導体チップの電極パ
ッドと基板の電極とをワイヤーボンディングし、第２ボ
ンディング部分においてワイヤーをはがした後の、基板
上の電極の状態を示すものである。また、図４（ｂ）、
図５（ｂ）はそれぞれ、図４（ａ）、図５（ａ）を説明
するためにその写真に対応させて写真上の領域を示した
図である。In addition, in the results shown in the graph of FIG. 1, FIGS. 4 and 5 show that the method (Example) of the present embodiment further improves the bonding strength as compared with the sample manufactured by the method of Study 1. It is a figure for explaining the reason why it can be made.
In the photograph shown in FIG. 4A, the thermosetting resin for die-bonding the substrate and the semiconductor chip is temporarily cured under the condition of 150 ° C., which is lower than a predetermined curing temperature, for 1 hour, and then the electrode pad of the semiconductor chip And the electrode of the substrate are wire-bonded, and then a thermosetting resin is fully cured under the condition of a predetermined curing temperature of 180 ° C. for 0.5 hour. It shows the state of the electrodes on the substrate after the wire is peeled off at the bonding portion. In the photograph shown in FIG. 5A, a thermosetting resin for die-bonding a substrate and a semiconductor chip is used at 150 ° C., which is lower than a predetermined curing temperature, at 0.
It shows the state of the electrode on the substrate after wire-bonding the electrode pad of the semiconductor chip and the electrode of the substrate after the temporary curing under the condition of 5 hours and peeling the wire at the second bonding portion. In addition, FIG.
FIG. 5B is a diagram showing regions on the photograph corresponding to the photographs for explaining FIGS. 4A and 5A, respectively.
【００１６】この図４と図５の写真に示した試料は、ワ
イヤーボンディング前における熱硬化性樹脂の硬化時間
も異なるがその相違はボンディングとの関連では無視し
得ると思われ、実質的にはワイヤーボンディング後に１
８０℃の温度に０．５時間の間さらされたか否かの違い
のみと考えることができる。この図４と図５の写真を比
較すると、ワイヤーと基板電極とが拡散固溶した部分
（合金化した部分）面積が異なることがわかる。すなわ
ち、図４（ａ）の写真において、図４（ｂ）で５１の符
号を付して示すハッチング部分に対応する合金化してい
る領域の面積が、図５（ａ）の写真において、図５
（ｂ）で６１の符号を付して示すハッチング部分に対応
する合金化している領域の面積に比較して大きくなって
いる。The samples shown in the photographs of FIGS. 4 and 5 also differ in the curing time of the thermosetting resin before wire bonding, but the difference is considered to be negligible in connection with bonding, and is substantially 1 after wire bonding
It can only be considered the difference between being exposed to a temperature of 80 ° C. for 0.5 hours. Comparing the photographs of FIGS. 4 and 5, it can be seen that the areas where the wires and the substrate electrodes diffuse and form a solid solution (alloyed portions) are different. That is, in the photograph of FIG. 4A, the area of the alloyed region corresponding to the hatched portion indicated by reference numeral 51 in FIG.
It is larger than the area of the alloyed region corresponding to the hatched portion indicated by reference numeral 61 in (b).
【００１７】また、図５（ａ）において、の図５（ｂ）
の６３の符号を付して破線で示す領域に対応する領域
は、ワイヤーが基板電極に接触しているにも関わらず合
金化していない領域であって、図４（ａ）の本願発明に
係る図には存在しない領域である。すなわち、本願発明
に係る方法により作製した試料は、ボンディング直後に
は合金化していなかった領域が、ボンディング後に１８
０℃、０．５時間の加熱処理により、ワイヤーと基板電
極との接触部分を中心に合金化が促進され、合金化領域
が拡大され、ボンディング部分の接合強度が強化され
る。Further, in FIG. 5A, FIG.
The region corresponding to the region denoted by reference numeral 63 and indicated by a broken line is a region which is not alloyed even though the wire is in contact with the substrate electrode, according to the present invention of FIG. This area does not exist in the figure. That is, in the sample manufactured by the method according to the present invention, the region that was not alloyed immediately after bonding was 18
By heat treatment at 0 ° C. for 0.5 hours, alloying is promoted centering on the contact portion between the wire and the substrate electrode, the alloyed region is expanded, and the bonding strength of the bonding portion is strengthened.
【００１８】以上説明したように、本実施の形態のボン
ディング方法は、半導体チップをダイボンディングする
熱硬化性接着剤を、硬化温度より低い温度で仮硬化する
工程後に、必要なワイヤーボンディングをし、その後
に、所定の硬化温度で本硬化するようにしているので、
電極表面が汚染されていない状態でボンディングをする
ことができ、ボンディング部分の接合強度を向上させる
ことができる。As described above, according to the bonding method of the present embodiment, necessary wire bonding is performed after the step of temporarily curing the thermosetting adhesive for die-bonding the semiconductor chip at a temperature lower than the curing temperature, After that, since it is designed to be fully cured at a predetermined curing temperature,
Bonding can be performed in a state where the electrode surface is not contaminated, and the bonding strength of the bonding portion can be improved.
【００１９】また、本実施の形態のボンディング方法で
は、ボンディングをした後に熱硬化性樹脂を所定の硬化
温度で本硬化するようにしているので、ボンディング接
合部分が加熱されてワイヤーと電極との間の合金化が促
進され、ボンディング部分の接合強度を向上させること
ができる。Further, in the bonding method of the present embodiment, since the thermosetting resin is subjected to main curing at a predetermined curing temperature after bonding, the bonding joint portion is heated so that the bonding portion between the wire and the electrode is heated. Alloying is promoted, and the bonding strength of the bonding portion can be improved.
【００２０】尚、本実施の形態では、エポキシ系の熱硬
化性樹脂からなる接着剤を例に説明したが、本発明は熱
硬化性樹脂の種類に限定されるものではなく、種々の熱
硬化性樹脂からなる接着剤を用いることができる。ま
た、本発明はボンディングワイヤーの材質に限定される
ものではなく、本発明において、ボンディング用のワイ
ヤーは、Ａｕ，Ａｌ等の種々のワイヤーを用いることが
できる。さらに、本発明は半導体チップが基板の電極又
はパッケージの電極にボンディングされる方法に限定さ
れるものではなく、リードフレーム上にボンディングす
る場合等も含め種々の基体にボンディングする場合に適
用することができる。In the present embodiment, an adhesive made of an epoxy type thermosetting resin has been described as an example, but the present invention is not limited to the type of thermosetting resin, and various thermosetting resins can be used. An adhesive made of a conductive resin can be used. Further, the present invention is not limited to the material of the bonding wire, and various wires such as Au and Al can be used as the bonding wire in the present invention. Further, the present invention is not limited to the method of bonding the semiconductor chip to the electrode of the substrate or the electrode of the package, and can be applied to the case of bonding to various bases including the case of bonding on the lead frame. it can.
【００２１】[0021]
【発明の効果】以上詳細に説明したことから明らかなよ
うに、本発明に係るボンディング方法によれば、ボンデ
ィングワイヤーが接合された部分において十分な接合強
度が得られるボンディング方法を提供することができ
る。As is clear from the above description, according to the bonding method of the present invention, it is possible to provide a bonding method in which a sufficient bonding strength can be obtained at the portion where the bonding wire is bonded. .
【図１】 実施例、比較例等の異なるボンディング方法
により作製した試料における、ボンディング接合部分の
強度を示すグラフである。FIG. 1 is a graph showing the strength of a bonding joint portion in a sample manufactured by a different bonding method such as an example and a comparative example.
【図２】 ワイヤープル試験により破壊された箇所を示
す図である。FIG. 2 is a diagram showing a portion destroyed by a wire pull test.
【図３】 ワイヤープル試験により破壊された箇所の割
合を示す図である。FIG. 3 is a diagram showing a ratio of places destroyed by a wire pull test.
【図４】 （ａ）は本実施の形態の方法により作製され
た試料において、ワイヤーをはがした後の電極表面の顕
微鏡写真であり、（ｂ）は（ａ）の写真における領域を
定義し説明するための平面図である。FIG. 4 (a) is a micrograph of the electrode surface of the sample prepared by the method of the present embodiment after stripping the wire, and FIG. 4 (b) defines the region in the photograph of (a). It is a top view for explaining.
【図５】 （ａ）は比較例の方法により作製された試料
において、ワイヤーをはがした後の電極表面の顕微鏡写
真であり、（ｂ）は（ａ）の写真における領域を定義し
説明するための平面図である。FIG. 5 (a) is a micrograph of the electrode surface of the sample prepared by the method of Comparative Example after stripping the wire, and FIG. 5 (b) defines and explains the region in the photograph of (a). FIG.
１ ワイヤー、２ 電極、３ 基板、５ 半導体チッ
プ、５１ 合金化領域。1 wire, 2 electrodes, 3 substrates, 5 semiconductor chips, 51 alloyed regions.
Claims (2)
らなる接着剤によりダイボンディングして、半導体チッ
プの電極と上記基体に形成された電極とをワイヤーボン
ディングにより接続するボンディング方法において、 上記半導体チップを上記基体上に上記接着剤を介して載
置して、その接着剤を硬化温度より低い温度で仮硬化す
ることと、 上記仮硬化した後にワイヤーボンディングをすること
と、 上記ワイヤーボンディング後に上記接着剤を上記硬化温
度で本硬化することを含むことを特徴とするボンディン
グ方法。1. A bonding method, in which a semiconductor chip is die-bonded on a substrate with an adhesive made of a thermosetting resin, and an electrode of the semiconductor chip and an electrode formed on the substrate are connected by wire bonding. The chip is placed on the substrate via the adhesive, and the adhesive is temporarily cured at a temperature lower than the curing temperature; wire-bonding is performed after the adhesive is cured; A bonding method, which comprises main-curing an adhesive at the above-mentioned curing temperature.
ディングによる接合部分の合金化を促進させるための加
熱を兼ねる請求項１記載のボンディング方法。2. The bonding method according to claim 1, wherein the main hardening also serves as heating for promoting alloying of a joint portion by the wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000129186A JP3531580B2 (en) | 2000-04-28 | 2000-04-28 | Bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000129186A JP3531580B2 (en) | 2000-04-28 | 2000-04-28 | Bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001313301A JP2001313301A (en) | 2001-11-09 |
| JP3531580B2 true JP3531580B2 (en) | 2004-05-31 |
Family
ID=18638499
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000129186A Expired - Lifetime JP3531580B2 (en) | 2000-04-28 | 2000-04-28 | Bonding method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4562118B2 (en) | 2003-12-19 | 2010-10-13 | 日東電工株式会社 | Manufacturing method of semiconductor device |
| JP4529041B2 (en) * | 2004-09-24 | 2010-08-25 | スタンレー電気株式会社 | Circuit board modularization method |
| CN100472741C (en) | 2005-02-21 | 2009-03-25 | 日东电工株式会社 | Manufacturing method for semiconductor device |
| US20090001611A1 (en) | 2006-09-08 | 2009-01-01 | Takeshi Matsumura | Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method |
| US7772040B2 (en) | 2006-09-12 | 2010-08-10 | Nitto Denko Corporation | Manufacturing method of semiconductor device, adhesive sheet used therein, and semiconductor device obtained thereby |
| JP4523611B2 (en) * | 2007-02-20 | 2010-08-11 | 日東電工株式会社 | Manufacturing method of semiconductor device |
| JP5279196B2 (en) * | 2007-05-02 | 2013-09-04 | 盛岡セイコー工業株式会社 | Semiconductor element fixing method |
| US8592260B2 (en) | 2009-06-26 | 2013-11-26 | Nitto Denko Corporation | Process for producing a semiconductor device |
| JP2015046667A (en) * | 2013-08-27 | 2015-03-12 | セイコーエプソン株式会社 | Method for manufacturing electronic device |
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