TWI353642B - Method for forming a die attach layer during semic - Google Patents

Method for forming a die attach layer during semic Download PDF

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Publication number
TWI353642B
TWI353642B TW096147095A TW96147095A TWI353642B TW I353642 B TWI353642 B TW I353642B TW 096147095 A TW096147095 A TW 096147095A TW 96147095 A TW96147095 A TW 96147095A TW I353642 B TWI353642 B TW I353642B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
core layer
die
stiffener
Prior art date
Application number
TW096147095A
Other languages
Chinese (zh)
Other versions
TW200926314A (en
Inventor
Wen Jeng Fan
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096147095A priority Critical patent/TWI353642B/en
Publication of TW200926314A publication Critical patent/TW200926314A/en
Application granted granted Critical
Publication of TWI353642B publication Critical patent/TWI353642B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

1353642 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體晶片封裝技術 於一種半導體封裝製程中形成黏晶層之方法 【先前技術】 在-般的半導體封裝構造中，利用點晶材料 晶片黏著固定在一基板上。黏晶材 王要區別 類’-為以印刷或點膠形成之液態或膠狗態之膠 一為以固態貼附之黏晶膠帶。其中，印刷形成之 膠稠態之膠體具有黏晶材料節省與調整塗施= 大之優點，但對於基板之翹曲度甚為敏感，易有 膠之問題。習知的基板會在其上下表面各形成有 層，故基板之翹曲問題尚不嚴重。然而當基板之 所改變時，就會影響到黏晶材料之選用。 請參閱第1圖所示’一種習知半導體封裝構 主要包含一黏晶強化型基板丨i 0、_晶片1 2〇、 膠帶130、複數個銲線14〇以及一封膠體15〇。 11 0係包含有一基板核心層丨丨丨以及僅有一層之 層1 1 2，該下防銲層丨丨2係形成於該基板核心層 下表面1 1 4。該基板核心層丨丨丨之上表面丨丨3則 層，故該黏晶膠帶1 3 0直接貼附於該基板核心層 以黏接該晶片1 20。該些銲線丨4〇係通過該基板 打線槽孔1 1 5以電性連接該晶片i 2 〇之複數個銲 至s玄基板1 1 0之對應接指1 1 6。該封膠體1 5 〇係 係有關 以將一 為兩大 體’另 液態或 積彈性 靡占晶溢 防鲜 ,结構有 造100 一黏晶 該基板 下防鲜 1 1 1之 無防銲 111， 1 10之 墊121 密封該 6 1353642 晶片1 20與該些銲線1 40。複數個銲球i 60係設置於該 基板110之球墊117。通常該基板π〇之該基板核心層 • 1 1 1之材質係為玻纖布含浸樹脂，對於該黏晶膠帶1 3 〇 或其它黏晶材料有著較佳黏著效果，藉以加強該晶片 12〇之接合強度。然而該基板110因僅在該下表面114 形成有一下防焊層1 1 2，特別是使用基板條進行半導體 封裝時’該基板1 1 0的翹曲程度會更加明顯，使得在製 中無法以印刷方式直接在該基板核心層1 1 1上塗佈 液態之黏晶材料的困難度較高，並且翹曲嚴重之基板條 不便於製程傳輸與被封裝機台固定。目前一種習知半導 體封裝構造1 0 0之製造方法是先將該基板i i 〇分割成單 顆 y - 以降低輕曲度，但已無法提供一大面積之印刷表 面仍無法使用由印刷形成之液態或膠稠態之膠體作為 B 1 . 曰0才料’並且不利於製裎傳輸與基板定位。此外，製 成本亦是大幅增加。 •【發明内容】 本發明之主要目的係在於提供一種半導體封裝製程 方 點晶層之方法’藉由模板印刷（Stenci丨Printing) 式使黏晶材料直接塗佈於一晶片載體之基板核心 層，以^ σ強黏晶強度。利用一晶片載體上之加勁件以及 一* 与 μ、 θ平被印刷模板可以抑制晶片載體之翹曲以避免黏 日曰材料，，，， 方 溢流’故能在黏晶強化型晶片載體上以低成本 式•形成黏晶材料。 發明的目的及解決其技術問題是採用以下技術方 7 1353642 案來實現的。依據本發明之一種半導體封裝製程中 黏晶層之方法，首先，提供一晶片載體，該晶片載 包含一基板核心層與一加勁件，該基板核心層之一 . 面包含有複數個單元黏晶區以及一圍繞該些單元 區之周邊區，其中該加勁件係局部形成於該基板核 之該上表面，以覆蓋該周邊區，但顯露該些單元 區。接著，提供一非平板印刷模板，該非平板印刷 係具有一非平坦壓貼面，其中該非平坦壓貼面之周 * 為厚度減少，用以補償該加勁件之厚度，該非平板 模板更具有複數個印刷開孔。之後，壓附該非平板 模板至該晶片載體，以使該些印刷開孔顯露該基板 層之該些單元黏晶區，並且該非平板印刷模板係為 陷地貼觸至該基板核心層與該加勁件。最後，通過 平板印刷模板之該些印刷開孔，印刷一黏晶材料至 板核心層之該些單元黏晶區。 • 本發明的目的及解決其技術問題還可採用以下 措施進一步實現。 在前述的半導體封裝製程中形成黏晶層之方法 該加勁件係可為環形框。 在前述的半導體封裝製程中形成黏晶層之方法 該晶片載體係可為一印刷電路板並具有一下防焊為 下防：tf·層係大致覆蓋該基板核心層之—下表面，該 烊層之覆蓋面積係大於該加勁件之覆蓋面積。 在前述的半導體封裝製程中形成黏晶層之方法 形成 體係 上表 黏晶 心層 黏晶 模板 邊係 印刷 印刷 核心 無塌 該非 該基 技術 中， 中， ，該 下防 中， 8 力0勁件之厚度係 1353642 該加勁件係可為-加厚型圖案化 板核心層之該些單元黏晶區，並且該層’而不覆盍該 於該下防焊層》 在前述的半導體封裝製程中 可另包含-預烘烤步驟，以使該 ：：：方法中 在該基板核心層上之均厚黏晶層。’部分固化為 在前述的半導體封裝製裎中 表程中形成黏晶層之方法中 δ亥晶片載體係可為一基板條，且在 仕母一早元黏晶區内 設至少一打線槽孔’並在印刷捭兮Τ p刷時s亥非平板印刷模板係 全封閉該些打線槽孔。 【實施方式】 依據本發明之一具體實施例，揭示一種半導體封 製程中形成黏晶層之方法。第2A至2E圖係有關於 半導體封裝製程中形成黏晶層之方法。首先，請參閱 2Α及3圖所示，提供一晶片載體210，該晶片載體2 係包含一基板核心層2 1 1與一加勁件2 1 2，該基板核 層211之一上表面213包含有複數個單元黏晶區215 及一圍繞該些單元黏晶區215之周邊區2 1 6。請再參 第3圖所示，其中該加勁件2 1 2係局部形成於該基板 心層2 11之該上表面2 1 3 ’以覆蓋該周邊區2 1 6，但 露該些單元黏晶區2 1 5 ’用以增加該晶片載體2 1 0之 度，並避免該晶片載體2 1 〇翹曲’以利後續之半導體 裝製程。在本實施例中，該晶片載體210係可為一印 電路板並具有一下防焊層217’該下防焊層217係大 基 大 開 完 裝 該 第 10 心 以 閱 核 顯 強 封 刷 致 9 1353642 覆蓋該基板核心層211之一下表面214,該下防坤 之覆蓋面積係大於該加勁件212之覆蓋面積。在 例中’如第3圖所示，該加勁件2 12係可為環形 加勁件2 1 2係可為一加厚型圖案化防焊層，而不 基板核心層2 1 1之該些單元黏晶區2 1 5並且該 212之厚度係大於該下防焊層217之厚度。再如 所示’在本實施例中，該晶片載體210係可為 條’且在每一單元黏晶區2 1 5内開設至少一打 • 218。 接著，請參閱第2B圖及4所示，提供一非平 模板220，該非平板印刷模板220係具有—非平 面221 ’其中該非平坦壓貼面221之周邊222係 減少’用以補償該加勁件2 1 2之厚度，該非平板 板220更具有複數個印刷開孔223。該些印刷保 係對準於該基板核心層2 1 1之該些單元黏晶區: φ 之後’請參閱第2C圖所示，壓附該非平板印 2 2 0至該晶片載體2 1 0，以使該些印刷開孔2 2 3 基板核心層2 1 1之該些單元黏晶區2丨5，並且該 印刷模板2 2 0係為無塌陷地貼觸至該基板核心為 該加勁件212。再如第2C圖所示，該非平板印 2 2 0係元全封閉该基板核心層2 1 1之該些打線槽 最後’請參閱第2D及3圖所示，通過該非平 模板220之該些印刷開孔223，印刷一黏晶材料 該基板核心層2 1 1之該些單元黏晶區2 1 5。在權 :層 217 本貫施 框❶該 覆蓋該 加勁件 第3圖 一基板 線槽孔 板印刷 坦壓貼 為厚度 印刷模 孔223 ,15 〇 刷模板 顯露該 非平板 211與 刷模板 孔 218。 板印刷 230至 板印刷 10 1353642 (stencil printing)過程中，該黏晶材料23〇係以一到刀 240到過並填充在該非平板印刷模板22〇之該些印刷開 孔223中，以印刷形成在該基板核心層2丨丨上該非平 板印刷模板220係可控制該黏晶材料23〇之形成厚度。 由於該黏晶材料230係直接形成於該基板核心層2 i ! 上，故具有加強黏晶強度之功效。較佳地，該黏晶材料 230係可選用液態膠體或膠稠態膠體，如液態環氧樹脂 或是膠稠態B階黏膠，以降低製造成本。在本實施例 中，凊參閱第2D與3圖所示，由於該非平板印刷模板 2 2 0係元全封閉該些打線槽孔2丨8，故在印刷時可避免 3亥黏aa材料2 3 0流入該些打線槽孔2丨8 ’而影響後續封 裝製程。 具體而言’請參閱第2E圖所示，該半導體封裝製程 中形成黏晶層之方法中係可另包含一預烘烤步驟，以使 戎黏晶材料230部分固化為一在該基板核心層2U上之 均厚黏晶層。較佳地，該黏晶材料23〇係可為在室溫下 成為不具有流動性與黏性之B階膠體，但在加熱後仍然 具有黏接晶片之黏性。 因此’由上述可知該方法不僅可以利用模板印刷方 式使該黏晶材料2 3 0直接塗佈於該基板核心層2丨丨，以 加強黏晶強度，又可以抑制該晶片載體2丨〇之翹曲並避 免该黏晶材料23 0之溢流’不但可以低成本製造亦可供 半導體封裝使用β 第5Α至5Ε圖繪示前述方法運用於半導體封裝製 11 1353642 程。請參閱第5A圖所示，將複數個具有録塾si〗之晶 片3 1 0設置於該晶片載體2丨〇上，利用適當加熱後會具 有黏性之該黏晶材料2 3 0將該些晶片3 1 0分別黏貼至該 基板核心層2 1 1之該些單元黏晶區2 1 5。該些晶片3 1 0 係以其形成有該些銲墊3 1 1之主動面朝向該晶片載體 210的方式设置於該晶片載體21〇上，並且每一晶片31〇 之該些銲墊311係分別對準於每一單元黏晶區215之該 打線槽孔2 1 8内。接著，請參閱第$ b圖所示，形成複 數個打線形成之銲線3 2 0，以達到該些晶片3丨〇與該晶 片載體2 1 0之間之電性連接。在本實施例中，該些銲線 3 2 0係通過每單元黏晶區2 1 5之該打線槽孔2丨8以連 接該晶片3 1 0之該些銲墊3丨丨至該基板核心層2丨丨之對 應接指。 接著，請參閱第5C圖所示，形成一封膠體33〇於1353642 IX. Description of the Invention: [Technical Field] The present invention relates to a method for forming a die bond layer in a semiconductor package process by a semiconductor chip package technology. [Prior Art] In a general semiconductor package structure, a dot crystal is used. The material wafer is adhesively attached to a substrate. Adhesive crystals Wang wants to distinguish between the class's - a liquid or gel-like gel formed by printing or dispensing. Among them, the gel-formed colloid formed by printing has the advantages of slime-saving material and adjustment coating, but it is very sensitive to the warpage of the substrate, and it is easy to have the problem of glue. Conventional substrates have layers formed on the upper and lower surfaces thereof, so that the warpage of the substrate is not serious. However, when the substrate is changed, the selection of the die-bonding material is affected. Referring to Fig. 1, a conventional semiconductor package mainly comprises a die-bonded substrate 丨i 0, a wafer 1 2 〇, a tape 130, a plurality of bonding wires 14 〇, and a colloid 15 〇. The 110 layer includes a substrate core layer 丨丨丨 and only one layer of the layer 112, and the lower solder mask layer 2 is formed on the lower surface of the substrate core layer 141. The surface of the substrate core layer is 丨丨3, so the adhesive tape 130 is directly attached to the substrate core layer to adhere the wafer 1200. The bonding wires 4 are electrically connected to the corresponding contacts 1 1 of the s-substrate 1 1 0 through the substrate wire slot 1 1 5 to electrically connect the plurality of pads of the wafer i 2 . The encapsulant 1 5 〇 system is related to one of two major bodies 'other liquid or elastic 靡 靡 晶 晶 晶 晶 晶 , , , , , , , , , , 100 100 100 100 100 100 100 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The pad 10 of 10 seals the 6 1353642 wafer 1 20 and the bonding wires 1 40. A plurality of solder balls i 60 are disposed on the ball pads 117 of the substrate 110. Generally, the substrate π〇 of the substrate core layer • 1 1 1 is made of fiberglass cloth impregnated resin, which has a better adhesion effect on the adhesive tape 1 3 〇 or other viscous material, thereby strengthening the wafer 12 Bonding strength. However, since the substrate 110 is formed with only the solder resist layer 112 in the lower surface 114, especially when the substrate strip is used for semiconductor packaging, the degree of warpage of the substrate 110 is more obvious, so that it is impossible to The printing method directly coats the liquid core material on the substrate core layer 11 1 with a high degree of difficulty, and the substrate strip with severe warpage is inconvenient for the process transfer to be fixed with the packaged machine. At present, a conventional semiconductor package structure 100 is manufactured by dividing the substrate ii 单 into a single y - to reduce the light curvature, but it is impossible to provide a large area of the printing surface and still cannot use the liquid formed by printing. Or a colloidal colloid as a B 1 . 曰 0 material and is not conducive to the crucible transport and substrate positioning. In addition, the cost of manufacturing has also increased significantly. SUMMARY OF THE INVENTION The present invention is directed to a method for providing a semiconductor package process square dot layer. The stencil printing method directly applies a die bond material to a substrate core layer of a wafer carrier. Strong viscous crystal strength with ^ σ. The use of a stiffener on a wafer carrier and a * and μ, θ flat printed template can suppress the warpage of the wafer carrier to avoid sticking the corrugated material, and, the square overflow can be on the die-hardened wafer carrier Form a sticky crystal material at a low cost. The object of the invention and the solution of the technical problem are achieved by the following technique 7 1353642. According to the method of the present invention, a method of bonding a die layer in a semiconductor package process, firstly, providing a wafer carrier comprising a substrate core layer and a stiffener, one of the core layers of the substrate. The bread contains a plurality of unit die-bonding regions And a peripheral region surrounding the unit regions, wherein the stiffening member is partially formed on the upper surface of the substrate core to cover the peripheral region, but the unit regions are exposed. Next, a non-lithographic printing plate is provided, the non-flat printing system having a non-flat pressing surface, wherein the circumference of the non-flat pressing surface is reduced in thickness to compensate the thickness of the stiffening member, and the non-flat plate template has a plurality of Print the opening. Thereafter, the non-plate template is attached to the wafer carrier, so that the printing openings expose the unit die-bonding regions of the substrate layer, and the non-lithographic template is in contact with the substrate core layer and the stiffening Pieces. Finally, a die-bonding material is printed through the printing openings of the stencil to the die-bonding regions of the cells in the core layer of the plate. • The object of the present invention and solving the technical problems thereof can be further achieved by the following measures. A method of forming a die bond layer in the aforementioned semiconductor package process The stiffener may be a ring frame. A method of forming a die bond layer in the foregoing semiconductor package process. The wafer carrier can be a printed circuit board and has a solder mask for the next step: the tf. layer substantially covers the lower surface of the substrate core layer. The coverage area is greater than the coverage area of the stiffener. In the foregoing semiconductor packaging process, a method of forming a die-bonding layer is formed on the system, and the surface of the die-bonded core layer is bonded to the edge of the printed printing core without collapse. The thickness is 1353642. The stiffening member can be the unit die-bonding region of the core layer of the thickened patterned plate, and the layer is 'overlying the lower solder resist layer'. In the foregoing semiconductor packaging process A pre-baking step may be additionally included to cause a blanket layer of uniform thickness on the core layer of the substrate in the ::: method. 'Partial curing is a method for forming a viscous layer in the surface of the semiconductor package, and the δ ray wafer carrier can be a substrate strip, and at least one wire slot is provided in the mother-early early-ear bond region. And when printing the 捭兮Τp brush, the non-lithographic stencil template completely closes the wire slot holes. [Embodiment] According to one embodiment of the present invention, a method of forming a die bond layer in a semiconductor package process is disclosed. The 2A to 2E drawings relate to a method of forming a die layer in a semiconductor packaging process. First, as shown in FIGS. 2 and 3, a wafer carrier 2 is provided. The wafer carrier 2 includes a substrate core layer 21 and a stiffener 2 1 2, and an upper surface 213 of the substrate core layer 211 includes A plurality of unit die-bonding regions 215 and a peripheral region 2 16 surrounding the unit die-bonding regions 215. Please refer to FIG. 3 again, wherein the stiffener 2 1 2 is partially formed on the upper surface 2 1 3 ′ of the substrate core layer 11 11 to cover the peripheral region 2 1 6 , but the cells are exposed. The region 2 1 5 ' is used to increase the degree of the wafer carrier 2 10 and to avoid warping of the wafer carrier 2 1 to facilitate the subsequent semiconductor fabrication process. In this embodiment, the wafer carrier 210 can be a printed circuit board and has a lower solder resist layer 217 ′. The lower solder resist layer 217 is a large base to open the 10th core to read the strong seal. 1353642 covers a lower surface 214 of the substrate core layer 211, and the coverage area of the lower barrier is greater than the coverage area of the stiffener 212. In the example, as shown in FIG. 3, the stiffener 2 12 can be a ring stiffener 2 1 2 can be a thickened patterned solder mask, and the cells of the substrate core layer 2 1 1 The die bond region 2 15 and the thickness of the 212 is greater than the thickness of the lower solder resist layer 217. Further, as shown, in the present embodiment, the wafer carrier 210 can be a strip' and at least one dozen 218 is provided in each of the unit die bonds 215. Next, referring to FIGS. 2B and 4, a non-flat template 220 is provided. The non-planar template 220 has a non-planar surface 221 'where the perimeter 222 of the non-flat pressing surface 221 is reduced' to compensate for the stiffener. The thickness of the 2 1 2 plate further includes a plurality of printing openings 223. The printing protection is aligned with the unit die-bonding regions of the substrate core layer 2 1 1 : after φ 'please refer to FIG. 2C to smear the non-lithographic printing 2 2 0 to the wafer carrier 2 1 0, So that the printing openings 2 2 3 of the substrate core layer 2 1 1 of the unit die-bonding region 2 丨 5, and the printing template 2 2 0 is non-collapsed to the substrate core is the stiffener 212 . As shown in FIG. 2C, the non-lithographic 2 20-element completely encloses the wire trenches of the substrate core layer 21 1 . Finally, please refer to FIGS. 2D and 3 , through the non-flat template 220 Printing the opening 223, printing a die-bonding material of the substrate core layer 2 1 1 of the unit die-bonding region 2 15 . In the right: layer 217, the frame is covered by the stiffener. Figure 3 A substrate line slot plate printing is pressed to the thickness of the printing die hole 223, 15 〇 the brush template reveals the non-plate 211 and the brush template hole 218. During the process of plate printing 230 to plate printing 10 1353642 (stencil printing), the die bonding material 23 is passed through a plurality of knives 240 and filled in the printing openings 223 of the non-lithographic printing template 22 to form a printing. The non-lithographic template 220 is controlled on the substrate core layer 2 to control the thickness of the die bond material 23. Since the die bonding material 230 is directly formed on the substrate core layer 2 i ! , it has the effect of enhancing the strength of the die bond. Preferably, the die-bonding material 230 is selected from a liquid colloid or a gel-like colloid, such as a liquid epoxy resin or a gel-like B-stage adhesive, to reduce manufacturing costs. In the present embodiment, as shown in FIGS. 2D and 3, since the non-lithographic template 2 2 0 element completely closes the wire slot 2 丨 8 , it is possible to avoid 3 ah aa material 2 3 during printing. 0 flows into the wire slot 2'8' and affects the subsequent packaging process. Specifically, as shown in FIG. 2E, the method of forming a die bond layer in the semiconductor package process may further include a prebaking step to partially cure the germanium die bond material 230 to a core layer of the substrate. The uniform thickness of the 2U layer. Preferably, the viscous material 23 is a B-stage colloid which does not have fluidity and viscosity at room temperature, but still has the adhesiveness of the bonded wafer after heating. Therefore, it can be seen from the above that the method can directly apply the die bonding material 230 to the core layer 2 of the substrate by using a stencil printing method to strengthen the bonding strength and suppress the warp of the wafer carrier. And avoiding the overflow of the die-bonding material 23' can be used not only for low-cost manufacturing but also for semiconductor package use. The fifth method is shown in Figure 5 to illustrate the method described above for semiconductor packaging. Referring to FIG. 5A, a plurality of wafers 310 having a recording history are disposed on the wafer carrier 2, and the adhesive material is viscous by appropriate heating. The wafers 310 are respectively adhered to the unit die-bonding regions 2 15 of the substrate core layer 2 1 1 . The wafers 3 10 are disposed on the wafer carrier 21 以 in such a manner that the active faces of the pads 3 1 1 are formed toward the wafer carrier 210 , and the pads 311 of each of the wafers 31 are They are respectively aligned in the wire slot 2 1 8 of each unit die bond region 215. Next, referring to FIG. 5b, a plurality of bonding wires formed by wire bonding are formed to achieve electrical connection between the wafers 3丨〇 and the wafer carrier 210. In this embodiment, the bonding wires 320 are passed through the wire slot 2丨8 of each of the die bonding regions 2 to 5 to connect the pads 3 of the die 310 to the substrate core. Corresponding fingers of layer 2丨丨. Next, please refer to Figure 5C to form a gel 33

基板核心層211之該上表面213與該下表面2丨4之局部 區域’以社封4些a日片3 i 〇以及該些銲線3 2 q。在封膠 後，請參閱帛5D圖所示，將複數個銲球34〇設置於該 基板核心& 2U之該下“ 214, α供對外接合至一印 刷電路板（圖中未繪出）。最後，請參閱第5Ε圖所示， 利用-切割…50切穿該封膠體33〇與該晶片載體 21〇,便可獲得複數個半導體封裝構造。再如第5ε圖所 示’在切割時，該加勁件212會一同被切除，故並不會 改變最終之半導體封裝結構。 因此，本發明之形成曰 成黏曰日層之方法不僅可選用低材 12 1353642 料成本與可低成本印刷方法形成之液態膠體 谬體作為黏晶材料2 3 0，運用於黏晶強化之晶 降低製造成本與提高產品可靠度，亦可抑制該 210之勉曲以避免因翹曲所造成之傳輸與基 題’以利於後續半導體封裝製程，同時提高半 構造之產能與穩定性。此外，另可避免該黏晶 之溢流’使所製成之半導體封裝構造在該些銲 合的部位不會有不良溢膠，以確保品質之可靠 以上所述，僅是本發明的較佳實施例而已 本發明作任何形式上的限制，本發明技術方案 所附申請專利範圍為準。任何熟悉本專業的技 利用上述揭示的技術内容作出些許更動或修 變化的等效實施例，但凡是未脫離本發明技術 谷，依據本發明的技術實質對以上實施例所作 單修改、等同變化與修飾，均仍屬於本發明技 範圍内。 【圖式簡單說明】 第1圖：習知半導體封裝之載面示意圖。 第2A至2E圖：依據本發明之一具體實施例 種半導體封裝製程中形成黏晶層之方3 載體之截面示意圖。 第3圖.依據本發明之一具體實施例，在該〕 用之晶片載體之上表面示意圖。 第4圓·依據本發明之一具體實施例，在該> 或夥裯態 片載體來 晶片戴體 板定位問 導體封裝 材料23 0 線3 20接 度。 ，並非對 範圍當依 術人員可 都為專同 方案的内 的任何簡 術方案的 ，續'示一 中一晶片 法中所使 法中所使 13 1353642 用之非平面鋼板之非平面壓 第5A至5E圖：依據本發明之一具 用之半導體封裝製程之該 圖。 貼面示意圖。 體實施例，該方法運 I片載體之截面示意The upper surface 213 of the substrate core layer 211 and the partial region ′ of the lower surface 2丨4 are used to seal the four a-day sheets 3 i 〇 and the bonding wires 3 2 q. After the encapsulation, please refer to the 帛5D figure, a plurality of solder balls 34 〇 are disposed under the substrate core & 2U, 214, α is externally bonded to a printed circuit board (not shown) Finally, referring to Fig. 5, a plurality of semiconductor package structures can be obtained by cutting through the encapsulant 33〇 and the wafer carrier 21〇 by using - cutting ... 50. As shown in Fig. 5 ε, The stiffener 212 will be removed together, so that the final semiconductor package structure will not be changed. Therefore, the method of forming the adhesive layer of the present invention can not only select low material 12 1353642 material cost and low cost printing method. The formed liquid colloidal cadmium is used as the viscous material 203, and the crystal used for the viscous crystal strengthening reduces the manufacturing cost and improves the reliability of the product, and can also suppress the distortion of the 210 to avoid the transmission and the base problem caused by the warpage. 'In order to facilitate the subsequent semiconductor packaging process, while increasing the productivity and stability of the semi-structure. In addition, the overflow of the adhesion crystal can be avoided, so that the fabricated semiconductor package structure does not have a defective overflow in the soldered portions. Glue to The invention is based on the preferred embodiment of the present invention and is not limited to any form of the present invention. The technical scope of the present invention is subject to the patent application. Any technique familiar to the art utilizes the above disclosed technology. The present invention is not limited to the embodiment of the present invention, and it is still within the scope of the present invention to make a single modification, equivalent change, and modification to the above embodiments in accordance with the technical spirit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a carrier surface of a conventional semiconductor package. Figs. 2A to 2E are schematic cross-sectional views showing a side of a carrier 3 in which a crystal layer is formed in a semiconductor package process according to an embodiment of the present invention. Fig. 3 is a schematic view showing the surface of the wafer carrier in accordance with an embodiment of the present invention. The fourth circle is according to an embodiment of the present invention, in which the wafer is mounted on the wafer carrier. Wearing a body plate positioning conductor packaging material 23 0 line 3 20 degrees., is not a range of simple surgery within the scope of the program can be any special program The non-planar pressure of the non-planar steel sheet used in the method of the method of the present invention is shown in Figures 5A to 5E for the non-planar steel sheet used in the method of the present invention: the figure of the semiconductor packaging process according to one of the present invention. Schematic diagram of a body embodiment

【主要元件符號說明： ] 100 半導體封裝構造 110 基板 111 基板核心層 113 上表 面 114 下表面 116 接指 117 球墊 120 晶片 121 銲墊 140 銲線 150 封膠體 210 晶片 載體 211 基板核心層 213 上表 面 214 下表面 216 周邊 區 217 下防焊層 220 非平 板印刷模板 221 非平 坦壓貼面 222 周邊 223 印刷 開孔 230 黏晶封料 3 10 晶片 311 銲墊 320 銲線 330 封膠體 340 銲球 350 切割刀具 112下防焊層 11 5打線槽孔 13 0黏晶膠帶 160銲球 212加勁件 2 1 5單元黏晶區 21 8打線槽孔 240刮刀 14[Main component symbol description:] 100 Semiconductor package structure 110 Substrate 111 Substrate core layer 113 Upper surface 114 Lower surface 116 Finger 117 Ball pad 120 Wafer 121 Pad 140 Bond wire 150 Sealant 210 Wafer carrier 211 Substrate core layer 213 Upper surface 214 Lower surface 216 Peripheral area 217 Lower solder mask 220 Non-lithographic template 221 Non-flat pressing surface 222 Peripheral 223 Printing opening 230 Adhesive sealing material 3 10 Wafer 311 Solder pad 320 Bonding wire 330 Sealing body 340 Solder ball 350 Cutting Tool 112 under solder mask 11 5 wire slot hole 13 0 adhesive tape 160 solder ball 212 stiffener 2 1 5 unit die bond area 21 8 wire slot hole 240 scraper 14

Claims (1)

1353642 j一一—一----- |α·年〜月《γ正本I 十、申請專利範圍： 1、一種半導體封裝製程中形成黏晶層之方法，包含 提供一晶片載體，係包含一基板核心層與—加 动件，該 基板核心層之一上表面包含有複數個單元黏晶區以及 -圍繞該些單元黏晶區之周邊區，其中該加勁件係局 部形成於該基板核心層之該上表面，以覆蓋該周邊 區，但顯露該些單元黏晶區，其中該晶片載體係為一1353642 j一一一一----- |α·年至月《γ正本 I X. Patent application scope: 1. A method for forming a crystal layer in a semiconductor packaging process, comprising providing a wafer carrier, comprising one a substrate core layer and an urging member, wherein an upper surface of the substrate core layer comprises a plurality of unit die-bonding regions and a peripheral region surrounding the unit die-bonding regions, wherein the stiffening member is partially formed on the substrate core layer The upper surface covers the peripheral region, but exposes the unit die-bonding regions, wherein the wafer carrier is a 印刷電路板並具有-下防焊層，該下防焊層係mi 蓋該基板核心層之一下表面，該下防焊層之覆蓋面積 係大於該加勁件之覆蓋面積，其中該加勁件係為一加 厚型圖案化防焊層，而不覆蓋該基板核心層之該些單 兀黏晶區並且該加勁件之厚度係大於該下防焊層； 提供一非平板印刷模板，係具有一非平坦壓貼面g，其中 該非平坦壓貼面之周邊係為厚度減少，用以補償該加The printed circuit board has a lower solder mask layer, and the lower solder resist layer covers a lower surface of the core layer of the substrate, and the coverage area of the lower solder resist layer is larger than the coverage area of the stiffener, wherein the stiffener is a thickened patterned solder mask layer without covering the single germanium die bond regions of the substrate core layer and the thickness of the stiffener is greater than the lower solder resist layer; providing a non-lithographic template having a non- a flat pressing surface g, wherein the periphery of the uneven pressing surface is reduced in thickness to compensate for the addition 勁件之厚度，該非平板印刷模板更具有複數個印 孔； 壓附該非平板印刷模板至該晶片載體’以使該些印刷開 孔顯露該基板核心層之該些單元黏晶區，並且該非平 板印刷模板係為無塌陷地貼觸至該基板核心層與該加 勁件；以及 通過該非平板印刷模板之該些印刷㈤孔，印㈣一黏晶材 料至該基板核心層之該些單元黏晶區。 2如申請專利範圍第1項所述之半導體封裝製程令形成 黏曰s層之方法，其中該加勁件係為環形框。 15 1353642 3、 4、 如申明專利範圍第1項料之半導體封裝製程中形成 讀曰曰層之方法，另包含一預烘烤步驟以使該黏晶材 料部分固化為-在該基板核心層上之均厚黏晶層。 如申請專利範圍第i項所述之半導體封裝製程中形成 =層之方法，其中該晶片載體係為一基板條，且在 單几黏晶區内開設至少一打線槽孔，並在印刷時 “非平板印刷模板係完全封閉該些打線槽孔。The non-lithographic printing template further has a plurality of printing holes; the non-lithographic printing template is affixed to the wafer carrier' such that the printing openings expose the unit die-bonding regions of the substrate core layer, and the non-plate The printing template is attached to the core layer of the substrate and the stiffener without collapse; and the printed (5) holes of the non-lithographic template are printed (4) a die-bonding material to the unit die-bonding regions of the core layer of the substrate . [2] The method of forming a layer of adhesive s by a semiconductor package process as described in claim 1 wherein the stiffener is a ring frame. 15 1353642 3, 4, the method of forming a read layer in the semiconductor packaging process of claim 1 of the patent scope, further comprising a pre-baking step to partially cure the die-bonding material - on the core layer of the substrate The average thickness of the sticky layer. The method of forming a layer in a semiconductor packaging process as described in claim i, wherein the wafer carrier is a substrate strip, and at least one wire slot is opened in a single die bond region, and is printed. The non-lithographic template completely closes the wire slot holes. 1616
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