TWI689023B - Stacked semiconductor package - Google Patents

Abstract

The present invention relates to a stacked semiconductor package and has a substrate, a first chip, a second chip and an adhesive layer. The substrate has a chip area and multiple projections formed around the chip area. Multiple pads are formed on the chip area. The first chip is mounted on the chip area and electrically connected to the pads. The adhesive layer encapsulates the first chip and the projections. The second chip is mounted on the adhesive layer and a size of the second chip is larger than that of the first chip, so the second chip corresponds the first chip and the projections. Since the projections formed around the chip area, a top surface of the adhesive layer is flatter.

Description

Stacked semiconductor packaging structure

The invention relates to a stacked semiconductor packaging structure, in particular to a stacked semiconductor packaging structure using an improved circuit substrate.

In the semiconductor packaging technology, a stacked semiconductor packaging structure may be used to package multiple chips in a stacked manner to reduce the lateral size of the package.

Please refer to FIGS. 8A and 8B, a stacked semiconductor package structure includes a circuit substrate 50, a first chip 60, a encapsulant layer 70 (Film-On-Die adhesive; FOD) and a second chip 80 Wherein the first chip 60 is electrically connected to the circuit substrate 50, and then the encapsulant layer 70 attached with the second chip 80 is heated and then flat-pressed and bonded to the circuit substrate 50 to cover the first chip 60 As shown in FIG. 8B, a stacked semiconductor package structure is constructed accordingly.

As can be seen from FIG. 8B, in order to completely cover the first wafer 60, the above encapsulant layer 70 is pre-heated in a viscous state and then flatly attached to the circuit substrate 50; however, because the first wafer 60 has a certain thickness, the package During the flat lamination process of the gel layer 70, part of the colloid corresponding to the first wafer 60 will be squeezed upwards and outwards. Since the encapsulant layer 70 is viscous, the encapsulant layer 70 is pressed down evenly. During the flat lamination process, the part of the colloid that is being pushed out cannot be evenly pushed to the entire encapsulant layer 70, which causes the part of the encapsulant layer 70 corresponding to the position of the first wafer 50 to arch upward, as shown in FIG. 9A and FIG. As shown in FIG. 9B, the height difference between the height corresponding to the position of the first wafer 60 in the middle of the encapsulant layer 70 and the surrounding height is large (in this example, there are 9 levels of height differences H1~H9), making the subsequent second wafer 80 unable to Stacked on a flat encapsulant layer 70, After the stacked semiconductor package structure is completed, it is prone to delamination, so further improvement is necessary.

In view of the fact that the stacked semiconductor package structure described above is prone to delamination due to the use of a peri-plastic layer, the main object of the present invention is to provide a stacked semiconductor package structure and its circuit substrate to improve delamination defects.

The main technical means used to achieve the above purpose is that the stacked semiconductor package structure includes: a circuit substrate, an insulating protective layer is formed on the first surface thereof, and includes a chip area and a plurality of locations around the chip area And protruding from the insulating protection layer; wherein the chip area contains a plurality of contacts; a first chip is disposed in the chip area of the circuit substrate and electrically connected to the contacts; A encapsulant layer, which is attached and covered with the protrusions and the first chip on the insulating protective layer of the circuit substrate; and a second chip, which is arranged on the encapsulant layer; wherein the second The size of the wafer is larger than the size of the first wafer, and the second wafer corresponds downward to the protrusions.

As can be seen from the above description, the present invention mainly forms a plurality of protrusions outside the wafer area of the circuit substrate. When a viscous encapsulant layer is applied to the insulating protective layer on the first surface after heating, due to the plurality of protrusions The device is located at the periphery of the wafer area, and the colloid of the encapsulant layer can be evenly squeezed out to reduce the height difference from the wafer area to the surrounding area, so that the second wafer is arranged on the encapsulant layer more evenly.

1, 1a, 1b, 1c, 1d: stacked semiconductor packaging structure

10: circuit board

101: first surface

102: second surface

103: insulating protective layer

11: Wafer area

12, 12a, 12b: convex parts

13: Contact

14: Tin ball

15: Line

20: First chip

201: viscose

21: Pad

22: connection line

30: encapsulated gel layer

40: Second chip

S1: first lateral zone

S2: Second outer zone

50: circuit board

60: First chip

70: encapsulated gel layer

80: second chip

FIG. 1 is a side cross-sectional view of a stacked semiconductor package structure of the present invention.

2A and 2B are side cross-sectional views of semi-finished products at different steps in the stacked packaging process of the present invention.

FIG. 3A is a top plan view of the first embodiment of the stacked packaging process of the present invention.

Fig. 3B: A graph of the change in height of the cladding gel layer of Fig. 3B.

FIG. 4A is a top plan view of a second embodiment of the stacked packaging process of the present invention.

Fig. 4B: A graph of the change in height of the cladding layer of Fig. 4A.

FIG. 5A is a top plan view of a third embodiment of the stacked packaging process of the present invention.

Fig. 5B: A graph of the change in height of the cladding gel layer of Fig. 5A.

6A: It is a top plan view of the fourth embodiment of the stacked packaging process of the present invention.

Fig. 6B: A graph of the change in height of the cladding gel layer of Fig. 6A.

7A: It is a top plan view of a fifth embodiment of the stacked packaging process of the present invention.

Fig. 7B: A graph of the change in height of the cladding gel layer of Fig. 7A.

8A and 8B are side cross-sectional views of semi-finished products at different steps in the existing stacked packaging process.

Figure 9A: a top plan view of Figure 8B.

FIG. 9B: A graph of the change in the height of the peritectic layer of FIG. 9A.

The present invention is directed to the improvement of the stacked semiconductor package structure. The technical content of this case will be described in detail in conjunction with a number of different embodiments and drawings.

First, please refer to FIG. 1, an embodiment of the stacked semiconductor package structure 1 of the present invention includes a circuit substrate 10, a first chip 20, a encapsulant layer 30 and a second chip 40.

The circuit board 10 includes a first surface 101 and a third surface opposite to the first surface 101 Two surfaces 102; please refer to FIG. 3A, the first surface 101 includes a wafer area 11 and a plurality of protrusions 12, and the second surface 102 is formed with a plurality of solder balls 14 or bumps. A circuit 15 is formed in the circuit substrate 10, the wafer area 11 on the first surface 101 includes a plurality of contacts 13, and a plurality of protrusions 12 are located on the periphery of the wafer area 11 and protrude from the first surface 101, the circuit 15 is a solder ball 14 or bump for electrically connecting the contact 13 on the first surface 101 and the second surface 102. In this embodiment, the circuit substrate 10 is a glass fiber board (FR4 board or FR5 board), and the first surface 101 and the second surface 102 of the glass fiber board are coated with an insulating protective layer 103 (such as green paint), so the convex parts 12 is protruding from the insulating protective layer 103 on the first surface 101, but the insulating protective layer 103 does not cover the contact 13 on the first surface 101 and the solder balls 14 or bumps on the second surface 102, that is, the solder balls 14 Or the bumps protrude from the insulating protective layer 103 on the second surface 102. Preferably, the convex member 12 is made of an insulating material, such as green paint or resin; because the convex member 12 is protruded from the insulating protective layer 103, the convex member 12 and the insulating protective layer can be made of the same material, but neither is limit.

The above-mentioned first chip 20 is disposed in the chip area 11 of the circuit substrate 10 and is electrically connected to the contact 13; in this embodiment, as shown in FIG. 2A, the first chip 20 is fixed to the circuit substrate 10 through the adhesive 201 On the insulating protective layer 103, and the plurality of pads 21 of the first chip 20 face upward, and one end of the connecting wire 22 is connected to the pad 21 and the other end is connected to the contact 13 by a wire bonding process, so that the first chip 20 and The circuit board 10 is electrically connected.

The second wafer 40 is disposed on the encapsulant layer 30, and the encapsulant layer 30 and the second wafer 40 thereon are evenly pressed and attached to the insulating protective layer 103 on the first surface 101 of the circuit substrate 10, Since the thickness of the encapsulant layer 30 is greater than the heights of the first wafer 20, the convex member 12 and the connecting wire 22, the first wafer 20, the convex member 12 and the connecting wire 22 can be covered therein. In this embodiment, the encapsulant layer 30 is a double-sided adhesive tape (Die-Attach Film; DAF), which can be sticky after heating, as shown in FIG. 2B, so it is bonded to the circuit substrate 10 after heating The insulating protective layer 103 of the first surface 101.

As shown in FIG. 2B, the second wafer 40 is stacked on the first wafer 20 through the encapsulant layer 30, and the size of the second wafer 40 is larger than the size of the first wafer 20, so that the second wafer 40 corresponds to The first wafer 20, the connection line 22, and the protrusions 12. That is, the size range of the second wafer 40 can cover the first wafer 20, the connection line 22, and the protrusion 12.

There are a plurality of protrusions 12 on the circuit substrate 10. When the encapsulant layer 30 can be evenly pressed onto the first surface 101 of the circuit substrate 10, since the protrusions 12 are located on the periphery of the wafer area 11, the colloid of the encapsulant layer 30 Can be evenly squeezed out, so that the height drop of the encapsulant layer 30 from the corresponding circuit substrate 10 located in the middle wafer area 11 to its peripheral area presents a slowing down phenomenon; furthermore, this embodiment has a large number of columnar convex pieces The large number of spaced channels between 12 also helps to reduce the generation of air bubbles in the encapsulated gel layer 30 after bonding.

Please refer to FIG. 3A, which is a top plan view of the first embodiment of the stacked semiconductor package structure 1 of the present invention. In this embodiment, each convex element 12 of the circuit substrate 10 is columnar, and a plurality of convex element matrix Are arranged on the periphery of the wafer area 11; in this embodiment, a plurality of protrusions 12 are arranged on the periphery of the wafer area 11. As shown in FIG. 3B, it is a height distribution diagram corresponding to the cladding layer 30 of FIG. 3A. Compared with FIG. 9B, the height difference between adjacent sections H1/H2, H2/H3, H3/H4, H4/H5, H5 /H6, H6/H7, H7/H8, H8/H9 interval becomes wider, and the range of the minimum height difference H9 is significantly reduced, with the help of FIG. 1, the encapsulant layer 30 representing the stacked semiconductor packaging structure of the present invention is The height difference from the corresponding wafer area 11 to its peripheral area has been reduced, so that the second wafer 40 can be arranged on the encapsulant layer 30 relatively flatly.

Please refer to FIG. 4A, which is a top plan view of the second embodiment of the stacked semiconductor package structure 1a of the present invention. In this embodiment, each of the protrusions 12a on the circuit board 10 is in a sheet shape, and the protrusions 12a are arranged parallel to each other outside the wafer area 11; in this embodiment, a plurality of sheet-shaped protrusions 12a are in parallel Arranged around the periphery of the wafer area 11; the length of each of the convex parts 12a located outside the wafer area 11 relative to the first outer side area S1 is shorter than that of the convex pieces located outside the wafer area 11 relative to the second outer side area S2 The length of 12a is long, and the number of protrusions 12a of each second outer area S2 located outside the wafer area 11 is larger than the number of protrusions 12a of each first outer area S1 located outside the wafer area 11, and is located in each The convex parts 12a of the two outer side regions S2 are arranged side by side in double rows. As shown in FIGS. 1 and 4B, it is a height distribution diagram corresponding to the cladding layer 30 of FIG. 4A. Compared with FIG. 9B, the height difference between adjacent sections is H1/H2, H2/H3, H3/H4, H4/ H5, H5/H6, H6/H7, H7/H8, H8/H9 interval Also widened, and the range of the minimum height difference H9 is also significantly reduced, which means that the height difference of the encapsulant layer 30 from the corresponding wafer area 11 to its peripheral area has been reduced, and the second wafer 40 can be arranged more flatly on the encapsulated crystal The glue layer 30.

Please refer to FIG. 5A, which is a third embodiment of the stacked semiconductor package structure 1b of the present invention, which is substantially the same as the second embodiment. However, in this embodiment, the protrusions 12a located in each second outer region S2 are In three rows side by side. As shown in FIG. 5B, it is a height distribution diagram corresponding to the cladding layer 30 of FIG. 5A. Compared with FIG. 9B, the height difference between adjacent sections H1/H2, H2/H3, H3/H4, H4/H5, H5 /H6, H6/H7, H7/H8, H8/H9 interval is also widened, and the range of the minimum height difference H9 is also significantly reduced, indicating that the height difference of the encapsulant layer 30 from the corresponding wafer area 11 to its peripheral area has Slowly, the second wafer 40 can be arranged on the encapsulant layer 30 relatively flat, as shown in FIG. 1.

Please refer to FIG. 6A, which is a fourth embodiment of the stacked semiconductor package structure 1c of the present invention. In this embodiment, each of the protrusions 12b on the circuit substrate 10 is block-shaped. In this embodiment, the length of each of the protrusions 12b located outside the wafer area 11 relative to the first outer area S1 is shorter than the length of the protrusions 12b located outside the wafer area 11 relative to the second outer area S2, and The number of protrusions 12b located in each second outer area S2 is the same as the number of protrusions 12b located in each first outer area S1. As shown in FIG. 6B, it is a height distribution diagram corresponding to the cladding layer 30 of FIG. 6A. Compared with FIG. 9B, the height difference between adjacent sections H1/H2, H2/H3, H3/H4, H4/H5, H5 /H6, H6/H7, H7/H8, H8/H9 interval is also widened, and the range of the minimum height difference H9 is also significantly reduced, indicating that the height difference of the encapsulant layer 30 from the corresponding wafer area 11 to its peripheral area has Slowly, the second wafer 40 can be arranged on the encapsulant layer 30 relatively flat, as shown in FIG. 1.

Please refer to FIG. 7A, which is a fifth embodiment of the stacked semiconductor package structure 1d of the present invention, which is substantially the same as the fourth embodiment. However, in this embodiment, only two second outer regions S2 are provided with a piece Convex part 12b. As shown in FIG. 7B, it is a height distribution diagram corresponding to FIG. 7A cladding layer 30, and Compared with Fig. 9B, the height differences between adjacent sections H1/H2, H2/H3, H3/H4, H4/H5, H5/H6, H6/H7, H7/H8, H8/H9 are also widened, and the minimum height The range of the difference H9 is also significantly reduced, which means that the height difference of the encapsulant layer 30 from the corresponding wafer area 11 to its peripheral area has been reduced, and the second wafer 40 can be arranged on the encapsulant layer 30 relatively flat, as shown in FIG. 1 shown.

To sum up, the present invention mainly forms a plurality of convex parts outside the wafer area on the first surface of the circuit substrate. When the viscous encapsulant layer after heating is flat on the first surface, corresponding to the position of each convex part Part of the colloid is also pushed outwards and upwards to reduce the height difference from the wafer area to the surrounding area, so that the second wafer is arranged flat on the encapsulant layer, eliminating the delamination or the existence of bubbles after packaging.

The above is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art, Within the scope of not departing from the technical solution of the present invention, when the technical contents disclosed above can be used to make some modifications or modifications to equivalent embodiments of equivalent changes, but any content that does not depart from the technical solution of the present invention, based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

1: Stacked semiconductor packaging structure

10: circuit board

101: first surface

102: second surface

103: insulating protective layer

12: convex

13: Contact

14: Tin ball

15: Line

20: First chip

201: viscose

21: Pad

22: connection line

30: encapsulated gel layer

40: Second chip

Claims (10)

A stacked semiconductor packaging structure includes: a circuit substrate having an insulating protective layer formed on a first surface thereof, and including a chip area and a plurality of protrusions located around the chip area and protruding from the insulating protective layer; The chip area contains a plurality of contacts; a first chip is provided in the chip area of the circuit substrate and is electrically connected to the contacts; a crystal encapsulant layer is attached and covered in The protrusion and the first chip on the insulating protective layer of the circuit substrate; and a second chip, which are disposed on the encapsulant layer; wherein the size of the second chip is larger than the size of the first chip, and The second wafer corresponds downward to the protrusions. The stacked semiconductor package structure according to claim 1, wherein each of the convex member ties is columnar, and the convex elements are arranged in a matrix outside the chip area. The stacked semiconductor package structure according to claim 1, wherein each of the convex pieces is in a sheet shape, and the convex pieces are arranged parallel to each other outside the chip area. The stacked semiconductor package structure as claimed in claim 3, wherein the length of each of the protrusions located outside the wafer area relative to the first outer side area is two opposite to the second outside area outside the wafer area The length of each of the protruding members is long; the number of the protruding members of each of the second outer regions located outside the wafer region is larger than the number of the protruding members of each of the first outer regions located outside the wafer region . The stacked semiconductor package structure according to claim 1, wherein: each of the protrusions located outside the wafer area and the first outer area is in a block shape; and the two located outside the wafer area are opposite the second Each convex part of the outer side region is in a block shape; the length of the convex part located in each of the first outer side regions is shorter than the length of the convex part located in each of the second outer side regions. The stacked semiconductor package structure according to claim 5, wherein the number of the protrusions located in each second outer area of the wafer area and the number of protrusions located in each first outer area of the wafer area with. According to the stacked semiconductor package structure of claim 1, each of the protruding members is in a block shape, and is arranged in two opposite outer second regions outside the chip region. The stacked semiconductor package structure according to any one of claims 1 to 7, wherein the circuit substrate further includes: a second surface on which a protective insulating layer is formed and protrudes more than the protective insulating layer A plurality of solder balls or bumps; and a plurality of circuits are formed in the circuit substrate to electrically connect the contacts and the solder balls or bumps. The stacked semiconductor package structure according to any one of claims 1 to 7, wherein the material of each protrusion is the same as the protective insulating layer. The stacked semiconductor package structure according to any one of claims 1 to 7, wherein the material of each of the protrusions is resin.

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