I34S826' ' 'c ,、vA ^ 、 九、發明說明： 【發明所屬之技術領域】 本發明係有關於可運用於多晶片堆疊之間隔體形成 技術，特別係有關於一種可降低晶片間隔層厚度之多晶 片堆疊方法及其結構。 【先前技術】 為了提昇單一積體電路產品之性能與容量，以符合 電子產品小型化、大容量與高速化之趨勢，一般而言是 I 將積體電路產品以多晶片立體堆疊（multi-chip 3D stacking)的形式呈現，此種積體電路產品亦可縮減整體 體積並可提昇電性功能。然而多晶片堆疊過程中應在晶 片與晶片之間介設一間隔體（spacer)，以避免上方堆疊 晶片壓觸至位其下方之銲線。但考慮到在間隔體表面之 黏著層厚度，故整體的多晶片堆疊厚度無法降低。 請參閱第1圖所示，一種習知的多晶片堆疊結構1 00 • 主要包含一第一晶片110、一第二晶片160、一間隔體 120以及一基板130。其中該第一晶片110與該第二晶 片160係設置於該基板130之上方。該間隔體120係介 設於該第一晶片1 1 0與該第二晶片1 60之間，並且在該 間隔體120之下表面更形成有一第一黏著層151與一第 二黏著層 1 5 2，以黏著該第一晶片1 1 0與該第二晶片 160。 依其製造順序，當該第一晶片11 0設置之後，到用 打線形成之複數個第一銲線1 4 1電性連接該第一晶片 6 1-345826'I34S826' 'c,, vA ^, IX, invention: [Technical Field] The present invention relates to a spacer formation technology that can be applied to multi-wafer stacking, and more particularly to a method for reducing the thickness of a wafer spacer The multi-wafer stacking method and its structure. [Prior Art] In order to improve the performance and capacity of a single integrated circuit product, in order to meet the trend of miniaturization, large capacity, and high speed of electronic products, it is generally a multi-chip three-dimensional stacking of integrated circuit products (multi-chip). 3D stacking), this integrated circuit product can also reduce the overall size and enhance electrical functions. However, a spacer should be placed between the wafer and the wafer during the multi-wafer stacking process to prevent the upper stacked wafer from being pressed against the bonding wires below it. However, considering the thickness of the adhesive layer on the surface of the spacer, the overall thickness of the multi-wafer stack cannot be lowered. Referring to FIG. 1, a conventional multi-wafer stack structure 100 includes a first wafer 110, a second wafer 160, a spacer 120, and a substrate 130. The first wafer 110 and the second wafer 160 are disposed above the substrate 130. The spacer 120 is disposed between the first wafer 110 and the second wafer 160, and a first adhesive layer 151 and a second adhesive layer 15 are formed on the lower surface of the spacer 120. 2, to adhere the first wafer 110 and the second wafer 160. In the manufacturing order, after the first wafer 110 is disposed, the plurality of first bonding wires 144 formed by wire bonding are electrically connected to the first wafer 6 1-345826'
V * 110之複數個第一銲墊112至該基板130, 隔體120,該第一黏著層151可預先形成於該 之下表面以黏者該第一晶片110之主動面1 間隔體1 2 0係可為一膠片、一虛晶片或一金 該第二晶片1 60係設置於該間隔體1 2〇 黏著層152可預先形成於該第二晶片16〇之 是該間隔體1 20之上表面以黏著該第二晶片 隔體120。該間隔體120提供一可容許該此笛 ~ 弧高，之高度，用以避免該第二晶片1 6 0之背 碰觸至該些第一銲線1 4 1。再利用打線技術 第二銲線1 42，以電性連接該第二晶片1 6〇 二銲墊162至該基板130。依據目前習知的 疊結構1 00之製程中，該間隔體1 20之黏貼 必要的步驟’並且在該間隔體120表面（上 面）之黏著層1 5 2或1 5 1會增加晶片堆叠間 • 減少該間隔體1 20之厚度則會導致該間隔體 黏著層1 5 1、1 5 2的比值變小，維持晶片堆 力變差’導致多晶片堆疊高度無法準確控制 後續打線與封膠製程的參數設定及最終產品 【發明内容】 本發明之主要目的係在於提供一種多晶 及其結構’可以郎省間隔體黏貼之步驟並維 晶強度下省去習知黏著膠在間隔體的表面厚 低多晶片堆疊厚度。故具有簡化多晶片堆叠 再設置該間 間隔體120 11。通常該 屬片等等。 上。該第二 背面161或 160且該間 一銲線1 4 1 面161直接 形成複數個 之複數個第 該多晶片堆 設置乃為·一 表面或下表 隙。當直接 1 2 0相對於 疊間隙的能 ’這會影響 ’品質。 片堆疊方法 持在足夠黏 度’進而降 之製作流程 7 1-345826 與降低製造成本之功效，更具有提高晶圓切割良率之功 效0 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明揭示一種多晶片堆疊方法，首 先，提供一半導體晶圓，該半導體晶圓係一體包含有複 數個第一晶片以及複數個在該些第一晶片之間之切割 道，每一第一晶片係具有一主動面以及複數個在該主動 面上之銲墊。接著，形成一層圖案化保護層於該些第一 晶片之該主動面上，該圖案化保護層係包含有複數個防 碎片護墊，其係位於該些切割道之交會區並佔據該些第 一晶片之主動面角隅。再沿著該些切割道切割該半導體 晶圓與該些防碎片護墊，以使該些第一晶片分離並使每 一防碎片護墊形成為複數個位於該些第一晶片之主動 面角隅上之晶圓級角隅間隔體。接著，設置已形成該些 晶圓級角隅間隔體之該第一晶片於一基板。電性連接該 第一晶片與該基板。在電性連接後，形成一黏著膠於該 第一晶片之該主動面。之後，設置一第二晶片於該第一 晶片之該主動面上，該第二晶片之一背面係支撐於該些 晶圓級角隅間隔體上並接觸該黏著膠。最後，固化該黏 著膠，以黏著已形成該些晶圓級角隅間隔體之該第一晶 片與該第二晶片，該黏著膠於固化後之厚度係由該些晶 圓級角隅間隔體之高度所定義。另揭示依前述方法所製 成之多晶片堆疊結構。 本發明的目的及解決其技術問題還可採用以下技術 8 1-345826 蝽 • 措施進一步實現。 在前述的多晶片堆疊方法中，該黏著膠係可為液態塗 膠。 前述的多晶片堆疊方法中，該黏著膠係可覆蓋該第一 晶片之該主動面之中央與側邊。 前述的多晶片堆疊方法中，該黏著膠係可覆蓋至該第一 晶片之該些銲墊。 前述的多晶片堆疊方法中1在該些晶圓級角隅間隔體 ^ 與該第二晶片之背面之間可為無黏性。 前述的多晶片堆疊方法中，上述電性連接步驟中，可 形成有複數個銲線，該些銲線之一端係連接至該第一晶 片之該些銲墊。 ' 前述的多晶片堆疊方法中，該些銲墊係可排列於該第 一晶片之主動面之側邊。 前述的多晶片堆疊方法中，該第二晶片係可實質相同 φ 於已形成該些晶圓級角隅間隔體之該晶片，而設有複數 個晶圓級角隅間隔體。 【實施方式】 依據本發明之第一具體實施例，揭示一種多晶片堆 疊方法及其結構。第2至4圖以及第5Α至5G圖係有 關於該多晶片堆疊方法。第6圖係有關於該多晶片堆疊 結構。第7圖係繪示該多晶片堆疊方法中形成一黏著膠 之立體示意圖。 首先，請參閱第2圖所示，提供一半導體晶圓10, 9 1.345826 該半導體晶圓1 〇係一體包含有複數個第—晶片21 〇以 及複數個在該些第一晶片210之間之切割道"，兮此 切割道1 1係用以定義出該些第一晶片2 i 〇。請再參閱 第2圖配合第5A圖所示，每一第一晶片21〇係具有一 第一主動面211與一相對之第一背面212,其中該第一 主動面211係形成有積體電路（圖中未繪出）與複數個第 一銲墊2 1 3。在本實施例中，該些第一銲墊2丨3係可排 列於該第一晶片210之該第一主動面211之側邊，如兩 側邊或四周側邊。 接著’請參閱第3及5A圖所示，形成一層圖案化保 護層於該些第一晶片210之該第一主動面211上，該圖 案化保護層係包含有複數個防碎片護墊2〇，其係位於 該些切割道1 1之交會區並佔據該些第一晶片2 i 〇之第 一主動面211之四個角隅。該些防碎片護墊2〇係可具 有電絕緣性並尚出於該些第一銲塾2 1 3，具有保護該些 第一晶片2 1 0在該第一主動面2 i丨上晶圓保護層（wafer passivation layer，圖中未繪出）之功效，用以避免晶圓 切割時發生碎片。通常該些防碎片護墊2〇之材料係為 樹脂，如固化、半固化之晶片黏貼膠材（Die Anach Material，DAM)。依形狀之不同，該些防碎片護墊2〇 之長寬或直徑可大於該些切割道1 1之寬度。 請參閱第5 A及5 B圖所示，利用一切割刀具（圖中未 繪出）切割該半導體晶圓1 〇 ’其切割路徑係沿著該半導 體晶圓1 0之該些切割道1 1進行，以切割該半導體晶圓 1345826 ·% 10與該些防碎片護墊2〇，q 並使每-防碎片護塾2G形/該些第—晶片2 1 0分離 片川之第-主動面21^為複數個位於該些第-晶 ^如第4圖所示）。較佳但^上^晶圓級角隅間隔體 該些防碎片護墊20可加以*入限疋地’在切割之前’ 堆疊間隔之維持功效。在切：：：化可以：效發揮晶片 所示形成有該些晶圓級角隅：仔到如第4圖a plurality of first pads 112 of V*110 to the substrate 130, the spacers 120, the first adhesive layer 151 may be formed on the lower surface to adhere to the active surface 1 of the first wafer 110. 0 can be a film, a virtual wafer or a gold. The second wafer 160 is disposed on the spacer. The adhesive layer 152 can be formed on the second wafer 16 and above the spacer 110. The surface is adhered to the second wafer spacer 120. The spacer 120 provides a height that allows the height of the flute to avoid touching the back of the second wafer 160 to the first bonding wires 141. The second bonding wire 124 is electrically connected to the second wafer 16 〇 2 pads 162 to the substrate 130. According to the conventional process of the stacked structure 100, the necessary steps of the spacer 1 20 are adhered and the adhesive layer 1 5 2 or 1 5 1 on the surface (above) of the spacer 120 increases the wafer stacking interval. Reducing the thickness of the spacer 1 20 causes the ratio of the spacer adhesion layer 1 5 1 , 1 5 2 to be small, and the wafer stacking force is deteriorated, which results in the multi-wafer stack height cannot accurately control the subsequent wire bonding and sealing process. Parameter setting and final product [Summary of the Invention] The main object of the present invention is to provide a polycrystalline structure and a structure thereof, which can be affixed to the process of affixing spacers and to eliminate the thickness of the conventional adhesive on the surface of the spacer. Multi-wafer stack thickness. Therefore, the simplified multi-wafer stack is provided and the spacers 120 11 are disposed. Usually the genus and so on. on. The second back surface 161 or 160 and the first bonding wire 1 4 1 surface 161 directly form a plurality of the plurality of the first multi-chip stacks to be a surface or a back surface. When direct 1 2 0 is relative to the energy of the stack gap, this will affect the quality. The chip stacking method has the effect of reducing the manufacturing cost of the manufacturing process 7 1-345826 and reducing the manufacturing cost, and has the effect of improving the wafer cutting yield. The purpose of the present invention and solving the technical problem is to adopt the following technical solutions. Realized. According to the present invention, a multi-wafer stacking method is disclosed. First, a semiconductor wafer is integrally provided. The semiconductor wafer system integrally includes a plurality of first wafers and a plurality of dicing streets between the first wafers, each first The wafer system has an active surface and a plurality of pads on the active surface. Then, a patterned protective layer is formed on the active surface of the first wafers, and the patterned protective layer includes a plurality of anti-fragment pads, which are located in the intersection of the dicing streets and occupy the first The active face angle of a wafer. Cutting the semiconductor wafer and the anti-fragmentation pads along the scribe lines to separate the first wafers and forming each of the anti-fragmentation pads into a plurality of active surface angles of the first wafers Wafer-level corner spacers. Next, the first wafer on which the wafer level corner spacers have been formed is disposed on a substrate. The first wafer and the substrate are electrically connected. After the electrical connection, an adhesive is formed on the active surface of the first wafer. Thereafter, a second wafer is disposed on the active surface of the first wafer, and one of the back surfaces of the second wafer is supported on the wafer level corner spacers and contacts the adhesive. Finally, the adhesive is cured to adhere the first wafer and the second wafer on which the wafer-level corner spacers have been formed. The thickness of the adhesive after curing is determined by the wafer-level corner spacers. The height is defined. Further disclosed is a multi-wafer stack structure formed by the foregoing method. The object of the present invention and solving the technical problems thereof can also adopt the following techniques: 8 1-345826 蝽 • Measures are further realized. In the foregoing multi-wafer stacking method, the adhesive system may be a liquid coating. In the above multi-wafer stacking method, the adhesive layer can cover the center and the side of the active surface of the first wafer. In the foregoing multi-wafer stacking method, the adhesive system can cover the pads of the first wafer. In the foregoing multi-wafer stacking method, 1 may be non-viscous between the wafer level corner spacers ^ and the back surface of the second wafer. In the above multi-wafer stacking method, in the electrical connection step, a plurality of bonding wires may be formed, and one of the bonding wires is connected to the pads of the first wafer. In the above multi-wafer stacking method, the pads may be arranged on the side of the active surface of the first wafer. In the foregoing multi-wafer stacking method, the second wafer system may be substantially the same as the wafer in which the wafer level corner spacers have been formed, and a plurality of wafer level corner spacers are provided. [Embodiment] According to a first embodiment of the present invention, a multi-wafer stacking method and structure thereof are disclosed. Figures 2 to 4 and 5th to 5G are related to the multi-wafer stacking method. Figure 6 is related to the multi-wafer stack structure. Fig. 7 is a perspective view showing the formation of an adhesive in the multi-wafer stacking method. First, as shown in FIG. 2, a semiconductor wafer 10, 9 1.345826 is provided. The semiconductor wafer 1 includes a plurality of first wafers 21 and a plurality of cuts between the first wafers 210. The track ", the scribe line 1 1 is used to define the first wafers 2 i 〇. Referring to FIG. 2 , in conjunction with FIG. 5A , each of the first wafers 21 has a first active surface 211 and an opposite first back surface 212 , wherein the first active surface 211 is formed with an integrated circuit. (not shown) and a plurality of first pads 2 1 3 . In this embodiment, the first pads 2丨3 may be arranged on the side of the first active surface 211 of the first wafer 210, such as two sides or four sides. Then, as shown in FIGS. 3 and 5A, a patterned protective layer is formed on the first active surface 211 of the first wafers 210. The patterned protective layer includes a plurality of anti-fragment pads. It is located at the intersection of the scribe lines 1 1 and occupies the four corners of the first active surface 211 of the first wafers 2 i . The anti-fragment pad 2 can be electrically insulated and still be used for the first pads 2 1 3 to protect the first wafers 2 1 0 on the first active surface 2 i The effect of a protective passivation layer (not shown) to avoid chipping during wafer dicing. Usually, the materials of the anti-fragment pad 2 are made of a resin such as a cured, semi-cured Die Anach Material (DAM). Depending on the shape, the length and width or the diameter of the anti-fragment pad 2 可 may be greater than the width of the dicing streets 1 1 . Referring to FIGS. 5A and 5B, the semiconductor wafer 1 is cut by a cutting tool (not shown). The cutting path is along the cutting streets 1 of the semiconductor wafer 10. Performing to cut the semiconductor wafer 1345826·% 10 and the anti-fragment pads 2〇, q and separate the anti-fragment guard 2G/the first wafer 2 1 0 from the first active surface 21^ is a plurality of the first-crystals as shown in Fig. 4). Preferably, the wafer level corner spacers are protected by the stacking gaps. In the cut::: can be: the effect of the wafer shown in the formation of the wafer level angle 隅: as shown in Figure 4
片一，該些晶圓級角隅間隔=;該些第—晶 J闯遐220可位於該些第一銲 墊213之兩側且不遮蓋該些第—銲墊213。 接著，請參閱第5C圖所示，設置已形成該些晶圓級 角隅間隔體220之該第一晶片210於一基板23〇。配合 參閱第7圖’該基板230係具有複數個接指231，以供 打線連接，該基板23 0係具有電性傳遞功能，依應用產 品之不同變化，該基板230可為印刷電路板、陶瓷基 板、玻璃基板或導線架《請參閱第5D及7圖所示，以 打線方式使複數個第一銲線24 1電性連接該第一晶片 210與該基板230。其中，該些第一銲線241之一端係 連接至該第一晶片210之該些第一銲墊213，該些第一 銲線241之另一端係連接至該基板230之該些接指 23 1(如第7圖所示）。 在電性連接之後，由於該第一晶片210之第一主動 面2 1 1可在晶圓階段形成有該些晶圓級角隅間隔體 220，並不需要在多晶片堆疊過程中設置間隔體。請參 閱第5E及7圖所示，形成一黏著膠250於該第一晶片 11 1-345826 w • K K ^ m • 2 1 0之該第一主動面2 1 1。該黏著膠2 5 0係 膠，如液態環氧樹脂（epoxy)。請參閱第 7 本實施例中，可利用點膠技術藉由一點膠針 黏著膠2 5 0點塗在該第一晶片2 1 0之該第一 之一中央區域。 之後，請參閱第5F及5G圖所示，設置 260於該第一晶片210之上方，其中該第二 具有一第二主動面261與一相對之第二背面 二主動面261係形成有複數個第二銲墊263 該第二晶片260與該第一晶片2 1 0係可具有 或者該第二晶片260之尺寸係可大於該第一 尺寸。對該第二晶片260施以一預定之下壓 二晶片260之該第二背面262係支撐於該些 間隔體220上並接觸該黏著膠250。該黏著 黏晶壓力之擠壓，而往外流動至該第一晶片 • 一主動面211之周邊，以覆蓋至該些第一銲 佳。在本實施例中，該黏著膠250更可密封 線241與該第一晶片210之該些第一銲墊 處，達到該些第一銲線24 1先置密封之功效 些第一銲線24 1之晶片接合端發生鬆脫（如 示）。 最後，請參閱第5G及6圖所示，固化該| 以黏著已形成該些晶圓級角隅間隔體220 片210與該第二晶片260，該黏著膠250於 可為液態塗 圖所示，在 頭3 0將該 主動面2 1 1 一第二晶片 晶片260係 262 ，該第 。較佳地， 相同尺寸， 晶片2 1 0之 力，使該第 晶圓級角隅 膠250會因 2 1 0之該第 墊2 1 3為較 該些第一銲 213之接合 ，以防止該 第5G圖所 i占著膠250， 之該第一晶 固化後之厚 12 1345826.In the first embodiment, the wafer-level corners are spaced apart; the first-layers J-220 may be located on opposite sides of the first pads 213 and do not cover the first pads 213. Next, referring to FIG. 5C, the first wafer 210 on which the wafer level corner spacers 220 have been formed is disposed on a substrate 23A. Referring to FIG. 7 , the substrate 230 has a plurality of fingers 231 for wire bonding. The substrate 230 has an electrical transmission function. The substrate 230 can be a printed circuit board or a ceramic according to different application products. The substrate, the glass substrate or the lead frame "please refer to FIGS. 5D and 7 to electrically connect the plurality of first bonding wires 24 1 to the first wafer 210 and the substrate 230 by wire bonding. One end of the first bonding wires 241 is connected to the first pads 213 of the first wafer 210, and the other ends of the first bonding wires 241 are connected to the fingers 23 of the substrate 230. 1 (as shown in Figure 7). After the electrical connection, since the first active surface 21 of the first wafer 210 can form the wafer level corner spacers 220 at the wafer stage, it is not necessary to provide spacers during the multi-wafer stacking process. . Referring to Figures 5E and 7, an adhesive 250 is formed on the first active surface 2 1 1 of the first wafer 11 1-345826 w • K K ^ m • 2 1 0. The adhesive is a glue such as a liquid epoxy resin. Referring to the seventh embodiment, the first central region of the first wafer 210 may be applied by a dispensing technique by a point of adhesive tape 2500. Then, as shown in FIGS. 5F and 5G, the 260 is disposed above the first wafer 210, wherein the second portion has a second active surface 261 and an opposite second back surface active surface 261 is formed with a plurality of The second pad 263 may have the second wafer 260 and the first wafer 210 or the second wafer 260 may be larger than the first size. The second back surface 262 of the second wafer 260 is applied to the spacers 220 and contacts the adhesive 250. The adhesive pressure is squeezed and flows outward to the periphery of the first wafer • an active surface 211 to cover the first solder. In this embodiment, the adhesive 250 can further seal the wire 241 and the first pads of the first wafer 210, and the first bonding wires 24 1 are sealed first. The wafer bonding end of 1 is loosened (as shown). Finally, as shown in FIGS. 5G and 6 , the photo-curing spacer 220 sheet 210 and the second wafer 260 are formed by adhesion, and the adhesive 250 can be liquid-painted. At the head 30, the active surface 2 1 1 - a second wafer wafer 260 is 262, the first. Preferably, the same size, the force of the wafer 2 10 causes the wafer level keratin 250 to be bonded to the first pads 213 by the second pad 2 1 3 to prevent the The 5G figure occupies the glue 250, and the thickness of the first crystal is 12 1345826.
V * 度係由該些晶圓級角隅間隔體220之高度 之，該黏著膠250於固化後之厚度係概與 隅間隔體220之高度相同。由於該黏著膠 積包含該第一晶片210之第一主動面21 緣，該些晶圓級角隅間隔體220可不需要 是殘留極少量的黏著材料，仍具有良好的 且晶片堆疊間隙（即該黏著膠2 5 0之黏著；f 晶圓級角隅間隔體220有效且準確的控制 I 因此，該些晶圓級角隅間隔體220具 影響之間隔維持功效。這是因為，該些晶 體220之上表面無黏著層，該些晶圓級角 與其表面黏著層的比值可為極大值，即使 角隅間隔體220之厚度直接減少仍能具 片堆疊間隙的能力，多晶片堆疊高度仍可 外，更可省去習知在多晶片堆疊過程中間 # 步驟，亦不會有間隔體在取放對位時不慎 問題，更由於該黏著膠2 5 0係可覆蓋該第 該第一主動面 2 1 1之中央與側邊，能加 2 1 0與該第二晶片260之間之黏晶強度與 使該第二晶片260不易位移。在該第二晶 作業時，打線機之銲針（圖中未繪出）會施 墊2 63 —向下壓力，而該第二晶片260之 自該已固化黏著膠250之支撐，故無力矩 得該第二晶片260於邊緣處產生打線崩； 所定義。換言 該些晶圓級角 2 5 0之黏著面 1之中央與邊 有黏著材料或 黏晶強度。並 P·度）已被該些 〇 有不受黏著層 圓級角隅間隔 隅間隔體220 將δ玄些晶圓級 有良好維持晶 準確控制。此 隔體黏貼設置 碰觸至銲線之 一晶片210之 強該第一晶片 打線支樓性， 片2 6 0之打線 予該些第二銲 周邊可獲得來 現象，不會使 之情況（如第 13 1345826 *» s * * ' V， ' 5 G圖所示）。 較佳地，在該些晶圓級角隅間隔體220與該第二晶 片260之第二背面262之間可為無黏性，僅需藉由該黏 著膠 250即可使該第二晶片 260黏貼至該第一晶片 2 1 0，不需在該些晶圓級角隅間隔體220與該第二晶片 2 60之第二背面262之間另設黏著層，並可達到足夠黏 著該第二晶片260之強度。 再如第6圖所示，該第二晶片260係藉由複數個第 ^ 二銲線242連接該些第二銲墊263至該基板230，以達 到該第二晶片260與該基板23 0之間之電性連接。該些 晶圓級角隅間隔體220之高度係高於該些第一銲線24 1 之打線弧高，以避免堆疊晶片時該第二晶片260壓觸該 " 些第一銲線241，又該黏著膠250已被固化可發揮與該 些晶圓級角隅間隔體220相同之打線支撐功效，能承受 該第二晶片260與該基板230打線接合時之作用力，達 φ 到防止該第二晶片260之破裂損壞。 再如第5G及6圖所示，本發明另揭示一種依前述方 法所製成之多晶片堆疊結構200。該多晶片堆疊結構 2 00主要包含該第一晶片2 1 0、該些晶圓級角隅間隔體 220、該基板230、該些第一銲線241、該黏著膠250以 及該第二晶片260。該些晶圓級角隅間隔體220係位於 該第一晶片210之第一主動面211角隅上。該基板230 係用以設置已形成該些晶圓級角隅間隔體220之該第 一晶片2 1 0。該些第一銲線24 1係電性連接該第一晶片 14 1345826 該基板230係用以設置已形成該些晶圓級角隅間隔 體220之該些晶片210’該些晶片210之該主動面211 係皆為朝上，並藉由該些第一銲線3 11電性連接該些晶 片210至該基板230。其中該基板230係可實質相同於 本發明之第一具體實施例之基板230,故沿用相同圖號。 請再參閱第8圖所示，該些晶片210係可為主動面 朝上的正向堆疊。該黏著膠320係形成於位於較下方之 晶片210之該主動面211。當該些晶片210在正向堆疊 時，位於較上方之晶片2 1 0之背面2 1 2係支撐於位於較 下方之晶片2 1 0之該些晶圓級角隅間隔體220上並接觸 該黏著膠320’其中位於較上方之晶片210之主動面211 係為朝上，以供該些第二銲線3 1 2、該些第三銲線3 1 3 與該些第四銲線3 1 4電性連接位於較上方之對應晶片 210至該基板230。其中，該黏者膠320係固化以黏著 位於較上方之晶片2 1 0與位於較下方之晶片2 1 0，該黏 著膠3 20於固化後之厚度係由該些晶圓級角隅間隔體 220之高度所定義。 本發明不侷限晶片所堆疊之數量，在本實施例中所 堆疊晶片之數量係為四個，每一晶片2 1 0之主動面2 1 1 角隅上皆形成有複數個晶圓級角隅間隔體2 2 0，以供疊 設其於上之晶片210。 因此’上述之多晶片堆疊結構不僅可省略習知之間 隔體之設置步驟並且在間隔體之上表面可不設置黏著 層，具有簡化步驟亦可降低晶片堆疊之整體厚度之功 16 1345826 ' 4 效’並且使位於較上 方之。玄些日曰片210不壓觸該些下 知·線 311、312 盘 τ 1 ^ . 2與313。在該黏著膠32〇固化之後亦The V* degree is the height of the wafer level corner spacers 220, and the thickness of the adhesive 250 after curing is substantially the same as the height of the spacers 220. Since the adhesive buildup includes the first active face 21 edge of the first wafer 210, the wafer level corner spacers 220 may not need to be a very small amount of adhesive material, and still have a good wafer stack gap (ie, the Adhesive bonding of the adhesive 250; f wafer level corner spacers 220 effective and accurate control I Therefore, the wafer level corner spacers 220 have an effect of maintaining the interval. This is because the crystals 220 The upper surface has no adhesive layer, and the ratio of the wafer level angle to the surface adhesive layer can be a maximum value. Even if the thickness of the corner spacer 220 is directly reduced, the stacking gap can be provided, and the multi-wafer stack height can still be external. Moreover, the conventional # step in the multi-wafer stacking process can be omitted, and there is no inconvenience when the spacer is in the pick-and-place alignment, and the adhesive layer 250 can cover the first active surface. The center and the side of the 2 1 1 can add the bonding strength between the 2 1 0 and the second wafer 260 and make the second wafer 260 not easily displaced. In the second crystal operation, the welding pin of the wire bonding machine ( Not shown in the figure) will apply pad 2 63 - downward pressure And the second wafer 260 is supported by the cured adhesive 250, so that there is no torque to cause the second wafer 260 to be broken at the edge; as defined. In other words, the adhesion angle of the wafer level angle 250 There is adhesive material or cohesive strength at the center and the edge of the layer. And P·degree) has been properly controlled by the 〇 玄 些 some wafer level with the spacer layer 220 . The spacer is disposed to touch the one of the bonding wires 210 and the first wafer is tying the building, and the bonding of the 260 to the second bonding periphery is obtained, and the situation is not 13th 1345826 *» s * * 'V, '5 G picture). Preferably, between the wafer level corner spacers 220 and the second back surface 262 of the second wafer 260, the second wafer 260 can be made by the adhesive 250. Adhesively bonding to the first wafer 210 does not require an adhesive layer between the wafer level corner spacers 220 and the second back surface 262 of the second wafers 260, and can be sufficiently adhered to the second The strength of the wafer 260. As shown in FIG. 6 , the second wafer 260 is connected to the substrate 230 by a plurality of second bonding wires 242 to reach the second wafer 260 and the substrate 23 0 . Electrical connection between the two. The heights of the wafer-level corner spacers 220 are higher than the arcing heights of the first bonding wires 24 1 to avoid the second wafer 260 pressing the first bonding wires 241 when the wafers are stacked. Moreover, the adhesive 250 has been cured to achieve the same wire bonding support effect as the wafer level corner spacers 220, and can withstand the force of the second wafer 260 and the substrate 230 when the wire is bonded, up to φ to prevent the The rupture of the second wafer 260 is broken. As further shown in Figures 5G and 6, the present invention further discloses a multi-wafer stack structure 200 fabricated in accordance with the foregoing method. The multi-wafer stack structure 200 mainly includes the first wafer 210, the wafer level corner spacers 220, the substrate 230, the first bonding wires 241, the adhesive 250, and the second wafer 260. . The wafer level corner spacers 220 are located on the corners of the first active surface 211 of the first wafer 210. The substrate 230 is used to set the first wafer 210 that has formed the wafer level corner spacers 220. The first bonding wires 24 1 are electrically connected to the first wafer 14 1345826. The substrate 230 is used to set the wafers 210 that have formed the wafer level corner spacers 220. The faces 211 are all facing upwards, and the wafers 210 are electrically connected to the substrate 230 by the first bonding wires 3 11 . The substrate 230 can be substantially identical to the substrate 230 of the first embodiment of the present invention, so that the same reference numerals are used. Referring again to Figure 8, the wafers 210 can be stacked in a forward direction with the active side facing up. The adhesive 320 is formed on the active surface 211 of the wafer 210 located below. When the wafers 210 are stacked in the forward direction, the back surface 2 1 2 of the upper wafer 210 is supported on the wafer level corner spacers 220 located on the lower wafers 2 1 0 and is in contact with the wafers 210 Adhesive 320', wherein the active surface 211 of the upper wafer 210 is upwardly provided for the second bonding wires 3 1 2, the third bonding wires 3 1 3 and the fourth bonding wires 3 1 4 electrically connecting the corresponding wafer 210 located above to the substrate 230. Wherein, the adhesive 320 is cured to adhere to the upper wafer 210 and the lower wafer 210, and the adhesive is cured to a thickness of the wafer-level corner spacer. The height of 220 is defined. The present invention does not limit the number of stacked wafers. In this embodiment, the number of stacked wafers is four, and each of the active planes 2 1 1 of each wafer has a plurality of wafer-level corners formed thereon. The spacer 2 2 0 is for the wafer 210 to be stacked thereon. Therefore, the above-mentioned multi-wafer stack structure can not only omit the conventional step of disposing the spacer and the surface of the spacer can be provided with no adhesive layer, and the simplified step can also reduce the overall thickness of the wafer stack by 16 1345826 '4 effect'. Make it located above. Xuan some Japanese 曰 210 does not touch the lower 知, line 311, 312 τ 1 ^ . 2 and 313. After the adhesive 32 is cured,
提供位於較上方夕枯B J h二日日片2 1 0良好的打線支撐性’ 免位於較上方^ 之5亥些晶片210因受打線接合力而崩裂 損壞。 、 以上所述，僅是本發明的較佳實施例而已，並非對 本發月作任何形式上的限制，本發明技術#案範胃t & 鲁所附中6f專利^圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 ' 奋’依據本發明的技術實質對以上實施例所作的任何簡 翠L改、等同變化與修飾’均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知多晶片堆疊結構之截面示意圖。 鲁 第2圖：依據本發明之第一具體實施例，在一種多晶片 堆疊方法中一半導體晶圓之主動面及局部放大示 意圖。 第3圖：依據本發明之第一具體實施例，在該多晶片堆 疊方法中形成有一層圖案化保護層之半導體晶圓 之主動面及局部放大示意圖。 第4圖：依據本發明之第一具體實施例，在該多晶片堆 疊方法中複數個已單體化之晶片之主動面示意 圖。 17Provided on the upper side of the night B J h two-day film 2 1 0 good wire support 'free than the upper half ^ 5 some of the wafer 210 due to the wire bonding force is broken and damaged. The above description is only a preferred embodiment of the present invention, and is not intended to impose any form limitation on the present month. The present invention is based on the patent of the invention. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the above embodiments are not deviated from the technical solution of the present invention. Any of the simple modifications, equivalent changes and modifications made by the examples are still within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-wafer stack structure. Lu Figure 2: An active side and partial enlarged view of a semiconductor wafer in a multi-wafer stacking method in accordance with a first embodiment of the present invention. Fig. 3 is a perspective view showing an active surface and a partial enlarged view of a semiconductor wafer having a patterned protective layer formed in the multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 4 is a schematic illustration of the active face of a plurality of singulated wafers in the multi-wafer stacking process in accordance with a first embodiment of the present invention. 17
1345826 第5A至5G圖：依據本發明之第一具體實施例，在 多晶片堆疊方法中該半導體晶圓之局部截面示 圖。 第6圖：依據本發明之第一具體實施例，繪示一種依 多晶片堆疊方法所製成之多晶片堆疊結構 側面示意圖。 第7圖：依據本發明之第一具體實施例，在該多晶片 疊方法中繪示一黏著膠形成於一已形成有晶圓 角隅間隔體之晶片上之立體示意圖。 第8圖：依據本發明之第二具體實施例，繪示另一種 用該多晶片堆疊方法所製成之多晶片堆疊 構之側面示意圖。 【主要元件符號說明】 10 半導體晶圓 11 切割道 20 防碎片護墊 30 點膠針頭 100多晶片堆疊結構 該 意 該 之 堆 級 利 結 11 0第一晶片 120間隔體 142第二銲線 160第二晶片 111主動面 130基板 1 5 1第一黏著層 1 6 1背面 11 2第一銲墊 141第一銲線 152第二黏著層 162第二銲墊 200多晶片堆疊結構 2 1 0第一晶片 213第一銲墊 211主動面 212第一背面 t 220晶圓級角隅間隔體 230基板 231接指 18 1345826 241 第- -銲線 242 第 260 第」 ， 曰 Η —aa乃 261 第 263 第二銲墊 311 第- -銲線 3 12 第 313 第： l銲線 314 第 320 黏著膠 二銲線 250黏著膠 二主動面 262第二背面 二銲線 四銲線1345826 Figures 5A through 5G are partial cross-sectional views of the semiconductor wafer in a multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 6 is a side elevational view showing a multi-wafer stack structure fabricated by a multi-wafer stacking method in accordance with a first embodiment of the present invention. Figure 7 is a perspective view showing a first embodiment of the present invention in which a sticker is formed on a wafer on which a wafer corner spacer is formed. Figure 8 is a side elevational view of another multi-wafer stack made by the multi-wafer stacking method in accordance with a second embodiment of the present invention. [Main component symbol description] 10 semiconductor wafer 11 dicing street 20 anti-fragment pad 30 dispensing needle 100 multi-chip stack structure This is the stack of the knot 10 0 first wafer 120 spacer 142 second bonding wire 160 Two wafers 111 active surface 130 substrate 1 5 1 first adhesive layer 1 6 1 back surface 11 2 first bonding pad 141 first bonding wire 152 second adhesive layer 162 second bonding pad 200 multi wafer stack structure 2 1 0 first wafer 213 first pad 211 active surface 212 first back t 220 wafer level corner spacer 230 substrate 231 finger 18 1345826 241 first - wire 242 260th, 曰Η - aa 261 263 second Pad 311 No. - Welded wire 3 12 No. 313: l Welded wire 314 No. 320 Adhesive two welding wire 250 Adhesive two active surface 262 Second back Two welding wire Four wire bonding wire
1919