TWI311368B - Ic package encapsulating a chip under asymmetric single-side leads - Google Patents

Ic package encapsulating a chip under asymmetric single-side leads Download PDF

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Publication number
TWI311368B
TWI311368B TW95140632A TW95140632A TWI311368B TW I311368 B TWI311368 B TW I311368B TW 95140632 A TW95140632 A TW 95140632A TW 95140632 A TW95140632 A TW 95140632A TW I311368 B TWI311368 B TW I311368B
Authority
TW
Taiwan
Prior art keywords
wafer
package structure
pins
pin
asymmetric
Prior art date
Application number
TW95140632A
Other languages
Chinese (zh)
Other versions
TW200822326A (en
Inventor
Chia-Yu Hung
Chao-Hsiang Leu
Tseng-Shin Chiu
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW95140632A priority Critical patent/TWI311368B/en
Publication of TW200822326A publication Critical patent/TW200822326A/en
Application granted granted Critical
Publication of TWI311368B publication Critical patent/TWI311368B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed is an IC package encapsulating a chip under asymmetric single-side leads, including a plurality of leads from a leadframe having asymmetric lengths at two sides, a plurality of die-adhesive strips, a first chip under the longer side leads and having a plurality of single side pads, at least a second chip above the longer side leads, a plurality of molding compound. The die-adhesive strips are disposed in parallel and attached to partial lower surfaces of the longer side leads for adhering the first chip. There are one or more mold-flow channels constructed by the first chip, the longer side leads and the parallel die-adhesive strips. The bonding wires connect the single side pads on the first chip to the two side leads. The molding compound encapsulates the first and second chips, the bonding wires, and some portions of the two side leads and is further filled in the mold-flow channels. The mold-flow channels created by the die-adhesive strips increase encapsulation area of the molding compound to the chip wire-bonded at single-side to improve product reliability of the IC package.

Description

1311368 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種單側邊打線之晶片封裝構 造’特別係有關於一種包覆在非對稱單側引腳下晶片 之封裳構造。 【先前技術】 晶片封裝是半導體製造技術的一門重要課題，針對 不同的晶片能產生各式不同的封裝種類。例如，覆晶 封裝時，晶片的凸塊銲墊應排列於矩陣排列；傳統的 打線晶片封裝，晶片的銲墊應排列在一主動面之周 邊。其中，一種適用於打線連接之晶片係僅具有單邊 或非對稱配置之銲墊’例如銲墊排列成L形或门形。 然此一非對稱銲墊配置之晶片在多晶片封裝上會提高 封膠製程的難度。 如第1圖所示，一種習知多晶片封裝構造1〇〇主要包 含一基板110、一第一晶片120、一第二晶片13〇、複數個第 一銲線141、複數個第二鍀線142、一封膠體150以及複數 個外接端子160。其中’第一晶片120與第二晶片130係為 非對稱銲墊配置之晶片。該第一晶片12〇之主動面121係設 有複數個單側銲墊122。該第二晶片130主動面131係設有 複數個單侧銲墊132。 該基板110係具有一上表面111與一下表面112，其中該 上表面111係設有該第一晶片120。該第二晶片130係斜向 堆疊於該第一晶片120上’以使該第二晶片130不遮蓋該第 • 1311368 一晶片120之該些單側銲墊122。該些第一銲線141係電性 連接該第一晶片120之該些單侧銲墊122至該基板110。該 些第二銲線142係電性連接該第二晶片13〇之該些單側銲墊 132至該基板11〇。該封膠體15〇形成於該基板11〇之上表 面111，以畨封該第一晶片12 〇、該第二晶片13 〇、該些第一 銲線141與該第二銲線142。例如銲球之該些外接端子16〇 係設置於該基板110之下表面112。在前述之傳統多晶片封 裝構造100中，該基板110佔整體封裝相當大的成本，且第 一晶片120被該封膠體150的直接覆蓋面積過少，容易有受 到内應力導致脫層的問題。且越上層錯位堆疊之晶片其連接 之銲線會越加的增長。 美國專利第M9M91號（其優先權案為我國專利公 404030號）揭示-種單側邊打線之多晶片封裝構造，使： 對稱引腳之導線架承載兩個單側銲塾之晶片。導線架之… 長側引腳係被夾設在兩錯位之晶片之仏卜另一壓模較 移體係密封該兩晶片及非對稱引聊之内端。由於長㈣= 兩晶片之夾設空間存在有縫隙，依模流填充之特性在 無法順利填滿該縫隙’藏附於縫隙的氣泡會;、向並 ㈣—）與爆米花（pQp⑽n)的 起脫層 度。 降低了產品可靠 【發明内容】 為了解決上述之問題’本發明之主要目 供-種包覆在非對稱單侧引腳下晶片之封 =提 加單側邊打線晶片被封膠體包覆之面積… 增 儐且瑕< 泡不會藏 7 .1311368 附在長側引腳之縫隙内，提昇半導體封裝產品之可靠 性。 本發明之次一目的係在於提供一種包覆在非對稱 單側引腳下晶片之封裝構造，以利封膠體可填滿較長側 引腳之間隙，且不會有氣泡藏在兩晶片之間，導致脫層 (delamination)或爆米花（popcorn)的問題。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種包覆在非對稱單側 引腳下晶片之封裝構造主要包含一導線架、複數個第 一黏晶膠條、一第一晶片、複數個第一銲線、至少一 第二晶片、複數個第二銲線以及一封膠體。該導線架 係具有非對稱之複數個第一側引腳與複數個第二側引 腳，其中該些第一側引腳係較長於該些第二側引腳且 其長度超過一中心線。該些第一黏晶膠條係相互平行 並貼附於該些第一側引腳之局部下表面。該第一晶片 之主動面係貼設於該些第一黏晶膠條，由該第一晶 片、該些第一側引腳與該些第一黏晶膠條之間形成有 至少一模流通道，且該主動面之一側邊形成有複數個 單側銲墊，該些單側銲墊係位於在該些第一側引腳與 該些第二側引腳之間的一非中心間隙。該些第一銲線 係將該些單側銲墊電性連接至該些第一側引腳與該些 第二側引腳。該第二晶片之背面係設置於該些第一側 引腳之上方，且不遮蓋上述之非中心間隙。該些第二 銲線係電性連接該第二晶片至該些第一側引腳與該些 8 1311368 第二側引腳。該封膠體係密封該第一晶片、該第二晶 片、該些第一銲線、該些第二銲線、以及該些第一侧 引腳與該些第二側引腳之一部位並填充於該模流通 道。 本發明的目的及解決其技術問題還可採用以不技 術措施進一步實現。 在前述的封裝構造中，該模流通道係橫向於該些第一 側引腳之間隙。 在刖述的封裝構造中，另包含有複數個第二黏晶膠 條，其係相互平行並貼附於該些第一侧引腳之局部上表面與 該第一晶片之背面。 在前述的封裝構造中’該些第一側引腳與該些第二側 引腳被該封膠體密封之部位係為共平面。 在前述的封裝構造中’該第二晶片係實質相同於該第 一晶片，亦具有複數個單側銲墊。 在前述的封裝構造中，該導線架另具有複數個第三側 引腳與複數個第四側引腳，其位於該封膠體之其餘兩側且較 短於該些第一側引腳。 在前述的封裝構造中，另包含有一第三晶片，其係設 置於該第二晶片上。 在前述的封裝構造中，該第三晶片係錯位疊設在該第 二晶片上。 在前述的封裝構造中，該第三晶片係實質相同於該第 二晶片，並且該第三晶片係重疊在該第二晶片上。 ‘1311368 -晶片之間 ，其係設 •晶片皆為 包覆在非 為該封裝 之導線架 側引腳下 數個第一 個第一黏 線 2 5 1、 以及一封 引腳212 第一側引 圖所示， 200 之一 與該第一 在前述的封裝構造中，該第三晶片與該第二 係形成有一間隔件。 在前述的封裝構造中，另包含有一第四晶少 置於該第一晶片之下方。 在前述的封裝構造中，該第二晶片與該第-單側邊打線連接之晶片。 【實施方式】 在本發明之第一具體實施例中，揭示一種 對稱單側引腳下晶片之封裝構造，第2圖係 構造之截面示意圖，第3圖係為該封裝構造 與下方晶片之俯視示意圖。 如第2及3圖所示，一種包覆在非對稱單 晶片之封裝構造200主要包含一導線架之複 側引腳2 1 1與複數個第二側引腳2 1 2、複數 晶膠條220、一第一晶片230、複數個第一矣 至少一第二晶片240、複數個第二銲線252 膠體262。該些第一側引腳21 1與該些第二积 係位在半導體封裝構造之兩相對應側，該些 腳2 1 1係較長於該些第二側引腳2 1 2。如第： 該些第一側引腳2 1 1之長度超過該封裝構造 中心線201，用以上下承載該第二晶片 240 晶片230 。 該些第一黏晶膠條 220係相互平行並貼附於該些 第一側引腳2 1 1之局部下表面2 1 1 A。而該第一晶片2 3 0 .1311368 之主動面23 1係貼設於該些第一黏晶膠條220。如 圖所示，該些第一黏晶膠條220係為細長條狀。 2及3圖所示，由該第一晶片2 3 0、該些第一側 2 1 1與該些第一黏晶膠條2 2 0之間形成有至少一 通道221。該些第一黏晶膠條220之厚度可約為 微米。 此外，該第一晶片2 3 0之主動面2 3 1之一側邊 有複數個單側銲墊233。在本實施例中，該些單 墊2 3 3係為一直線排列且位於在該些第一側引腳 與該些第二側引腳2 1 2之間的一非中心間隙2 1 3 些第一銲線2 5 1係經由該非中心間隙2 1 3將該些 銲墊23 3電性連接至該些第一側引腳2 1 1與該些 側引腳2 1 2。 該第二晶片240之背面241係設置於該些第一 腳2 1 1之上方，且不遮蓋上述之非中心間隙2 1 3 本實施例中，該第二晶片240係實質相同於該第 片230，亦具有複數個單側銲墊242。例如，該第 片230與該第二晶片240係為尺寸相同且該些單 墊242排列亦相同之晶片。該些第二銲線252係 連接該第二晶片240之該些單側銲墊242至該些 側引腳2 1 1與該些第二側引腳2 1 2。 該封膠體260係密封該第一晶片230、該第二 240、該些第一銲線251、該些第二銲線252、以 些第一側引腳2 1 1與該些第二側引腳2 1 2之内端 第3 如第 引腳 模流 100 形成 側銲 2 11 。該 單側 第二 側引 。在 一晶 一晶 側鲜 電性 第一 晶片 及該 並填 11 ‘1311368 充於該模流通道22 1。故可增加該第一晶片230被該 封膠‘Έ 260包覆之面積，提昇半導體封裝產兄之可靠 性。較佳地，如第3圖所示，該模流通道221係橫向 於該些第一側引腳2 1 1之間隙2 1 1 C，與模流方向概為 同向，該模流通道2 2 1之一端開口可作為主入膠口， 該模流通道22 1之另一端開口與該些第一側引腳2 1 1 之間隙2 1 1 C可作為排氣管道，使得該封膠體2 6 0可填 滿該些第一側引腳 2 1 1之間隙 2 1 1 C與該模流通道 221，可避免在該第一晶片230與該第二晶片240之間 產生氣泡，解決脫層（delamination)與爆米花（popcorn) 的問題。 較佳地，該封裝構造200可另包含有複數個第二黏 晶膠條 2 7 0，其係相互平行並貼附於該些第一側引腳 211 之局部上表面 211B與該第二晶片 240 之背面 24卜以增加模流通道之數量與增加第二晶片240被該 封膠體260包覆之面積。 此外，在本實施例中，該些第一側引腳2 1 1與該些 第二側引腳2 1 2被該封膠體260密封之内引腳部位係 為共平面。該些第一側引腳2 1 1與該些第二側引腳2 1 2 被該封膠體2 6 0密封之部位並無下沉彎折，可具有低 成本達到模流平衡之功效。 請參閱第4圖，在本發明之第二具體實施例中，另一種 包覆在非對稱單側引腳下晶片之封裝構造3 00主要包 含一導線架之複數個第一側引腳3 1 1與複數個第二側 12BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer package structure for single-sided wire bonding, particularly relating to a package structure of a wafer coated under an asymmetric one-sided pin. [Prior Art] Wafer packaging is an important issue in semiconductor manufacturing technology, and different types of packages can be produced for different wafers. For example, in a flip chip package, the bump pads of the wafer should be arranged in a matrix arrangement; in a conventional wire wafer package, the pads of the wafer should be arranged around an active surface. Among them, a type of wafer suitable for wire bonding has only a single-sided or asymmetrically arranged pad, e.g., the pads are arranged in an L-shape or a gate shape. However, a wafer with an asymmetric pad configuration can increase the difficulty of the encapsulation process on a multi-chip package. As shown in FIG. 1 , a conventional multi-chip package structure 1 〇〇 mainly includes a substrate 110 , a first wafer 120 , a second wafer 13 , a plurality of first bonding wires 141 , and a plurality of second wires 142 . , a glue 150 and a plurality of external terminals 160. Wherein the first wafer 120 and the second wafer 130 are wafers of an asymmetric pad configuration. The active surface 121 of the first wafer 12 is provided with a plurality of single-sided pads 122. The active surface 131 of the second wafer 130 is provided with a plurality of single-sided pads 132. The substrate 110 has an upper surface 111 and a lower surface 112, wherein the upper surface 111 is provided with the first wafer 120. The second wafer 130 is stacked obliquely on the first wafer 120 such that the second wafer 130 does not cover the single-sided pads 122 of the wafer 13 . The first bonding wires 141 are electrically connected to the one-side pads 122 of the first wafer 120 to the substrate 110. The second bonding wires 142 are electrically connected to the one-side pads 132 of the second wafer 13 to the substrate 11A. The encapsulant 15 is formed on the surface 111 of the substrate 11 to seal the first wafer 12, the second wafer 13, the first bonding wire 141 and the second bonding wire 142. For example, the external terminals 16 of the solder balls are disposed on the lower surface 112 of the substrate 110. In the conventional multi-chip package structure 100 described above, the substrate 110 occupies a considerable cost for the entire package, and the direct coverage area of the first wafer 120 by the sealant 150 is too small, and there is a problem that delamination is easily caused by internal stress. The higher the number of misaligned stacked wafers, the more the bonding wires will be connected. U.S. Patent No. M9M91 (the priority of which is Chinese Patent No. 404030) discloses a multi-chip package structure of single-sided wire bonding, such that: the lead frame of the symmetric pin carries two wafers of one-side soldering. The lead frame is... The long side pin is sandwiched between the two misaligned wafers, and the other die transfer system seals the inner ends of the two wafers and the asymmetric chat. Due to the long (four) = gap between the two wafers, the characteristics of the mold flow filling can not smoothly fill the gap 'bubble attached to the gap; to (4) -) and popcorn (pQp (10) n) Degree of delamination. Reducing product reliability [Summary of the Invention] In order to solve the above problems, the main object of the present invention is to encapsulate a wafer coated under an asymmetric one-side pin = to add a single-sided wire bonding wafer covered by an encapsulant ... 傧 傧 瑕 瑕 泡 泡 泡 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 A second object of the present invention is to provide a package structure of a wafer coated under an asymmetric single-sided pin, so that the sealant can fill the gap of the longer side pins without trapping bubbles in the two wafers. Between, causing problems with delamination or popcorn. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a package structure of a wafer coated under an asymmetric one-sided pin mainly comprises a lead frame, a plurality of first adhesive strips, a first wafer, a plurality of first bonding wires, and at least a second The wafer, a plurality of second bonding wires, and a gel. The lead frame has an asymmetrical plurality of first side pins and a plurality of second side pins, wherein the first side pins are longer than the second side pins and have a length exceeding a center line. The first adhesive strips are parallel to each other and attached to a partial lower surface of the first side pins. The active surface of the first wafer is attached to the first adhesive strips, and at least one mold is formed between the first wafer, the first side pins and the first adhesive strips. And a plurality of single-sided pads are formed on one side of the active surface, and the one-side pads are located in a non-center gap between the first side pins and the second side pins . The first bonding wires are electrically connected to the first side pads and the second side pins. The back surface of the second wafer is disposed above the first side pins and does not cover the non-center gap. The second bonding wires are electrically connected to the second chip to the first side pins and the second side pins of the 8 1311368. Sealing the first wafer, the second wafer, the first bonding wires, the second bonding wires, and a portion of the first side pins and the second side pins In the mold flow channel. The object of the present invention and solving the technical problems thereof can be further achieved by non-technical measures. In the foregoing package construction, the mold flow path is transverse to the gap of the first side pins. In the package structure described above, a plurality of second adhesive strips are disposed, which are parallel to each other and attached to the partial upper surface of the first side pins and the back surface of the first wafer. In the foregoing package structure, the first side pins are coplanar with the portions of the second side pins that are sealed by the sealant. In the foregoing package construction, the second wafer is substantially identical to the first wafer and also has a plurality of single-sided pads. In the foregoing package structure, the lead frame further has a plurality of third side pins and a plurality of fourth side pins located on the remaining sides of the encapsulant and shorter than the first side pins. In the foregoing package construction, a third wafer is further disposed on the second wafer. In the foregoing package configuration, the third wafer is misaligned on the second wafer. In the foregoing package construction, the third wafer is substantially identical to the second wafer, and the third wafer is overlaid on the second wafer. '1311368 - between the wafers, the wafers are covered by a number of first first bonding lines 2 5 1 under the lead pins of the package, and the first side of a pin 212 As shown in the drawings, one of the 200 and the first in the foregoing package configuration, the third wafer and the second system are formed with a spacer. In the foregoing package structure, a fourth crystal is further disposed under the first wafer. In the aforementioned package configuration, the second wafer is bonded to the first side of the wafer. [Embodiment] In a first embodiment of the present invention, a package structure of a symmetric single-sided pin-down wafer is disclosed. FIG. 2 is a schematic cross-sectional view of the structure, and FIG. 3 is a plan view of the package structure and the lower wafer. schematic diagram. As shown in FIGS. 2 and 3, a package structure 200 coated on an asymmetric single chip mainly comprises a double-sided pin 2 1 1 of a lead frame and a plurality of second side pins 2 1 2, a plurality of crystal strips 220, a first wafer 230, a plurality of first 矣 at least one second wafer 240, a plurality of second bonding wires 252 colloid 262. The first side pins 21 1 and the second series are on two opposite sides of the semiconductor package structure, and the legs 21 are longer than the second side pins 2 12 . For example, the length of the first side pins 21 1 exceeds the package structure center line 201 for carrying the second wafer 240 wafer 230 up and down. The first adhesive strips 220 are parallel to each other and attached to the partial lower surface 2 1 1 A of the first side pins 2 1 1 . The active surface 23 1 of the first wafer 2 3 0 1311368 is attached to the first adhesive strips 220. As shown, the first adhesive strips 220 are elongated strips. As shown in Figures 2 and 3, at least one channel 221 is formed between the first wafer 203, the first side 2 1 1 and the first viscous strips 2 2 0 . The first adhesive strips 220 may have a thickness of about micrometers. In addition, a plurality of single-sided pads 233 are formed on one side of the active surface 213 of the first wafer 230. In this embodiment, the single pads 233 are arranged in a line and are located in a non-center gap between the first side pins and the second side pins 2 1 2 A bonding wire 251 is electrically connected to the first side pins 2 1 1 and the side pins 2 1 2 via the non-center gap 2 1 3 . The back surface 241 of the second wafer 240 is disposed above the first legs 21 1 and does not cover the non-center gap 2 1 3 . In this embodiment, the second wafer 240 is substantially the same as the second chip. 230 also has a plurality of single-sided pads 242. For example, the second sheet 240 and the second wafer 240 are wafers of the same size and the same arrangement of the single pads 242. The second bonding wires 252 are connected to the one-side pads 242 of the second wafer 240 to the side pins 2 1 1 and the second side pins 2 1 2 . The encapsulant 260 seals the first wafer 230, the second 240, the first bonding wires 251, the second bonding wires 252, the first side pins 2 1 1 and the second side leads The inner end of the foot 2 1 2 is 3, as the first lead mold flow 100 forms a side weld 2 11 . The one side of the second side leads. The first electric wafer is fresh on the side of the crystal and the filling of the '1311368' is filled in the mold flow channel 22 1 . Therefore, the area of the first wafer 230 covered by the sealant Έ 260 can be increased to improve the reliability of the semiconductor package. Preferably, as shown in FIG. 3, the mold flow channel 221 is transverse to the gap 2 1 1 C of the first side pins 2 1 1 , and is substantially in the same direction as the mold flow direction, and the mold flow channel 2 is The one end opening of the mold can be used as the main glue inlet, and the gap between the other end of the mold flow channel 22 1 and the first side pin 2 1 1 2 1 1 C can be used as an exhaust pipe, so that the sealant 2 The gap of the first side pin 2 1 1 and the mold channel 221 can be filled in the gap between the first wafer 230 and the second wafer 240 to solve the delamination. (delamination) problems with popcorn (popcorn). Preferably, the package structure 200 further includes a plurality of second adhesive strips 210, which are parallel to each other and attached to the partial upper surface 211B of the first side pins 211 and the second wafer. The back side 24 of the 240 is used to increase the number of mold flow channels and to increase the area covered by the sealant 260 of the second wafer 240. In addition, in this embodiment, the first side pins 2 1 1 and the second side pins 2 1 2 are coplanar with the inner pin portions sealed by the encapsulant 260. The portions of the first side pins 2 1 1 and the second side pins 2 1 2 sealed by the encapsulant 210 are not sunken and bent, and have the effect of achieving a mold flow balance at a low cost. Referring to FIG. 4, in a second embodiment of the present invention, another package structure 300 that covers the wafer under the asymmetric one-sided pin mainly includes a plurality of first side pins 3 1 of a lead frame. 1 and a plurality of second sides 12

.1311368 引腳3 1 2、複數個第一黏晶膠條3 20、-複數個第一銲線3 5 1、至少一第二晶另 二銲線352以及一封膠體360。其中 3 1 1係較長於該些第二側引腳 3 1 2， 3 1 1之長度係可超過一中心線3 0 1。該 3 2 0係相互平行並貼附於該些第一側 下表面311A。該第一晶片330之主動 該些第一黏晶膠條3 20，由該第一晶少 側引腳3 1 1與該些第一黏晶膠條3 2 0 一模流通道3 2 1。該第一晶片3 3 0之 側邊形成有複數個單側銲墊 3 3 2。在 單側銲墊3 3 2係位於在該些第一側引 二側引腳3 1 2之間的一非中心間隙3 線3 5 1係將該些單側銲墊3 3 2電性連 引腳3 1 1與該些第二側引腳3 1 2。該 背面3 4 1係可藉由複數個第二黏晶膠 些第一側引腳3 1 1之上方，且不遮蓋 隙3 1 3。該些第二銲線3 5 2係電性連者 之複數個單侧銲墊3 42至該些第一側 第二側引腳 3 1 2。該封膠體 3 6 0係 330、該第二晶片340、該些第一銲轉 銲線3 5 2、以及該些第一側引腳3 1 1 腳3 1 2之一部位並填充於該模流通道 此外，在本實施例中，該封裝構造 -第一晶片3 3 0、 340、複數個笫 該些第一側引腳 該些第一側引腳 些第一黏晶膠條 引腳3 1 1之局部 面3 3 1係貼設於 ,3 3 0、該些第一 之間形成有至少 主動面331之一 黏晶之後，該些 腳3 1 1與該些第 13。該些第一銲 接至該些第一側 第二晶片340之 條3 9 0設置於該 上述之非中心間 該第二晶片340 引腳3 1 1與該些 密封該第一晶片 .3 5 1、該些第二 與該些第二側引 321 ° 300可另包含有 13 .1311368.1311368 Pin 3 1 2, a plurality of first adhesive strips 3 20, a plurality of first bonding wires 3 5 1 , at least a second second bonding wire 352 and a colloid 360. The length of the 3 1 1 is longer than the length of the second side pins 3 1 2, and the length of the 3 1 1 may exceed a center line 3 0 1 . The 3 20 lines are parallel to each other and attached to the first side lower surfaces 311A. The first die 330 is activated by the first die pad 3 1 1 and the first die pad 3 2 0 by a die flow channel 3 2 1 . A plurality of single-sided pads 3 3 2 are formed on the side of the first wafer 330. The one-side pad 3 3 2 is located between the first side lead two side pins 3 1 2 and a non-center gap 3 line 3 5 1 is electrically connected to the single-sided pads 3 3 2 Pin 3 1 1 and the second side pins 3 1 2 . The back surface 341 may be over the first side pins 3 1 1 by a plurality of second adhesive layers, and does not cover the gap 3 1 3 . The second bonding wires 3 5 2 are a plurality of single-sided pads 3 42 electrically connected to the first side second side pins 3 1 2 . The sealant 306 is 330, the second wafer 340, the first weld bond wires 325, and one of the first side pins 3 1 1 and 3 1 2 are filled in the mold. In addition, in this embodiment, the package structure - the first wafer 303, 340, the plurality of 第一 the first side pins, the first side pins, the first viscous strip pins 3 The partial surface 3 3 1 of the 1 1 is attached to the 3rd, and the first 3 is formed between at least one of the active surfaces 331 , and the legs 3 1 1 and the 13th. The strips 390 of the first soldering to the first side second wafers 340 are disposed between the non-center portions of the second wafer 340 pins 31 1 1 and the portions of the first wafers. 3 5 1 The second and the second side guides 321 ° 300 may additionally include 13.1311368

一第三晶片3 70，其係設置於該第二晶片340上，可 錯位疊設在該第二晶片340上，以不遮蓋該第二晶片 340之單側銲墊342。該第三晶片37〇係具有複數個銲 墊371’利用複數個第三銲線353電性連接至該些第 一側引腳3 11與該第二晶片3 4 0之該些單側銲墊3 4 2， 再經由訊號共用之第二銲線352電性速接至第二引腳 312。在本實施例中，該封裝構造可另包含有一第 四晶片3 80 ’其係設置於該第一晶片3 3 〇之下方，可 背對背方式貼附。該第四晶片3 80係具有複數個銲墊 381，並可利用複數個第四銲線354電性連接至該些第 一側引腳3 1 1與該些第二側引腳3丨2。 在本發明之第三具體實施例中，揭示另一種包覆在 非對稱單側引腳下晶片之封裝構造。第5圖為該封裝 構造之截面示意圖。第6圖為該封裝構造之導線架與其 下方晶片之俯視示意圖。 如第5及6圖所示，一種包覆在非對稱單側引腳下 晶片之封裝構造400主要包含一導線架之複數個第—伽 引腳411與複數個第二側引腳412、複數個坌一私 則 乐一黏晶膠條 〇、一第一晶片430、複數個第—銲線々si、至，丨、 第二晶片440、複數個第二銲線452 + 以及—封膠體 460。該些第一側引腳411與該些第二側引腳々ο係 非對稱長度’其中該些第一侧引腳411係較長於^ = 第二側引腳4 1 2且其長度超過一中心線4 〇 j。，二二 一黏晶膠條420係相互平行並貼附於哕此楚 第 二罘—侧引腳 14 4 1311368 4U之局部下表面411Αβ該第一晶片430之主動面431 係貼設於該些第—黏晶膠條42〇，由該第一晶片430、 镑些第一側引腳411與該些第一黏晶膠條420之間形 成有至少一模流通道42 1，且該主動面43 1之一側邊 形成有複數個單側銲墊432，該些單側銲墊432係位 於在該些第一側引腳411與該些第 > 侧引腳4 1 2之間 的一非中心間隙4 1 3。該些第一錄線4 5 1係將該些單 側銲墊432電性連接至該些第一側弓丨腳4 1 1與該些第 二側引腳412。該第二晶片440之背面441係可藉由 複數個第二黏晶膠條4 8 0設置於该检第一側引腳4 11 之上方，且不遮蓋上述之非中心間隙41 3 °該些第二 銲線452係電性連接該第二晶片44〇之複數個鲜塾442 至該些第一側引腳4 11與該些第 > 侧引腳4 1 2。該封 膠體46〇係密封該第一晶片430、該第二晶片440、該 些第一銲線4 5 1、該些第二銲線4 5 2、以及該些第一侧 引腳4 1 1與該些第二側引腳4 1 2之’部位並填充於該 模流通道42 1。較佳地，該模流通遒42 1係橫向於該 些第一側引腳4 1 1之間隙4 1 1 C (如第6圖所示）’使得 該封膠髏460可填滿該些第一側引腳41 1之間隙 4 1 1 C，玎避免在單側邊打線與錯位堆疊晶片之間產生 氣泡，而導致脫層（delamination)或爆米花（P〇Pc〇rn)的 問題。 在本實施例中，該封裝構造另包含有一第三晶片 47〇，其係設置於該第二晶片440上，該第三晶片470 15 t 1311368 係具有複數個銲墊47 1，利用複數個第三銲線 性連接至該些第一侧引腳 4 1 1與該些第二> 412。該第三晶片470與該第二晶片440之間係 有一間隔件472，可使該第三晶片470係重疊 二晶片440上，並不會壓觸該些第二銲線452。 如第6圖所示，在本實施例中，該第一晶片 銲墊4 3 2係為非對稱之门形排列，且該導線架 ^ 複數個第三側引腳4 1 4與複數個第四側引腳4 位於該封膠體460之其餘兩側且較短於該些第 腳4 1 1，利用該些第一銲線4 5 1電性連接較短 43 2至該些第三側引腳4 1 4與該些第四側引腳‘ 本發明可以應用於多晶片封裝。如第7圖所 一種包覆在非對稱單側引腳下晶片之封裝構造 要包含一導線架之複數個第一側引腳5 1 1與複 二側引腳5 1 2、複數個第一黏晶膠條520、一第 • 53 0、一第二晶片540、複數個銲線5 50以及一 5 6 0。該些第一側引腳5 1 1係與該些第二側引腳 非對稱且較長。該些第一黏晶膠條5 2 0係相互 貼附於該些第一側引腳5 1 1之局部下表面。該 片530之主動面531係貼設於該些第一黏晶膠 由該第一晶片5 3 0、該些第一側引腳5 1 1與該 黏晶膠條5 20之間形成有至少一模流通道5 2 1 C 該第二晶片5 4 0之背面5 4 1係設置於該些第一 5 1 1之上方，可利用複數個平行排列之第二黏 45 3電 測引腳 可形成 在該第 I 430之 另具有 15，其 一側引 侧銲墊 415 ° 示，另 500主 數個第 一晶片 封膠體 5 1 2為 平行並 第一晶 條 5 20, 些第一 1此外， 側引腳 晶膠條 16 1311368 570黏接該第二晶片540,同樣地，由該第二晶片540、 該些第一側引腳5 11與該些第二黏晶膠條5 70之間形 成有至少一另一模流通道5 7 1。在本實施例中，該第二 晶片540與該第一晶片530皆為單側邊打線連接之晶片。該 些銲線5 5 0係將該第一晶片5 3 0與該第二晶片540之單 側銲墊5 3 2、5 42電性連接至該些第一側引腳5 1 1與該 些第二側引腳5 1 2。該封膠體560係密封該第一晶片 I 530、該第二晶片 540、該些銲線550、以及該些第一 側引腳5 1 1與該些第二側引腳5 1 2之一部位並填充於 該模流通道5 2 1、5 7 1。此外，該封裝構造5 0 0可另包 含至少一在第二晶片540上方之第三晶片5 80，其係 具有複數個單側銲墊 5 8 1。另包含至少一在第一晶片 530下方之第四晶片 590，其係具有複數個單側銲墊 591。在本實施例中，所有晶片 530、540、580、590 可為相同之單側邊打線之晶片並錯位地斜向堆疊，以 φ 供該些銲線550電性連接至該些引腳511與512。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖：習知多晶片封裝構造之截面示意圖。 17 ,1311368 第2圖：依據本發明之篦—β —具體實施例，一錄台番 對稱單侧引腳下3曰Η + 種I覆在非 卜日日片之封裝構造之截 第3圖：依據本發明之第一曰 、.“、圖。 具體實施例，該封奘播 導線架與其下方# μ &釘裝構造之 Β片之俯視示意圖。 第4圖•·依據本發明之笛__ .. 一具體實施例’另一種白薄 在非對稱單側引腳 種包覆 意圖。 下日日片之封裝構造之載面示A third wafer 703 is disposed on the second wafer 340 and is misaligned on the second wafer 340 so as not to cover the one-side pad 342 of the second wafer 340. The third wafer 37 has a plurality of pads 371 ′ electrically connected to the first side pins 3 11 and the second side pads 340 of the second chip 340 by using a plurality of third bonding wires 353 3 4 2, and then electrically connected to the second pin 312 via the second bonding wire 352 shared by the signal. In this embodiment, the package structure may further include a fourth wafer 380' disposed under the first wafer 3 3 ,, which may be attached in a back-to-back manner. The fourth chip 380 has a plurality of pads 381 and can be electrically connected to the first side pins 31 and the second side pins 3 丨 2 by using a plurality of fourth bonding wires 354. In a third embodiment of the invention, another package construction encapsulating the wafer under an asymmetric one-sided pin is disclosed. Figure 5 is a schematic cross-sectional view of the package construction. Figure 6 is a top plan view of the leadframe of the package construction and the wafer below it. As shown in FIGS. 5 and 6, a package structure 400 encapsulating a wafer under an asymmetric one-sided pin mainly includes a plurality of first gamma pins 411 and a plurality of second side pins 412, a plurality of lead frames. The first wafer 430, the plurality of first bonding wires 々si, the 丨, the second wafer 440, the plurality of second bonding wires 452 + and the sealing body 460 . The first side pins 411 and the second side pins are asymmetric lengths, wherein the first side pins 411 are longer than ^= the second side pins 4 1 2 and the length thereof exceeds one Center line 4 〇j. The two-two adhesive crystal strips 420 are parallel to each other and attached to the second side-side pins 14 4 1311368 4U partial lower surface 411 Α β the active surface 431 of the first wafer 430 is attached to the The first adhesive layer 42 is formed by the first wafer 430, the first side pins 411 and the first adhesive strips 420, and the active surface is formed. One side of the 43 1 is formed with a plurality of single-sided pads 432, and the one-side pads 432 are located between the first side pins 411 and the first side pins 4 1 2 Non-central gap 4 1 3 . The first recording pads 451 are electrically connected to the first side pads 411 and the second side pins 412. The back surface 441 of the second wafer 440 can be disposed above the first side pin 4 11 by the plurality of second adhesive strips 400, and does not cover the non-center gap 41 3 °. The second bonding wire 452 is electrically connected to the plurality of fresh 442 of the second wafer 44 to the first side pins 4 11 and the second side pins 4 1 2 . The encapsulant 46 seals the first wafer 430, the second wafer 440, the first bonding wires 415, the second bonding wires 425, and the first side pins 4 1 1 And the portions of the second side pins 4 1 2 are filled in the mold flow channel 42 1 . Preferably, the mold flow 遒 42 1 is transverse to the gap 4 1 1 C of the first side pins 4 1 1 (as shown in FIG. 6) such that the sealant 460 can fill the first The gap of the one side pin 41 1 is 4 1 1 C, which avoids the occurrence of bubbles between the single-sided wire and the misaligned stacked wafer, resulting in delamination or popcorn (P〇Pc〇rn). In this embodiment, the package structure further includes a third wafer 47〇 disposed on the second wafer 440, the third wafer 470 15 t 1311368 having a plurality of pads 47 1 , using a plurality of The triple solder is linearly connected to the first side pins 4 1 1 and the second > 412. A spacer 472 is disposed between the third wafer 470 and the second wafer 440 to overlap the second wafer 440 without pressing the second bonding wires 452. As shown in FIG. 6, in the embodiment, the first wafer pad 423 is an asymmetric gate-shaped arrangement, and the lead frame has a plurality of third side pins 4 1 4 and a plurality of The four side pins 4 are located on the remaining two sides of the sealant 460 and are shorter than the first legs 141. The first bonding wires 451 are electrically connected to the shorter 43 2 to the third side leads. The foot 4 1 4 and the fourth side pins 'the present invention can be applied to a multi-chip package. The package structure of the wafer coated on the asymmetric single-sided pin as shown in FIG. 7 includes a plurality of first side pins 5 1 1 and a complex two side pins 5 1 2 of a lead frame 2 The adhesive strip 520, a 530 0, a second wafer 540, a plurality of bonding wires 5 50 and a 506. The first side pins 5 1 1 are asymmetric and longer with the second side pins. The first adhesive strips 5 2 0 are attached to a part of the lower surface of the first side pins 51 1 . The active surface 531 of the sheet 530 is attached to the first adhesive layer. The first wafer 530, the first side pins 51 1 and the adhesive strip 5 20 are formed at least. A mold flow channel 5 2 1 C The back surface 5 4 1 of the second wafer 510 is disposed above the first 511, and a plurality of parallel electrodes 4 485 can be used. The other one formed on the first 430 has 15 with one side lead pad 415 °, and the other 500 main first wafer encapsulants 51 are parallel and the first crystal strip 5 20, some first one The side lead plastic strip 16 1311368 570 is bonded to the second wafer 540. Similarly, between the second wafer 540, the first side pins 5 11 and the second adhesive strips 5 70 At least one other mold flow channel 517 is formed. In this embodiment, the second wafer 540 and the first wafer 530 are both wafers connected by a single side wire. The bonding wires 505 are electrically connected to the first side pads 5 3 2, 5 42 of the first wafer 530 and the second wafer 540 to the first side pins 51 1 and The second side pin 5 1 2 . The encapsulant 560 seals the first wafer I 530, the second wafer 540, the bonding wires 550, and the first side pins 51 1 and the second side pins 5 1 2 And filled in the mold flow channels 5 2 1 , 5 7 1 . In addition, the package structure 500 can further include at least one third wafer 580 over the second wafer 540 having a plurality of single-sided pads 581. Further included is at least one fourth wafer 590 under the first wafer 530 having a plurality of single-sided pads 591. In this embodiment, all of the wafers 530, 540, 580, and 590 may be the same single-sided wired wafers and stacked obliquely in a misaligned manner, and the bonding wires 550 are electrically connected to the pins 511 and φ. 512. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-chip package structure. 17 , 1311368 Figure 2: According to the invention, 篦 - β - a specific embodiment, a recorded symmetry single-sided pin under 3 曰Η + species I covered in the non-Di Ri Ri package structure of the third section According to a first embodiment of the present invention, a schematic view of a cymbal according to the present invention. __ .. A specific embodiment 'another white thin on the asymmetric one-sided pin type coating intention. The next day's package structure of the package shows

第5 依據本發明之第 在非對稱單側引 示意圖。 三具體實施例，另—種包覆 腳下晶片之封裝構造之截面 第6圖依據本發明之第： 道仏知 一具體實施例，該封裝構造之 導線架與其下方衣稱w之 ^ . s片之俯視示意圖。 第7圖.依據本發明之第 ^ „ 四具體實施例，另一種包霜 在非對稱單側引 已覆 音圖 下日日片之封裝構造之截面示 思圓。The fifth schematic diagram according to the first aspect of the present invention. Three specific embodiments, another cross-section of a package structure for wrapping a foot wafer, FIG. 6 is in accordance with the present invention: In a specific embodiment of the invention, the lead frame of the package structure and the underlying garment are called w. A bird's eye view. Fig. 7. In accordance with the fourth embodiment of the present invention, another type of frosting is shown in the cross section of the package structure of the Japanese wafer under the asymmetric one-sided overlying sound map.

【主要元件符號說明】 100多晶片封裝構造 110 120 130 141 150 200 基板 I" 第一晶片 121 第一晶片 13 1 第—銲線 142 上表面 主動面 主動面 第二銲線 1 1 2下表面 1 2 2單側銲墊 1 3 2單側銲墊 封膠體 160 包覆在非對稱單側 中心線 211 外接端子 引腳下晶片之封裝構造 第—側引腳 211A下表面 18 201 .1311368 2 11B上表面 211 C間隙 213非中心間隙 220第—黏晶膠條221模流通道 23()第一晶片 231主動面 240第二晶片 241背面 251第一銲線 252第二銲線 260封移體 270 笛一 卑二黏晶膠條271模流通道 300包覆在非對稱單侧引腳下晶片之封裝構造 212第 引腳 232單側銲墊 242單側銲墊 3〇1中心線 311第一侧弓丨腳 312 楚 昂二側引腳 313非中心間隙 320 笛 卑一黏晶膠條321模流通道 330 第一 b u 卑目日片 331主動面 3 11Α下表面 340第二晶片 351第一銲線 籲 354第四銲線 370第三晶片 380第四晶片 341背面 352第二銲線 360封膠體 371銲墊 381銲墊 3 3 2單側銲墊 3 42單側銲墊 353第三銲線 390第二黏晶膠條 4〇〇包覆在非對稱單侧引腳下晶片之封裝構造 401中心@ 、’、 411第一側弓丨腳 411A下表面 411C間险 414楚412第二側弓丨腳 413非中心間隙 二側引腳 415第四側弓丨腳 420第—點Β殺作 勒日日膠條421模流通道 19 .1311368 430 第一晶片 431 主動面 432 單侧銲墊 440 第二晶片 441 背面 442 銲墊 451 第一銲線 452 第二銲線 453 第三銲線 460 封膠體 470 第三晶片 471 銲墊 472 間隔件 480 第二黏晶膠條 500 包覆在非對稱單側引腳下晶片 之封裝構造 511 第一側引腳 512 第二側引腳 520 第一黏晶膠條 521 模流通道 530 第一晶片 531 主動面 532 單側銲墊 540 第二晶片 541 背面 542 單側銲墊 550 銲線 560 封膠體 570 第二黏晶膠條 571模流通道 580 第二晶片 581 單側銲墊 590 第四晶片 591 單側銲墊 20[Main component symbol description] 100 multi-chip package structure 110 120 130 141 150 200 substrate I" first wafer 121 first wafer 13 1 first-bonding wire 142 upper surface active surface active surface second bonding wire 1 1 2 lower surface 1 2 2 single-sided pad 1 3 2 single-sided pad sealant 160 wrapped on the asymmetric single-sided center line 211 external terminal pin under the package structure of the first side pin 211A lower surface 18 201 .1311368 2 11B Surface 211 C gap 213 non-center gap 220 first - adhesive strip 221 mold flow channel 23 () first wafer 231 active surface 240 second wafer 241 back surface 251 first bonding wire 252 second bonding wire 260 sealing body 270 flute A smear two adhesive crystal strip 271 mold flow channel 300 wrapped in an asymmetric single-sided pin under the chip package structure 212 pin 232 single-sided pad 242 single-sided pad 3 〇 1 center line 311 first side bow丨 312 Chu ang two side pin 313 non-center gap 320 Descartes a sticky crystal strip 321 mold channel 330 first bu 日 片 331 active surface 3 11 Α lower surface 340 second wafer 351 first welding line appeal 354 fourth bonding wire 370 third wafer 380 fourth wafer 341 back 352 second Line 360 Sealant 371 Pad 381 Pad 3 3 2 Single Side Pad 3 42 Single Side Pad 353 Third Bond Line 390 Second Sticker Strip 4〇〇 Wrapped on Asymmetric One Side Pin Under Wafer Package structure 401 center @, ', 411 first side bow 411A lower surface 411C 414 412 Chu 412 second side bow 413 non-center gap two side pin 415 fourth side bow 420 foot - point Β Killed as a day strip 421 mold channel 19 .1311368 430 first wafer 431 active surface 432 single side pad 440 second wafer 441 back 442 pad 451 first bond wire 452 second bond wire 453 third bond wire 460 Sealant 470 Third Wafer 471 Pad 472 Spacer 480 Second Sticker Strip 500 Wrapped on Asymmetric One-Side Pin Under Wafer Package Structure 511 First Side Pin 512 Second Side Pin 520 First Adhesive strip 521 Mold flow channel 530 First wafer 531 Active surface 532 Single side pad 540 Second wafer 541 Back side 542 Single side pad 550 Wire bond 560 Sealant 570 Second stick crystal strip 571 Mold channel 580 Two wafers 581 single side pads 590 fourth wafer 591 single side soldering 20

Claims (1)

.1311368 十、申請專利範園： 卜一種包覆在非對稱單侧引腳下晶片之封裝構造，包含·· -導線架之複數個第一側引腳與複數個第二側引腳，其 中該些第-侧引腳係較長於該些第二側引腳且其長度超 過一中心線； 複數個第-黏晶膠條，其係相互平行並貼附於該些第— 側引腳之局部下表面； :第-晶片’其主動面係貼設於該些第__黏晶膠條，由 忒第-晶片'該些第一侧引腳與該些第_黏晶膠條之間 形成有至V-模流通道，且該主動面之—側邊形成有複 數個單侧銲墊，該些單側銲墊係、位於在該些第—側引聊 與該些第二側引腳之間的一非中心間隙； 複數個第-n其將該些單側銲墊電性 -側引腳與該些第二側引腳； “ 至；一第二晶片，其背面係設置於該些第一侧引腳之上 方，且不遮蓋上述之非中心間隙； 複數個第二銲線，其係電性連接該第二晶片至該些第— 側引腳與該些第二側引腳；以及 封膠體’其係密封該第-晶片、該第二晶片、該些第 線該些第一知線、以及該些第一侧引腳與該此第 一側引腳之—部位並填充於該模流通道。 2、如申請專利範圍第1項所述之包覆在非對稱單側引腳下 曰曰片之封裝構造，其中該模流通道係橫向於該些第一側 引腳之間隙。 1 21 .1311368 3、 如申請專利範图坌 a ΰ 項所述之包覆在非對稱單側引saj 目日片之封裝構造，另包含有 ㈣腳下 相互平行並貼附於 一黏晶膠條，其係 V亚貼附於該些第一側引 二晶片之背面。 叫〈局社表面與該第 4、 如申請專利範圍第丨項所述之 晶片之封裝構造，盆中…y非對稱早側引腳下 一中該些第一側引腳血此一 腳破該封膠體密封之部位係為共平面。—側引 5、 如申請專利範圍第丨 晶片之封裝構it，；L覆在非對稱單側引腳下 晶片，第二晶片係實f相同於該第-亦具有複數個單側銲墊。 6、 如申請專利範圍第i項 晶片之封裝構造，其中，導壤=在非對稱單側引腳下 腳與複數個第四側引腳：Γ 有複數個第三側引 較短於該些第一側引聊。、位於該封膠體之其餘兩側且 7、 如申請專利範圍帛 腳下晶片之封裝構造，另m非對稱單側引 於該第二晶片上。匕3有—第三晶片，其係設置 8、 如申請專利範圍第7項 晶片之封裝構造，其中該：一曰非對稱單側引腳T 晶片上。 °Χ第二晶片係錯位疊設在該第二 9、 如申請專利範圍第7 晶片之封裝構造，其中^之包覆在非對稱單側引腳下 晶片，並且該第三晶片：：二晶片係實質相同於該第二 1〇 , ^ φ ^ ^ 糸重疊在該第二晶片上。 如“專利範圍第9項所述之包覆在非對稱單側引- 22 .1311368 下晶片之封装構造， 係形成有一間隔件。 11、如申請專利範圍第 下晶片之封裝構造， 該第一晶片之下方。 其中該第 三晶片與該第二晶 片之間 7項所述之包覆在 巧包含有一第四晶 非對稱單側引聊 片’其係設置於.1311368 X. Application for Patent Park: A package structure of a wafer wrapped under an asymmetric one-sided pin, comprising a plurality of first side pins and a plurality of second side pins of the lead frame, wherein The first side pins are longer than the second side pins and have a length exceeding a center line; a plurality of first-adhesive strips are parallel to each other and attached to the first side pins a partial lower surface; the first wafer's active surface is attached to the first __ viscous strips, and between the first side pins and the first viscous strips Forming a V-mode flow channel, and the side of the active surface is formed with a plurality of single-sided pads, and the one-side pads are located at the first side and the second side a non-center gap between the legs; a plurality of -n of the one-side pad electrical-side pins and the second side pins; "to; a second wafer, the back side of which is disposed Above the first side pins, and not covering the non-center gap; the plurality of second bonding wires electrically connecting the second chip to the first a side pin and the second side pins; and a sealant 'which seals the first wafer, the second wafer, the first lines, the first lines, and the first side pins The portion of the first side pin is filled in the mold flow channel. 2. The package structure of the underside of the asymmetric one-side pin, as described in claim 1, wherein the mold is circulated. The channel is transverse to the gap between the first side pins. 1 21 .1311368 3. The package structure of the asymmetric one-side saj mesh as described in the patent application 坌a ΰ, including There are (4) feet parallel to each other and attached to a sticky crystal strip, which is attached to the back side of the first side lead two wafers. It is called the "Company surface and the fourth, as in the scope of the patent application" The package structure of the wafer, the y ... asymmetry of the early side of the pin, the first side of the pin, the foot of the seal is sealed to be coplanar. - side lead 5, such as Apply for the patent range 丨 chip package structure it; L over the asymmetric single-sided pin under the wafer, second The chip is the same as the first one and has a plurality of single-sided pads. 6. The package structure of the wafer of the i-th aspect of the patent application, wherein the guide = the asymmetrical one-sided pin and the fourth Side pins: Γ There are a plurality of third side leads shorter than the first side chats. They are located on the other sides of the sealant and 7. The package structure of the wafer at the foot of the patent application scope, and m asymmetry One side is led to the second wafer. The 匕3 has a third wafer, which is provided with a package structure of the wafer of the seventh aspect of the patent application, wherein: an asymmetric one-side pin T wafer. The second wafer is misaligned and stacked on the second substrate, such as the package structure of the seventh wafer of the patent application, wherein the wafer is coated on the asymmetric single-sided pin, and the third wafer: two wafers It is substantially the same as the second one, and ^ φ ^ ^ 糸 is superimposed on the second wafer. The package structure of the wafer coated on the asymmetric one-side lead- 22.1311368 as described in the scope of Patent No. 9 is formed with a spacer. 11. The package structure of the lower wafer as claimed in the patent application, the first The underside of the wafer, wherein the coating between the third wafer and the second wafer is covered by a fourth crystal asymmetric one-sided chatter 12、如申請專利範圍第 下晶片之封裝構造， 單側邊打線連接之晶 1項所述之包覆在非對稱單側引腳 其中該第二晶片與該第一晶片皆為 片012. The package structure of the first wafer in the patent application scope, the one side of the wire bonding connection is coated on the asymmetric one-side pin, wherein the second wafer and the first wafer are both slices 0 23twenty three
TW95140632A 2006-11-02 2006-11-02 Ic package encapsulating a chip under asymmetric single-side leads TWI311368B (en)

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