CN1234158C - Manufacturing method of packaging base plate and its structure - Google Patents
Manufacturing method of packaging base plate and its structure Download PDFInfo
- Publication number
- CN1234158C CN1234158C CN 03154941 CN03154941A CN1234158C CN 1234158 C CN1234158 C CN 1234158C CN 03154941 CN03154941 CN 03154941 CN 03154941 A CN03154941 A CN 03154941A CN 1234158 C CN1234158 C CN 1234158C
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- Prior art keywords
- contact
- welding
- power supply
- passive component
- carrier
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The present invention relates to a manufacturing method and a structure of a packaging base plate. The manufacturing method at least comprises the steps: providing a bearing device which has one surface and a plurality of connection points configured on the surface; bridging at least one passive element with a plurality of welding ends respectively and electrically connected to the connection points among the connection points; forming a metallic layer on the surfaces of the welding ends and the exposed surfaces of the connection points. When a subsequent leading wire is bonded, both ends of the leading wire can be respectively connected to one welding pad of the chip and one welding end of the passive element to enhance the qualified rate and the reliability of the chip packaging technology.
Description
Technical field
The present invention relates to a kind of chip packaging method and structure thereof, and particularly relevant for a kind of base plate for packaging manufacture method and structure thereof of the bonding kenel that applies to go between.
Background technology
Because development of semiconductor, under the market demand improves, make semiconductor industry constantly develop more accurate, electronic component faster, technology with present semiconductor packages, such as the technology of chip packaging, the making of chip support plate (chip carrier) and the assembling of passive component (passive component) etc., all in semiconductor industry, occupy indispensable status.
With regard to the technology of chip packaging, each cuts formed bare chip (die) by wafer (wafer), for example with lead-in wire bonding (wire bonding) or flip-chip welding modes such as (flip chip bonding), be disposed at the surface of a carrier (carrier), wherein carrier for example is lead frame (leadframe) or substrate (substrate), chip then has a plurality of welded gaskets, make the welded gasket of chip be able to transmission line and contact, and be electrically connected to outside electronic installation via carrier.In addition, utilize the chip of lead-in wire bonding, after the contact of its welded gasket and substrate is electrically connected, forms an adhesive material again chip and lead-in wire are coated, be used for protecting chip and lead-in wire, so promptly finish a chip package process and structure thereof.
Figure 1A～1C shows the schematic flow sheet of the chip package process of existing a kind of bonding kenel that goes between in regular turn.Please refer to Figure 1A, a carrier 110 at first is provided, its surface has a chips welding district 112, and the surface of carrier 110 disposes a power supply contact 116, a ground contact 114 and a signal contact 118 at least.In addition, power supply contact 116 and ground contact 114 are positioned at the same side in chips welding district 112, and signal contact 118 be positioned at power supply contact 116 and ground contact 114 away from the outside in chips welding district 112.Wherein, power supply contact 116, ground contact 114 and signal contact 118 for example are made of a trace layer of patterning, and a welding cover layer 140 of coverability graph caseization is gone back on the surface of trace layer, and welding cover layer 140 has a plurality of openings 142, and it exposes the surface of power supply contact 116, ground contact 114 and signal contact 118 respectively.In addition, produce oxidation for fear of contact and outside air, the surface of carrier 110 can form a metal level 144 by the mode of electroplating, this metal level 144 for example is nickel, gold or other alloy, it is covered in the surface that is exposed of power supply contact 116, ground contact 114 and signal contact 118, to improve the reliability in the follow-up lead key closing process.
Please refer to Figure 1B, dispose a chip 120 in the surface of carrier 110, and chip 120 is attached in the chips welding district 112 with the back side 122, and chip 120 active surperficial 124 have a plurality of welded gaskets 126, and it corresponds respectively to power supply contact 116, ground contact 114 and signal contact 118.
Please refer to Fig. 1 C, the two ends that connect lead-in wire 134,136,138 respectively to a welded gasket 126 of chip 120 with and pairing power supply contact 116, ground contact 114 and signal contact 118.In addition, in order effectively to improve the electrical characteristic of chip-packaging structure 100, normally utilize surface mounting technology (Surface Mount Technology, SMT) small passive element 130 is attached to the surface of carrier 110, be used for reducing the noise cross-talk (crosstalk) that signal is produced when switching, and keep signal transmitting quality.Wherein, passive component 130 for example is inductance element (inductor) or capacity cell (capacitor), and passive component 130 is cross-placed between the power supply contact 116 and ground contact 114 of carrier 110, and two welding ends 132a, the 132b of passive component 130 are connected to power supply contact 116 and ground contact 114 respectively.
Please refer to Fig. 1 C equally, it should be noted that, passive component 130 for example is configured in the below of signal lead 138, and signal lead 138 can be across the top of passive component 130 and can not touch the welding ends 132a of passive component 130, therefore the laying space that can improve signal lead 138.Yet, be connected in the lead-in wire 136 between welded gasket 126 and the power supply contact 116, must stride across the top of passive component 130 earlier, be soldered to again on the surface of power supply contact 116 afterwards.Because lead-in wire 136 must elongate camber line earlier, just can stride across the top of passive component 130, so 136 itself the length that cause relatively going between increase, and signal rows increases through 136 the transmission path of going between, to the electric property of chip 120 be reduced, and the laying space of the contiguous lead-in wire of influence.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of base plate for packaging manufacture method, be used for improving the qualification rate and the reliability of follow-up lead key closing process.
For reaching above-mentioned purpose of the present invention, the invention provides a kind of base plate for packaging manufacture method, one carrier at first is provided, the surface of this carrier has a chips welding district, and a trace layer that forms patterning is in the surface of carrier, and wherein trace layer has a power supply contact, a ground contact and a signal contact, and then at least one passive component of cross-over connection is between power supply contact and ground contact, passive component has at least two welding endss, and it is electrically connected to power supply contact and ground contact respectively.At last, form a metal level in the surface of these welding endss and the surface that is exposed of power supply contact, ground contact and signal contact.
Described according to the preferred embodiments of the present invention, above-mentioned metal level is for example formed in the mode of electroplating, and the material of metal level can be selected from a kind of material by nickel, gold and group that these alloys are formed.In addition, passive component for example is inductance element or capacity cell, and the welding ends of passive component can be welded on the surface of power supply contact and ground contact by surface mounting technology (SMT) respectively.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A～1C shows the schematic flow sheet of the chip package process of existing a kind of bonding kenel that goes between in regular turn;
Fig. 2 A～2C shows the schematic flow sheet of chip package process of a kind of bonding kenel that goes between of one embodiment of the present invention in regular turn.
Description of reference numerals
110 carriers, 112 chips welding districts
114 ground contacts, 116 power supply contacts
118 signal contacts, 120 chips
124 active surfaces, 122 back sides
126 welded gaskets, 130 passive components
132a welding ends 132b welding ends
134 lead-in wires, 136 lead-in wires
138 lead-in wires, 140 welding cover layers
142 openings, 144 metal levels
210 carriers, 212 chips welding districts
214 ground contacts, 216 power supply contacts
218 signal contacts, 220 chips
224 active surfaces, 222 back sides
226a welded gasket 226b welded gasket
226c welded gasket 230 passive components
The 236a first lead-in wire 236b first lead-in wire
238 second lead-in wires, 240 welding cover layers
242 openings, 244 metal levels
Embodiment
Fig. 2 A～2C shows the schematic flow sheet of chip package process of a kind of bonding kenel that goes between of one embodiment of the present invention in regular turn.Please refer to Fig. 2 A, a carrier 210 at first is provided, this carrier for example is a substrate, and its surface has a chips welding district 212, and the surface of carrier 210 disposes a power supply contact 216, a ground contact 214 and a signal contact 218 at least.In addition, power supply contact 216 and ground contact 214 are positioned at the same side in chips welding district 212, and both are for example formed by a power ring (not shown) of the periphery that is surrounded on chips welding district 212 and the local line segment of a ground loop (not shown) respectively, and signal contact 218 be positioned at power supply contact 216 and ground contact 214 away from the outside in chips welding district 212.Wherein, power supply contact 216, ground contact 214 and signal contact 218 for example are made of a trace layer of patterning, and a welding cover layer 240 of coverability graph caseization is gone back on the surface of trace layer, and welding cover layer 240 has a plurality of openings 242, and it exposes the surface of power supply contact 216, ground contact 214 and signal contact 218 respectively.
Please refer to Fig. 2 A equally, in the present embodiment, at least one passive component 230 of cross-over connection is between power supply contact 216 and ground contact 214, and passive component 230 has at least two welding ends 232a, 232b, it can be welded on the surface of power supply contact 216 and ground contact 214 by surface mounting technology (SMT) respectively, be used for reducing the noise cross-talk that signal is produced when switching, and keep signal transmitting quality.Wherein, passive component 230 for example is small inductance element or capacity cell, and the material of its welding ends for example is a leypewter.
Then please refer to Fig. 2 B, form a metal level 244 simultaneously in the surface of welding ends 232a, 232b and the surface that is exposed of power supply contact 216, ground contact 214 and signal contact 218, be used for avoiding contact 214,216,218 and outside air to produce the effect of oxidation.Wherein, the material of metal level 244 for example is nickel, gold or its alloy, and it can be formed at the surface of welding ends 232a, 232b and the surface that is exposed of contact 214,216,218 by the mode of electroplating.In addition, metal level 244 adopts and the good metal material of gold thread bonding, so can improve the reliability of follow-up lead key closing process.
Please refer to Fig. 2 C, dispose a chip 220 in the surface of carrier 210, and chip 220 is attached in the chips welding district 212 with the back side 222, and chip 220 active surperficial 224 have a plurality of welded gaskets 226, and it corresponds respectively to power supply contact 216, ground contact 214 and signal contact 218.
Please refer to Fig. 2 C equally, in order to shorten the length of first lead-in wire 236a, 236b, present embodiment directly is welded on the end of at least one first lead-in wire 236a on the welding ends 232a of passive component 230, wherein the two ends of the first lead-in wire 236a can corresponding be connected to a welded gasket 226a of chip 220 and the welding ends 232a away from chip 220 of passive component 220, and two ends of another first lead-in wire 236b can corresponding be connected to that the welding ends 232b of the adjacent chips 220 of another welded gasket 226b of chip 220 and passive component 230 goes up or ground contact 214 on.Because the outer field first lead-in wire 236a must not elongate the top that camber line strides across passive component 230, but directly be welded on the welding ends 232a of passive component 230, therefore the length of the outer field first lead-in wire 236a can effectively shorten, and signal rows shortens through the transmission path of the first lead-in wire 236a, to the electric property of chip 220 be improved, and increase the laying space of contiguous lead-in wire.In addition, the two ends of second lead-in wire 238 can correspondingly connect the another welded gasket 226c of chip 220 and the signal contact 218 of carrier 210 outermost, and second lead-in wire 238 also can be across the top of passive component 230, and can not touch arbitrary welding ends 232a, the 232b of passive component 230.
By above explanation as can be known, base plate for packaging manufacture method of the present invention bridges at least one passive component earlier between the power supply contact and ground contact of carrier, and two welding endss of passive component connect power supply contact and ground contact respectively, and form the surface that exposed of a metal level in welding ends and power supply contact, ground contact and the signal contact of passive component simultaneously.
In sum, base plate for packaging manufacture method of the present invention has following advantage:
(1) utilizes the mode of electroplating, form a metal level simultaneously in the contact surface of passive component and the surface that is exposed of power supply contact, ground contact and signal contact, be beneficial to a follow-up end that will go between and directly be connected on the welding ends of passive component, use the qualification rate and the reliability that improve chip package process.
(2) Yin Xian a end can directly be welded on the welding ends of passive component, and therefore the length of lead-in wire can effectively shorten, and signal rows shortens through the transmission path of lead-in wire, will improve the electric property of chip, and increases the wiring space of contiguous lead-in wire.
Though the present invention discloses as above in conjunction with a preferred embodiment; so it is not to be used for limiting the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention is with being as the criterion that claim was defined.
Claims (9)
1. base plate for packaging manufacture method comprises at least:
One carrier is provided, and it has a surface and a plurality of contacts, and wherein those joint configuration are in this surface;
At least one passive component of cross-over connection is between those contacts, and this passive component has a plurality of welding endss, and it is electrically connected to those contacts respectively; And
Form a metal level in the surface of those welding endss and the surface that those contacts exposed.
2. base plate for packaging manufacture method as claimed in claim 1 wherein after this carrier is provided, also comprise a welding cover layer that forms patterning in this surface of this carrier, and this welding cover layer exposes the surface of those contacts.
3. base plate for packaging manufacture method as claimed in claim 1, wherein this metal level is formed in the mode of electroplating.
4. base plate for packaging manufacture method as claimed in claim 1, wherein the material of this metal level is selected from a kind of material by nickel, gold and nickel group that billon is formed.
5. base plate for packaging manufacture method as claimed in claim 1, wherein this passive component be inductance element and capacity cell one of them.
6. a package substrate construction is suitable for carrying a chip of lead-in wire bonding kenel, and this package substrate construction comprises at least:
One carrier has a surface, a power supply contact, a ground contact and a signal contact, and this surface has a chips welding district, and this power supply contact, this ground contact and this signal contact all are disposed at the zone outside this chips welding district; And
At least one passive component is cross-placed between this power supply contact and this ground contact of this carrier, and this passive component has at least two welding endss, and it is electrically connected to this power supply contact and this ground contact respectively; And
One metal level is covered in the surface of those welding endss and the surface that is exposed of this power supply contact, this ground contact and this signal contact.
7. package substrate construction as claimed in claim 6 also comprises a welding cover layer of patterning, be disposed at this surface of this carrier, and this welding cover layer exposes the surface of this power supply contact, this ground contact and this signal contact.
8. package substrate construction as claimed in claim 6, wherein this passive component be inductance element and capacity cell one of them.
9. package substrate construction as claimed in claim 6, wherein the material of this metal level is selected from a kind of material by nickel, gold and nickel group that billon is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03154941 CN1234158C (en) | 2003-08-25 | 2003-08-25 | Manufacturing method of packaging base plate and its structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03154941 CN1234158C (en) | 2003-08-25 | 2003-08-25 | Manufacturing method of packaging base plate and its structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1485893A CN1485893A (en) | 2004-03-31 |
| CN1234158C true CN1234158C (en) | 2005-12-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03154941 Expired - Lifetime CN1234158C (en) | 2003-08-25 | 2003-08-25 | Manufacturing method of packaging base plate and its structure |
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| Country | Link |
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| CN (1) | CN1234158C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
| US9147664B2 (en) * | 2013-10-11 | 2015-09-29 | Mediatek Inc. | Semiconductor package |
| US9806053B2 (en) | 2013-10-11 | 2017-10-31 | Mediatek Inc. | Semiconductor package |
| CN115831935B (en) * | 2023-02-15 | 2023-05-23 | 甬矽电子(宁波)股份有限公司 | Chip packaging structure and chip packaging method |
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2003
- 2003-08-25 CN CN 03154941 patent/CN1234158C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1485893A (en) | 2004-03-31 |
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Granted publication date: 20051228 |