CN115831935B - Chip packaging structure and chip packaging method - Google Patents
Chip packaging structure and chip packaging method Download PDFInfo
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- CN115831935B CN115831935B CN202310114403.8A CN202310114403A CN115831935B CN 115831935 B CN115831935 B CN 115831935B CN 202310114403 A CN202310114403 A CN 202310114403A CN 115831935 B CN115831935 B CN 115831935B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
- H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present disclosure provides a chip packaging structure and a chip packaging method, and relates to the technical field of semiconductor packaging. The chip packaging structure comprises a substrate, an electronic device and a wire bonding structure, wherein the substrate is provided with a grounding part, and the electronic device is electrically connected with the grounding part; the wire bonding structure is electrically connected with the grounding part, and is positioned on the outer side of the electronic device, and one end of the wire bonding structure, which is far away from the grounding part, is higher than the surface of one side of the electronic device, which is far away from the substrate. The static electricity discharge can be realized, the heat dissipation effect is improved, and adverse effects caused by electron migration are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a chip packaging method.
Background
With the rapid development of the semiconductor industry, the adoption of a flip-chip stacked hybrid packaging structure, such as flip-chip and forward chip stacking, can meet the multi-functional and miniaturized design of electronic packaging products. With the increasing of the stacking density, the size of the welding spot of the flip chip is smaller and smaller, the current density born by the welding spot and the working temperature of the welding spot are increased sharply, and the phenomenon of electron migration is generated inside the welding spot. The electron transfer phenomenon is an atomic transfer phenomenon caused by inelastic collision of high-density electron flow with atoms in the welding spot. Electromigration causes bumps and voids in the interconnect pads. Electromigration has become a challenge for reliability of electronic packages and a major obstacle to the continued development of electronic products.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a chip packaging method, which can realize electrostatic discharge, reduce adverse effects caused by an electromigration phenomenon and improve a heat dissipation effect.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a chip package structure, including:
a substrate, on which a grounding part is provided;
an electronic device electrically connected to the ground;
and the wire bonding structure is electrically connected with the grounding part, and is positioned at the outer side of the electronic device, and one end of the wire bonding structure, which is far away from the grounding part, is higher than the surface of one side of the electronic device, which is far away from the substrate.
Optionally, the electronic device includes a first pad, and the first pad is soldered with the grounding portion;
and one side of the electronic device, which is far away from the first bonding pad, is provided with a connecting part, and one end of the wire bonding structure, which is far away from the grounding part, is connected with the connecting part.
Optionally, the connection part includes at least one metal pad, and the wire bonding structure is electrically connected with at least one metal pad;
or, the connecting part comprises a metal layer, the metal layer covers one side surface of the electronic device, which is far away from the substrate, and the wire bonding structure is welded with the metal layer.
Optionally, the wire bonding structure includes a plurality of wire bonding structures distributed around the electronic device.
Optionally, the electronic device includes a flip chip, the flip chip is provided with a flip bump, the flip bump is welded with the grounding portion, and the wire bonding structure is welded with the grounding portion.
Optionally, the electronic device further includes a front-mounted chip, and the front-mounted chip is disposed on a side of the flip chip away from the substrate; the front-mounted chip is electrically connected with the substrate;
one end of the wire bonding structure, which is far away from the grounding part, is higher than one side surface of the flip chip, which is far away from the substrate.
Optionally, a glue layer is arranged between the front-mounted chip and the flip chip.
Optionally, the adhesive layer is conductive adhesive or insulating adhesive.
Optionally, the wire bonding structure is arranged at the periphery of the electronic device and is arranged at intervals with the adhesive layer; alternatively, the wire bonding structure is connected to the adhesive layer.
Optionally, the side wall of the flip chip is provided with a metal flank layer, the wire bonding structure is connected to the metal flank layer, and the adhesive layer is electrically connected with the metal flank layer.
Optionally, a metal electrical connection layer is disposed on a side of the front-mounted chip, which is close to the flip chip, and the metal electrical connection layer is electrically connected with the wire bonding structure.
Optionally, a plastic package body is disposed on the substrate, the plastic package body encapsulates the electronic device, and the wire bonding structure is exposed out of the plastic package body.
Optionally, a bending part is arranged at one end of the wire bonding structure exposed out of the plastic package body.
Optionally, a protective adhesive is disposed between the substrate and the electronic device, the protective adhesive at least partially covers the wire bonding structure, and the protective adhesive covers the grounding portion.
In a second aspect, the present invention provides a chip packaging method, including:
providing a substrate; the substrate is provided with a grounding part;
mounting an electronic device on the substrate; wherein the electronic device is electrically connected with the grounding part;
forming a wire bonding structure by wire bonding from the grounding part; the wire bonding structure is positioned on the outer side of the electronic device, and one end, away from the grounding part, of the wire bonding structure is higher than the surface of one side, away from the substrate, of the electronic device.
Optionally, the method further comprises:
after forming the wire bond structure, a protective paste is filled between the electronic device and the substrate.
Optionally, the step of mounting an electronic device on the substrate includes:
mounting a flip chip on the substrate; wherein the flip chip is welded with the grounding part;
attaching a normal chip to the flip chip; wherein, an adhesive layer is arranged between the flip chip and the normal chip;
the step of forming a wire bonding structure from the ground wire bonding includes:
and forming a wire bonding structure between the grounding part and the adhesive layer.
Optionally, the step of mounting a flip chip on the substrate includes:
forming a metal flank layer on the side wall of the flip chip;
the step of mounting the front-mounted chip on the flip chip comprises the following steps: overflowing the adhesive layer when the forward chip is attached to the forward chip so as to be electrically connected with the metal flank layer;
the step of forming a wire bonding structure from the ground wire bonding includes: and forming a wire bonding structure between the grounding part and the metal flank layer.
Optionally, the step of forming the routing structure from the grounding portion includes:
the wire bonding structure is higher than the flip chip, and one end of the wire bonding structure, which is far away from the grounding part, is arranged at intervals with one side surface of the flip chip, which is far away from the substrate;
the step of mounting the front-mounted chip on the flip chip comprises the following steps:
pressing the normal chip onto the flip chip; wherein, one end of the wire bonding structure far away from the grounding part is pressed to one side surface of the flip chip far away from the substrate; and a metal electric connecting layer is arranged on one side of the forward chip, which is close to the flip chip, and the wire bonding structure is electrically connected with the metal electric connecting layer.
The beneficial effects of the embodiment of the invention include, for example:
according to the chip packaging structure and the chip packaging method provided by the embodiment of the invention, the wire bonding is performed on the grounding part, the wire bonding structure is distributed on the outer side of the electronic device, and one end of the wire bonding structure, which is far away from the grounding part, is higher than the upper surface of the electronic device, so that static electricity around and on the surface of the electronic device can be eliminated, and the phenomenon of electron migration of welding spots of the electronic device under the condition that the born current density and the working temperature of the welding spots are rapidly increased is relieved, and the adverse effect caused by the phenomenon of electron migration is reduced. The wire bonding structure can also improve the heat dissipation performance of the chip packaging structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a first structure of a chip package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second structure of a chip package structure according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a third structure of a chip package structure according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a fourth structure of a chip package structure according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a fifth structure of a chip package structure according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a sixth structure of a chip package structure according to an embodiment of the present invention;
fig. 7 and 8 are schematic views illustrating a first process of a chip packaging method according to an embodiment of the invention;
fig. 9 is a schematic diagram of a second process of the chip packaging method according to the embodiment of the invention.
Icon: 100-chip packaging structure; 110-a substrate; 111-ground; 113-functional pads; 115-protective glue; 120-an electronic device; 121-flip chip; 123-first pads; 124-second pads; 125-a connection; 127-metal flank layer; 130-a wire bonding structure; 131-a bend; 140-normal chip; 141-metal lines; 143-a metal electrical connection layer; 150-plastic package body; 160-an adhesive layer; 170-solder balls.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1, the present embodiment provides a chip package structure 100, which includes a substrate 110, an electronic device 120, and a wire bonding structure 130, wherein a grounding portion 111 is disposed on the substrate 110. The electronic device 120 is electrically connected to the ground 111. The wire bonding structure 130 is electrically connected to the grounding portion 111, and the wire bonding structure 130 is located outside the electronic device 120, where an end of the wire bonding structure 130 away from the grounding portion 111 is higher than a side surface of the electronic device 120 away from the substrate 110 (i.e., an upper surface of the electronic device 120). Through the routing on the grounding portion 111, the routing structure 130 is distributed outside the electronic device 120 and is higher than the upper surface of the electronic device 120, and can eliminate static electricity around and on the surface of the electronic device 120, so as to relieve the electromigration phenomenon of the welding spot of the electronic device 120 under the condition that the born current density and the working temperature of the welding spot are rapidly increased, and reduce the adverse effect caused by the electromigration phenomenon. The routing structure 130 also improves the heat dissipation performance of the chip package structure 100.
In connection with fig. 2, optionally, electronic device 120 includes, but is not limited to, a chip or component, or the like. In this embodiment, the electronic device 120 includes a flip chip 121, the flip chip 121 is provided with a first pad 123, and the first pad 123 is soldered to the ground portion 111. It is easy to understand that the flip chip 121 is further provided with a second pad 124, the second pad 124 being a functional connection pad, the second pad 124 being soldered with the functional pad 113 on the substrate 110 to achieve an electrical connection of the flip chip 121 and the substrate 110. The substrate 110 may be a silicon carrier plate, a ceramic plate, or other base plate, and is not particularly limited herein. The grounding portion 111 may be provided in a pad structure or may be provided in a groove or protrusion structure, so long as it is capable of facilitating soldering or wire bonding.
The electronic device 120 is provided with a connecting portion 125 at a side far away from the first bonding pad 123, and one end of the wire bonding structure 130 far away from the grounding portion 111 is connected to the connecting portion 125. Optionally, the connection portion 125 includes at least one metal pad, and the wire bonding structure 130 is electrically connected to the at least one metal pad. That is, the connection portion 125 may be provided in a structure form of a pad, and a specific shape, number, distribution position, etc. thereof may be flexibly adjusted according to actual situations. Alternatively, the connection portion 125 includes a metal layer covering a surface of the electronic device 120 remote from the substrate 110, and the wire bonding structure 130 is soldered to the metal layer. That is, the connection portion 125 may be continuous and present in a large coverage, for example, the metal layer may be formed by sputtering metal, attaching a metal film, plating metal, or the like. The connection portion 125 may be formed on the upper surface of the flip chip 121, or may be formed on the upper surface and four sides of the flip chip 121. Since the connection portion 125 is made of metal, it has an electromagnetic shielding function after being connected to the ground portion 111 through the wire bonding structure 130. Of course, in some embodiments, the connection portion 125 may be made of a non-metal material, which also has the effects of releasing static electricity and improving heat dissipation performance, but has no electromagnetic shielding effect.
Alternatively, the wire bond structure 130 may be one or more. If the wire bond structure 130 includes a plurality of wire bond structures 130, the plurality of wire bond structures 130 are distributed around the electronic device 120. The wire bond structures 130 and the ground portions 111 may be in one-to-one correspondence, i.e., the number of wire bond structures 130 and the ground portions 111 are equal. One of the routing structures 130 is disposed corresponding to one of the grounding portions 111. Of course, a plurality of wire bonding structures 130 may be disposed on the same grounding portion 111, and the wire bonding directions of the wire bonding structures 130 are different and uniformly distributed along the periphery of the electronic device 120, so that the effect of eliminating static electricity and the heat dissipation effect are better. It will be appreciated that the end of the wire bond 130 remote from the ground 111 may extend in any direction, such as vertically upward, to form a fence structure; or each toward the center of the upper surface of the electronic device 120 to form a cage structure, not specifically defined herein. The cage structure means that the wire bonding structure 130 is curved or arc-shaped, and the highest point of the arc-shaped is higher than the end of the wire bonding structure 130 far away from the grounding portion 111.
In this embodiment, the grounding portion 111 employs a plurality of grounding pads, and the plurality of grounding pads are annularly distributed on the outer periphery of the electronic device 120. For example, one or more grounding portions 111 are disposed in the front-rear-left-right direction of the electronic device 120.
Optionally, the electronic device 120 comprises a flip chip 121, the flip chip 121 being provided with flip bumps, i.e. first pads 123. The flip-chip bumps are soldered to the ground 111, and the wire bonding structure 130 is soldered to the ground 111. The grounding part 111 has both a soldering structure and a wire bonding structure 130, and serves as a grounding circuit layer for leading static electricity around the flip chip 121 from the wire bonding structure 130 to the substrate 110, and the grounding part 111 is connected with the grounding circuit layer inside the substrate 110, so that the influences of the soldering spot structure of the chip and the electromigration around the chip (such as electrostatic accumulation on the back surface of the chip and inside the chip) are avoided. In addition, the wire bonding structure 130 can improve heat dissipation of the chip package structure 100.
In this embodiment, referring to fig. 1 and 2, a protective adhesive 115 is disposed between the substrate 110 and the electronic device 120, the protective adhesive 115 at least partially covers the wire bonding structure 130, and the protective adhesive 115 covers the grounding portion 111. It is understood that the protective paste 115 is filled between the flip chip 121 and the substrate 110, and the protective paste 115 may protect the bonding structure of the flip bump and the ground 111, the bonding structure of the second pad 124 on the flip chip 121 and the functional pad 113 on the substrate 110, and the bonding site of the wire bonding structure 130 and the ground 111, etc. Due to the arrangement of the wire bonding structure 130, static electricity on the upper surface and around the flip chip 121 can be released, and static electricity on the lower surface of the flip chip 121 can be released through the flip bumps and the grounding part 111, so that static electricity interference can be avoided, and meanwhile, the problems of dissolution, fracture and other failure of the bottom protection glue 115 caused by the electromigration phenomenon can be relieved. In addition, due to the arrangement of the routing structure 130, when the protective glue 115 at the bottom is filled, the capillary action is also provided, so that the capillary effect of the protective glue 115 around the chip can be improved, the fluidity of the protective glue 115 around the chip is increased, the fluidity of the protective glue 115 filled at the bottom is improved, and the phenomenon of cavitation at the bottom of the flip chip 121 is avoided. Thus, the problem that the protective adhesive 115 is easily broken at the cavity when being influenced by the electron migration can be avoided. And meanwhile, the structural integrity and mechanical property of the protective adhesive 115 are guaranteed, and the structural reliability and connection stability of the welding structure are guaranteed.
The substrate 110 is provided with a plastic package body 150, and the plastic package body 150 encapsulates the electronic device 120, so as to protect the electronic device 120, the wire bonding structure 130 and the like.
Referring to fig. 2, optionally, the electronic device 120 further includes a front-mounted chip 140, where the front-mounted chip 140 is disposed on a side of the flip-chip 121 away from the substrate 110; the front-mounted chip 140 is electrically connected to the substrate 110. In this embodiment, the front-mounted chip 140 is connected to the substrate 110 by bonding wires 141. One end of the wire bonding structure 130 away from the ground portion 111 is higher than a surface of the flip chip 121 away from the substrate 110. Alternatively, an end of the wire bonding structure 130 remote from the ground 111 is disposed between the front chip 140 and the flip chip 121.
Optionally, an adhesive layer 160 is disposed between the front-mounted chip 140 and the flip-chip 121, and the front-mounted chip 140 is adhesively fixed to the flip-chip 121 through the adhesive layer 160. The wire bonding structure 130 can discharge static electricity between the front-mounted chip 140 and the flip chip 121, prevent electrostatic interference and alleviate adverse effects caused by electromigration. It should be understood that if static electricity exists between the front-mounted chip 140 and the flip-chip 121, the static electricity is affected by the electromigration phenomenon, and when the current and the temperature gradient are larger, the electromigration effect is easily triggered, so that the defects of dissolution of the interfacial compound of the adhesive layer, fracture of the adhesive layer and the like are caused, and the integrity of the adhesive layer structure is damaged and the mechanical property is degraded, so that the device fails.
Optionally, the wire bonding structure 130 is connected to the adhesive layer 160, and can guide the static electricity on the upper surface of the flip chip 121 to the grounding portion 111 for release, so as to ensure the structural integrity and mechanical properties of the adhesive layer 160 between the flip chip 121 and the front-mounted chip 140, and prevent the adhesive layer 160 from breaking, generating voids or dissolving. Alternatively, the adhesive layer 160 is conductive adhesive or insulating adhesive. If the adhesive layer 160 is conductive adhesive, the wire bonding structure 130 is electrically connected with the conductive adhesive, so as to play a role in electromagnetic shielding for the flip chip 121. Flip chip 121 includes, but is not limited to, a radio frequency chip, a memory chip, a sensor chip, or the like. If the adhesive layer 160 is an insulating adhesive, it can play roles of electrostatic discharge, buffering, heat dissipation, etc.
With reference to fig. 3, it can be understood that the wire bonding structure 130 is disposed at the periphery of the electronic device 120 and spaced apart from the adhesive layer 160. This can block static electricity from entering or accumulating on the flip chip 121, and guide static electricity around the flip chip 121 to the ground portion 111 for discharging, such as guiding static electricity agglomerated at the bottom of the metal line 141 to the ground portion 111.
Referring to fig. 4, optionally, a metal side wing layer 127 is disposed on a sidewall of the flip chip 121, the wire bonding structure 130 is connected to the metal side wing layer 127, and the adhesive layer 160 is electrically connected to the metal side wing layer 127. It will be appreciated that by providing the metal side wing layer 127, soldering and routing of the routing structure 130 is facilitated. During stacking of the front-mounted chips 140, the glue layer 160 may overflow and be connected to the metal side wing layer 127. If the adhesive layer 160 is conductive adhesive, the wire bonding structure 130 and the adhesive layer 160 are directly or indirectly electrically connected, and then have electromagnetic shielding effect. Of course, the adhesive layer 160 may be an insulating adhesive, which is not particularly limited herein. In this embodiment, the plurality of wire bonding structures 130 are arranged around the flip chip 121 in a cage shape, and the highest point of the wire arc of the wire bonding structure 130 is higher than the upper surface of the flip chip 121, which is beneficial to locking the adhesive layer 160 between the front-mounted chip 140 and the flip chip 121.
Referring to fig. 5, optionally, a metal electrical connection layer 143 is disposed on a side of the front-mounted chip 140 adjacent to the flip-chip 121, and the metal electrical connection layer 143 is electrically connected to the wire bonding structure 130. It will be appreciated that the front-mounted chip 140 is provided with wire bonding pads provided on the front side of the front-mounted chip 140 (the upper surface of the front-mounted chip 140 in the drawing) for electrical connection with the substrate 110 via wire bonding 141. The metal electrical connection layer 143 is provided on the back surface of the front-mounted chip 140 (the lower surface of the front-mounted chip 140 in the drawing). One end of the wire bonding structure 130, which is far from the ground portion 111, is disposed above the flip chip 121 with a certain distance from the upper surface of the flip chip 121. When the chip 140 is stacked, the adhesive layer 160 contacts the wire bonding for electrostatic shielding and electrostatic discharge, and the metal electrical connection layer 143 can be designed at the bottom of the chip 140, and when the metal electrical connection layer 143 is designed, the adhesive layer 160 can be conductive adhesive or non-conductive adhesive. If the bonding structure 130 is made of non-conductive adhesive, the bonding structure is connected with the metal electrical connection layer 143 at the bottom of the front-mounted chip 140, so that the electromagnetic shielding effect on the flip-chip 121 can be achieved.
Referring to fig. 6, optionally, a plastic package body 150 is disposed on the substrate 110, the plastic package body 150 encapsulates the electronic device 120, and the wire bonding structure 130 is exposed to the plastic package body 150. The wire bonding structure 130 is arranged at one end far away from the grounding part 111, exposing the plastic package body 150, so that static electricity accumulated on the surface of the plastic package body 150 can be introduced into the grounding part 111 of the substrate 110, the purpose of protecting products is achieved, and the plastic package body 150 is prevented from being broken down by static electricity. In addition, the heat dissipation of the packaging structure is facilitated. It should be appreciated that if the electronic device 120 is continuously stacked on the surface of the plastic package 150, the exposed end portion of the wire bonding structure 130 may be used as a grounding end of the stacked electronic device 120, so that the arrangement of the grounding end may be reduced, the structure is more compact, and the grounding is more convenient. Optionally, a bending portion 131 is disposed at an end of the wire bonding structure 130 exposed out of the plastic package 150. The bending part 131 can promote the bonding force between the wire bonding structure 130 and the plastic package body 150, and the structure is more reliable. And the heat dissipation area is larger, and the heat dissipation effect is better.
Second embodiment
Referring to fig. 7 and 8, an embodiment of the present invention provides a chip packaging method, including:
step S100: providing a substrate 110; the substrate 110 is provided with a ground portion 111 and a functional pad 113. The ground portion 111 is provided on the outer periphery of the functional pad 113.
Step S200: mounting an electronic device 120 on a substrate 110; wherein the electronic device 120 is electrically connected to the grounding portion 111. In this embodiment, the electronic device 120 includes a flip chip 121, a first bonding pad 123 of the flip chip 121 is bonded to the ground 111 on the substrate 110, and a second bonding pad 124 of the flip chip 121 is bonded to the functional bonding pad 113 on the substrate 110. The flip-chip 121 is further provided with a connection 125 on a side surface facing away from the substrate 110.
Step S300: forming a wire bonding structure 130 from the ground portion 111; the routing structure 130 is located outside the electronic device 120, and an end of the routing structure 130 away from the grounding portion 111 is higher than a surface of the electronic device 120 away from the substrate 110. Alternatively, an end of the wire bonding structure 130 away from the ground portion 111 may be connected to the upper surface of the flip chip 121, or may be spaced apart from the flip chip 121, i.e., an end of the wire bonding structure 130 away from the ground portion 111 is spaced apart from the upper surface or side of the flip chip 121. In this embodiment, one end of the wire bonding structure 130 away from the grounding portion 111 is connected to the connection portion 125 on the upper surface of the flip chip 121, and the wire bonding structure 130 is soldered to the connection portion 125.
Step S400: after the wire bond structure 130 is formed, a protective paste 115 is filled between the electronic device 120 and the substrate 110. The protective adhesive 115 protects the first pad 123, the second pad 124, the wire bonding structure 130, and the like, and the protective adhesive 115 is an insulating adhesive. The routing structure 130 is beneficial to improving the filling property and fluidity of the protective adhesive 115, preventing the occurrence of voids, and reducing adverse effects caused by phenomena such as electron migration.
Step S500: a molding body 150 is formed on the substrate 110, and the molding body 150 encapsulates the electronic device 120, and protects the electronic device 120, the wire bonding structure 130, and the like. Solder balls 170 are planted on one side of the substrate 110 far from the plastic package body 150, and finally the plastic package body 150 and the substrate 110 are cut and separated into single products.
Referring to fig. 9, optionally, the step S200 of mounting the electronic device 120 on the substrate 110 includes:
step S210: mounting a flip chip 121 on a substrate 110; wherein the flip chip 121 is soldered to the ground 111.
Step S220: mounting a front-mounted chip 140 on the flip chip 121; wherein an adhesive layer 160 is disposed between the flip chip 121 and the front-mounted chip 140.
The wire bonding structure 130 is formed after step S210. Specifically, the step of forming the routing structure 130 by routing from the ground portion 111 includes: the wire bonding structure 130 is formed between the ground portion 111 and the adhesive layer 160. Alternatively, an end of the wire bonding structure 130 remote from the ground portion 111 extends above the flip chip 121 and is spaced apart from the upper surface of the flip chip 121. Step S220 is performed again, in which the adhesive layer 160 contacts the bonding structure 130 when the chip 140 is mounted.
Finally, plastic packaging, ball planting and cutting are carried out to form a single product.
Optionally, in some embodiments, the step of mounting the flip chip 121 on the substrate 110 includes: after the flip chip 121 is mounted, a metal wing layer 127 is formed on the sidewall of the flip chip 121; or the metal side wing layer 127 is formed on the flip chip 121 first, and then the flip chip 121 is attached to the substrate 110. The glue layer 160 is then overflowed when the chip 140 is mounted so that the glue layer 160 is electrically connected to the metal side wing layer 127. With this process, the step of forming the routing structure 130 by routing from the grounding portion 111 includes: a wire bond 130 is formed between the ground 111 and the metal shoulder layer 127.
Optionally, the step of forming the routing structure 130 by routing from the grounding portion 111 includes: the wire bonding structure 130 is higher than the flip chip 121, and an end of the wire bonding structure 130 away from the ground 111 is spaced apart from a surface of the flip chip 121 away from the substrate 110. The step of mounting the front-mounted chip 140 on the flip chip 121 includes: pressing the front-mounted chip 140 onto the flip-chip 121; wherein, one end of the wire bonding structure 130 far away from the grounding part 111 is pressed to one side surface of the flip chip 121 far away from the substrate 110; the side of the front-mounted chip 140, which is close to the flip-chip 121, is provided with a metal electrical connection layer 143, and the wire bonding structure 130 is electrically connected with the metal electrical connection layer 143.
The technical features of the above embodiments may be combined with or replaced with each other to form different embodiments, and are not particularly limited herein.
Other parts of the content not mentioned in this embodiment are similar to those described in the first embodiment, and will not be repeated here.
In summary, the chip packaging structure 100 and the chip packaging method provided by the embodiments of the present invention have the following beneficial effects:
according to the chip packaging structure 100 and the chip packaging method provided by the embodiment of the invention, the wire bonding structure 130 is distributed on the outer side of the electronic device 120 and higher than the upper surface of the electronic device 120 through wire bonding on the grounding part 111, so that static electricity around and on the surface of the electronic device 120 can be eliminated, and the phenomenon of electron migration of welding spots of the electronic device 120 under the conditions of bearing current density and rapidly increasing the working temperature of the welding spots is relieved, and adverse effects caused by the phenomenon of electron migration are reduced. The routing structure 130 also improves the heat dissipation performance of the chip package structure 100. In addition, the wire bonding structure 130 can promote the filling property and fluidity of the bottom protective adhesive 115, prevent the bottom protective adhesive 115 from breaking or generating voids, and is also beneficial to realizing electromagnetic shielding effect, and the wire bonding structure 130 can be used as a grounding end of a stacked product, so that the setting of the grounding end is reduced.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (15)
1. A chip package structure, comprising:
a substrate (110), wherein a grounding part (111) is arranged on the substrate (110);
an electronic device (120), the electronic device (120) comprising a flip chip (121) and a front-mounted chip (140), the flip chip (121) being electrically connected to the ground (111); the flip chip (121) is provided with a flip bump, and the flip bump is welded with the grounding part (111);
a wire bonding structure (130), wherein the wire bonding structure (130) is electrically connected with the grounding part (111), the wire bonding structure (130) is positioned at the outer side of the flip chip (121), and the normal chip (140) is arranged at one side of the flip chip (121) far away from the substrate (110); the front-mounted chip (140) is electrically connected with the substrate (110); one end of the wire bonding structure (130) far away from the grounding part (111) is higher than one side surface of the flip chip (121) far away from the substrate (110);
a protective adhesive (115) is arranged between the substrate (110) and the flip chip (121), the protective adhesive (115) at least partially covers the routing structure (130), and the protective adhesive (115) covers the grounding part (111);
an adhesive layer (160) is arranged between the front-mounted chip (140) and the flip chip (121); the side wall of the flip chip (121) is provided with a metal flank layer (127), the wire bonding structure (130) is connected to the metal flank layer (127), and the adhesive layer (160) is electrically connected with the metal flank layer (127).
2. The chip package structure according to claim 1, wherein the flip chip (121) includes a first pad (123), the first pad (123) being soldered with the ground (111);
one side of the flip chip (121) far away from the first bonding pad (123) is provided with a connecting portion (125), and one end of the wire bonding structure (130) far away from the grounding portion (111) is connected with the connecting portion (125).
3. The chip package structure according to claim 2, wherein the connection portion (125) includes at least one metal pad, and the wire bonding structure (130) is electrically connected to the at least one metal pad;
alternatively, the connection portion (125) includes a metal layer covering a side surface of the flip chip (121) remote from the substrate (110), and the wire bonding structure (130) is soldered to the metal layer.
4. The chip package structure according to claim 1, wherein the wire bonding structure (130) comprises a plurality of wire bonding structures (130) distributed around the flip chip (121).
5. The chip packaging structure according to claim 1, wherein the wire bonding structure (130) is soldered to the ground portion (111).
6. The chip packaging structure according to claim 1, wherein the adhesive layer (160) is a conductive adhesive or an insulating adhesive.
7. The chip packaging structure according to claim 1, wherein the wire bonding structure (130) is disposed at a periphery of the flip chip (121) and is spaced apart from the adhesive layer (160); alternatively, the wire bond structure (130) is connected to the glue layer (160).
8. The chip packaging structure according to claim 1, wherein a side of the front-mounted chip (140) close to the flip chip (121) is provided with a metal electrical connection layer (143), and the metal electrical connection layer (143) is electrically connected with the wire bonding structure (130).
9. The chip packaging structure according to claim 1, wherein a plastic package body (150) is disposed on the substrate (110), the plastic package body (150) encapsulates the electronic device (120), and the wire bonding structure (130) is exposed from the plastic package body (150).
10. The chip packaging structure according to claim 9, wherein a bending portion (131) is disposed at an end of the wire bonding structure (130) exposed out of the plastic package body (150).
11. A method of packaging a chip, comprising:
providing a substrate (110); the substrate (110) is provided with a grounding part (111);
mounting an electronic device (120) on the substrate (110); wherein the electronic device (120) comprises a flip chip (121) and a front-mounted chip (140), the flip chip (121) being electrically connected to the ground (111); the flip chip (121) is provided with a flip bump, and the flip bump is welded with the grounding part (111);
forming a wire bonding structure (130) from the grounding portion (111); wherein the wire bonding structure (130) is positioned at the outer side of the flip chip (121), and the front-mounted chip (140) is arranged at one side of the flip chip (121) away from the substrate (110); the front-mounted chip (140) is electrically connected with the substrate (110); one end of the wire bonding structure (130) far away from the grounding part (111) is higher than one side surface of the flip chip (121) far away from the substrate (110);
an adhesive layer (160) is arranged between the front-mounted chip (140) and the flip chip (121); the side wall of the flip chip (121) is provided with a metal flank layer (127), the wire bonding structure (130) is connected to the metal flank layer (127), and the adhesive layer (160) is electrically connected with the metal flank layer (127);
a protective adhesive (115) is arranged between the substrate (110) and the flip chip (121), the protective adhesive (115) at least partially covers the routing structure (130), and the protective adhesive (115) covers the grounding part (111).
12. The chip packaging method according to claim 11, further comprising:
after forming the wire bonding structure (130), a protective paste (115) is filled between the flip chip (121) and the substrate (110).
13. The chip packaging method according to claim 11, wherein the step of mounting an electronic device (120) on the substrate (110) comprises:
mounting a flip chip (121) on the substrate (110); wherein the flip chip (121) is soldered to the ground (111);
mounting a front-mounted chip (140) on the flip chip (121); wherein an adhesive layer (160) is arranged between the flip chip (121) and the normal chip (140);
the step of forming a wire bonding structure (130) from the ground portion (111) includes:
a wire bonding structure (130) is formed between the grounding portion (111) and the adhesive layer (160).
14. The chip packaging method according to claim 13, wherein the step of mounting a flip chip (121) on the substrate (110) includes:
forming a metal side wing layer (127) on the side wall of the flip chip (121);
the step of mounting the front-mounted chip (140) on the flip chip (121) includes: overflowing the adhesive layer (160) to be electrically connected with the metal flank layer (127) when the normal chip (140) is attached;
the step of forming a wire bonding structure (130) from the ground portion (111) includes: a wire bonding structure (130) is formed between the ground portion (111) and the metal side wing layer (127).
15. The chip packaging method according to claim 13, wherein the step of forming a wire bonding structure (130) from the ground portion (111) wire bonding includes:
the wire bonding structure (130) is higher than the flip chip (121), and one end of the wire bonding structure (130) away from the grounding part (111) is arranged at intervals with one side surface of the flip chip (121) away from the substrate (110);
the step of mounting the front-mounted chip (140) on the flip chip (121) includes:
pressing the front-mounted chip (140) onto the flip-chip (121); wherein, the one end of the wire bonding structure (130) far away from the grounding part (111) is pressed to the surface of one side of the flip chip (121) far away from the substrate (110); and a metal electric connection layer (143) is arranged on one side of the front-mounted chip (140) close to the flip chip (121), and the wire bonding structure (130) is electrically connected with the metal electric connection layer (143).
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| JPH07109867B2 (en) * | 1991-04-15 | 1995-11-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Cooling structure for semiconductor chips |
| JP3690342B2 (en) * | 2001-12-10 | 2005-08-31 | 凸版印刷株式会社 | Bonding wire and semiconductor device using the same |
| DE10204403A1 (en) * | 2002-02-04 | 2003-08-21 | Infineon Technologies Ag | Device for connecting an IC connection to a reference potential |
| CN1234158C (en) * | 2003-08-25 | 2005-12-28 | 威盛电子股份有限公司 | Manufacturing method of packaging base plate and its structure |
| DE10352946B4 (en) * | 2003-11-11 | 2007-04-05 | Infineon Technologies Ag | Semiconductor component with semiconductor chip and rewiring layer and method for producing the same |
| JP4140012B2 (en) * | 2004-02-06 | 2008-08-27 | ソニー株式会社 | Chip-shaped electronic component, manufacturing method thereof and mounting structure |
| DE102005062344B4 (en) * | 2005-12-23 | 2010-08-19 | Infineon Technologies Ag | Semiconductor component for high-frequency applications and method for producing such a semiconductor component |
| US20070164446A1 (en) * | 2006-01-13 | 2007-07-19 | Hawk Donald E Jr | Integrated circuit having second substrate to facilitate core power and ground distribution |
| TWI343611B (en) * | 2007-06-08 | 2011-06-11 | Orient Semiconductor Elect Ltd | Semiconductor package and method for discharging electronic devices on a substrate |
| US7838975B2 (en) * | 2008-05-27 | 2010-11-23 | Mediatek Inc. | Flip-chip package with fan-out WLCSP |
| US8000068B2 (en) * | 2008-10-27 | 2011-08-16 | Qualcomm Incorporated | ESD protection for field effect transistors of analog input circuits |
| KR101564070B1 (en) * | 2009-05-01 | 2015-10-29 | 삼성전자주식회사 | Printed circuit board and semiconductor package using the same |
| CN102522391B (en) * | 2011-12-31 | 2014-11-05 | 天水华天科技股份有限公司 | e/LQFP (low-profile quad flat package) stacked package with grounded ring and production method of e/LQFP stacked package with grounded ring |
| DE112018000762T5 (en) * | 2017-02-10 | 2019-12-19 | Microchip Technology Inc. | Grounding techniques for back-biased semiconductor chips and related devices, systems and methods |
| US20210035916A1 (en) * | 2019-07-29 | 2021-02-04 | Nanya Technology Corporation | Semiconductor package |
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