CN1101597C - Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same - Google Patents
Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same Download PDFInfo
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- CN1101597C CN1101597C CN96112063A CN96112063A CN1101597C CN 1101597 C CN1101597 C CN 1101597C CN 96112063 A CN96112063 A CN 96112063A CN 96112063 A CN96112063 A CN 96112063A CN 1101597 C CN1101597 C CN 1101597C
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Abstract
The present invention relates to a method for manufacturing an LOC package, which comprises a step depositing insulating liquid adhesive on a leading wire connection region formed on an active surface of a semiconductor in a wafer. The deposition of the adhesive can be realized by using a screen printing method in which the adhesive is caused to pass through hole patterns of a metal screen or by a dispensing method in which liquid adhesive is dispensed from needles of a dispensing head which moves on the wafer surface and is aligned with the wafer. In addition, in the dispensing method, the distribution can be applied to a plurality of chips step by step or once applied to a plurality of chips in large quantities, such as using a multi-pin dispensing head.
Description
The present invention relates to LOC (going between on the sheet) formula semiconductor die package and preparation method thereof.
In LOC formula semiconductor die package, semiconductor chip is connected to the lead end of lead frame rather than the press welding block of lead frame (being also referred to as " tube core press welding block ").Because the lead-in wire of lead frame must be electrically connected to semiconductor chip,, be formed with required circuit element and many electrode pressure welding pieces on the chip so the inner lead of lead frame is connected to the active surface of chip.Therefore lead-in wire is positioned at the chip top shown in Figure 1A.With reference to Figure 1A, copper alloy or ferroalloy lead wire frame 10 have inner lead 12, outside lead 14 and total line 16 (bus bars), and they are connected to the upper surface of semiconductor chip 20 by adhesive 30.Adhesive 30 is used for inner lead 12 and total line 16 be connected to and is formed with the active surperficial 24 of press welding block 22, and provides support to chip by lead frame in the chip mounting technique process.
Shown in Figure 1B, inner lead 12 and electrode pressure welding piece 22 are electrically connected by gold or aluminum steel 40.Total line 16 provides stable power for chip.When protectiveness packaging body 50 forms and outside lead 14 stretches out packaging body and forms suitable shape,, just obtained the encapsulation of LOC formula semiconductor chip as J-shaped.In the LOC technology, can improve the ratio of die size and package dimension, and therefore realize littler packaging.For example, in the standard packaging device, the ratio that chip size accounts for encapsulation is up to 60%, and in COL (chip is on lead-in wire) device, is up to 70%, and ratio can be up to 90% in the encapsulation of LOC formula.And can prevent that in LOC encapsulation because the device reliability variation that the difference (for example difference of the coefficient of expansion between packaging body and the lead frame) of physical property causes between the different materials, this is because do not use the lead frame press welding block.Because these advantages, the LOC encapsulation technology is extensively adopted by semiconductor production person now.
Usually adhesive 30 is based on the double-sided sticky tape of polyimides, but for example two-sided polyimide film that is coated with the epobond epoxyn of thermosetting, below described be its production technology.At first, the liquid-state viscosity material is deposited to equably a surface of polyimide film.The fluid binder of deposit is cured to B level (B-stage) (for example semisolid) adhesive.Deposit and curing schedule are also carried out in another surface at polyimides.The Kapton Tape of this adhesive deposit is made required width, is used for semiconductor chip is sealed to the tube core process for sealing of lead frame then.
Fig. 2 A to 2C shows the technology of using Kapton Tape semiconductor chip to be connected to lead frame.Lead frame 10 and adhesive tape 30 with inner lead 12 and total line 16 are heated to about 200 to 400 ℃ by heater 60, and by perforating press 70 their are pushed so that adhesive tape can be attached on the lead frame.Simultaneously, according to the shape of used lead frame, perforating press 70 cuts away unwanted tape portion.Then, semiconductor chip 20 is put on the heat block 80, Kapton Tape is connected to the active surface of chip.
Conventional LOC formula is packaged with following shortcoming: the first, and three strata acid imide adhesive tapes by the complicated production explained hereafter cause production cost to rise, and have the critical limit that reduces adhesive tape thickness.
Second, because adhesive tape is by using the machine tool such as perforating press to be connected to lead frame, the minimum dimension of adhesive tape is by the decision of the working limit of machine, and may form burr at adhesive tape punching edge, will cause the generation of some problems in follow-up assembly technology.
The 3rd, because Kapton Tape contacts several different materials, such as lead frame, semiconductor chip and plastic packaging body, in heat for example, the reliability testing carried out under the wet environment, the thermal stress that the mismatch of the TEC of different materials causes is the potential cause of component failure.In addition, when conventional LOC encapsulation was assembled on the external system plate by welding, because adhesive material and polyimide film have high water absorption character, packaging body can break.
Therefore, need exploitation to reduce the production cost of LOC formula encapsulation and reduce the size of adhesive and the method for thickness for the reliability that improves the encapsulation of LOC formula.
An object of the present invention is to provide a kind of method of producing low-cost LOC formula semiconductor die package.
Another object of the present invention is to improve the reliability of LOC formula semiconductor die package.
According to the manufacture method of LOC formula encapsulation of the present invention, when lead frame lead-in wire and chip sealing, do not use adhesive tape.But at semiconductor chip fully before the wafer-separate, adhesive is deposited to the active surface of semiconductor chip in wafer state.
In the adhesive depositing step, such as polyimides, epoxy resin, the electric insulation fluid binder of Polyimidesiloxane (polyimide siloxane) and polyetheramides (polyether amide) is deposited to the lead-in wire join domain that will place the active surface of chip of lead frame lead-in wire in future in the tube core process for sealing, and partly solidified then is B level adhesive phase.Excessive for the fluid binder that prevents deposit, the lead-in wire join domain is made the shape with groove.Groove lead-in wire join domain can obtain by using photo mask board, and photo mask board is originally and is used for making the electrode pressure welding piece in the protective layer upper shed that is formed at the entire wafer surface.
The deposit of wafer scale adhesive can be finished by the screen printing technology, the metal otter board that will have with lead-in wire join domain corresponding to required figure is pressed in wafer surface, use squeegee that fluid binder is pressed in the figure then, also can finish the pin hole distribution of fluid binder from ingredients head by ingredients technical, ingredients head moves on wafer surface and and wafer aligned.
In distribution, batching can be carried out many chips step by step, is perhaps undertaken by using spininess hole ingredients head to lump together.
Respectively the perspective view and the front cross-sectional view of conventional LOC formula chip-packaging structure shown in Figure 1A and the 1B;
Be to use the polyimide adhesive adhesive tape lead frame to be connected to the common process fragmentary cross-sectional view on the active surface of semiconductor chip shown in Fig. 2 A to 2C;
Fig. 3 is the manufacturing process flow diagram according to LOC formula Chip Packaging of the present invention;
Fig. 4 A is having the wafer surface of protective layer, according to the present invention, is used to out the perspective view of the photo mask board of electrode pressure welding piece and formation groove lead-in wire join domain;
Fig. 4 B is the photo mask board partial enlarged view with electrode pressure welding piece and lead-in wire join domain figure;
Fig. 4 C has finished the partial enlarged view that is used for the electrode pressure welding piece and the active surface of chip of the opening of the formation groove of lead-in wire join domain;
Fig. 5 is in the insulate perspective view of screen plate printing method of liquid adhesive material of the active surface deposition of chip at wafer scale;
Fig. 6 A is the semiconductor chip local zoomed-in view that is deposited with adhesive on it by screen plate printing method;
Fig. 6 B is the profile of Fig. 6 A of being as the criterion with line 6-6;
Fig. 7 is in the insulate perspective view of distribution of liquid adhesive material of the active surface deposition of chip at wafer scale;
Fig. 8 A and 8B are another embodiment according to distribution of the present invention;
Fig. 9 is the schematic diagram that has the tube core sealing maching of ingredients head 150; And
Figure 10 is the partial schematic diagram that the semiconductor chip from wafer-separate is sealed to the tube core process for sealing of lead frame alone.
The method that is used to make LOC formula Chip Packaging of the present invention is carried out according to processing step shown in Figure 3 substantially.In wafer fabrication step 100, make many semiconductor integrated circuit chips by batch process with required function and ability.The semiconductor chip of using in LOC formula encapsulation has the electrode pressure welding piece, and the electrode pressure welding piece is placed on the central area on the active surface that the lead frame lead-in wire connected.
Then wafer fabrication step 100 is in protective layer of wafer surface deposit in step 102.Protective layer can be the passivation layer of typical cover wafers, or the polyimide layer of one deck passivation layer and one deck covering passivation layer.Because the polyimides cover layer can effectively be protected active surface in the polished backside process that makes chip back surface ground connection for thinned wafer, and plays the part of the role who protects wafer surface in for the mold technology that forms packaging body, so obtained to use widely.In addition, have the polyimides cover layer, can significantly reduce the soft failure ratio (SER) that the α particle that sent by packaging body causes.Typical method is by the whirl coating method polyimide layer to be covered on the wafer.
When protective layer is deposited on the wafer; the necessary opening (opened) of the electrode pressure welding piece of semiconductor chip; because, can finish electrode pressure welding piece opening step 103 by using conventional photoetching method as chip will be connected with the lead-in wire of lead frame in wafer sealing-in step with the electrode pressure welding piece that the external world is electrically connected media.Simultaneously,, when forming electrode pressure welding piece opening,, on the active surface of chip, preferably open the lead-in wire join domain, make it have groove shapes, above adhesive material is deposited on according to the present invention with as described below.
In step 104, in deposit deposit adhesive layer on the lead-in wire join domain of wafer surface of protective layer, in step 105, from wafer, separate many semiconductor chips one by one.In step 106, the chip of separation is connected on the lead frame lead-in wire.The chip that separates is tube core, so step 106 is a tube core sealing-in step.Tube core sealing-in step of the present invention is not used any additional adhesive tape except the adhesive that uses deposit in step 104.
Technology then is similar to conventional packaging technology: lead bonding step 107 is used for electric connecting wire frame lead-in wire and chip electrode press welding block; Sealing step 108 is used to make the protection packaging body; And fine tuning and forming step 109, be used to cut and the lead-in wire of fine tuning packaging body with lead-in wire moulding remainder, and crooked lead portion of stretching out packaging body.
Fig. 4 A to 4C shows the groove lead-in wire join domain that forms on active surface according to the present invention.Grooved area is formed in the electrode pressure welding piece opening step 103 of Fig. 3.Obtain electrode pressure welding piece open area 124 and lead-in wire join domain 122 by using the photo mask board 110 that in conventional photoetching technique, uses usually.On a glass plate, form for example predefine pattern of chromium.These patterns comprise lead-in wire bonding pad pattern 112 and electrode pressure welding piece patterns of openings 114.Deposit photoresist on the wafer surface of the whole protective layer of deposit 128.Pattern mask plate 110 is placed on the wafer 120 and aims at it.When wafer surface is exposed in the light such such as UV light by mask plate, change according to mask plate pattern photoresist partial exposure and its chemical property.Wafer is immersed developer solution, and the part of change is removed, so expose the protective layer part.After the protective layer partial etching that exposes falls, lead-in wire join domain 122 and press welding block open area 124 shown in Fig. 4 C have just been obtained.Because lead-in wire join domain 122 has groove shapes, when on these zones 122, during the deposit adhesive, preventing overflowing of adhesive according to the present invention.Yet, it should be noted in the present invention groove lead-in wire join domain not necessarily, if therefore correct position, adhesive just can directly be deposited on the protective layer.
For on the predefine zone, just on the lead-in wire join domain of wafer scale on the active surface of chip, the deposit adhesive layer can adopt several method.Wherein, the whirl coating mode is that some fluid binders are dripped to wafer surface, and makes the wafer high speed rotating so that fluid binder is evenly distributed on the wafer surface.Although the whirl coating technology has the advantage of quick formation adhesive coverage layer, after adhesive solidifies, must form electrode pressure welding piece opening pretty troublesomely, this be because of adhesive coverage the entire wafer surface.Yet in order to guarantee the stable sealing-in between semiconductor chip and the lead frame, and for the active surface of protection chip in tube core sealing-in step process, require the adhesive phase of institute's deposit to have and surpass 30 microns thickness.Consequently time-consuming for the etching technics that forms electrode pressure welding piece opening.And cover the lip-deep thick adhesive phase meeting of entire wafer very lavishly owing to reducing reliability with other TCE mismatch such as silicon and package material.
Fig. 5 is the perspective view that is used to show screen plate printing method.Sheet metal web plate 130 has through-hole pattern, is deposited on the lead-in wire join domain that forms on the active surface of wafer 120 chips by through hole fluid binder 140.Web plate 130 also has the alignment mark (not shown) to be used for accurately aiming at wafer 120.After the aligning, web plate 130 contact wafer upper surfaces.At this moment, the lead-in wire join domain 122 on the wafer exposes by pattern 132.Along with fluid binder 140 is put on the web plate, by squeegee 134 is moved along the direction that arrow marks, adhesive just can be deposited to the lead-in wire join domain selectively.When the adhesive deposit finished, web plate was removed from wafer surface, and solidified the adhesive of deposit.Last structure is shown in Fig. 6 A and 6B.
Fig. 6 A is that Fig. 6 B is to be the profile of Fig. 6 A of benchmark with line 6-6 by the screen plate printing method partial enlarged drawing of the semiconductor chip 126 of deposit adhesive 142 thereon.
Adhesive is an electric insulation, and polyimides, epoxy resin, Polyimidesiloxane or polyetheramides can be selected as such insulating binder.Requirement is such as viscosity, and the operating characteristic of adhesives such as thixotropy and curing time is stable and consistent as far as possible.The curing time of epobond epoxyn is higher a little.
Because screen plate printing method once allows to use adhesives at many lead-in wire join domains, the adhesive that is used for this technology must be supported the operating time over a long time on web plate, so that neither need frequent draping plate, also do not need frequent clean.Adhesive must carefully design and make it fine work on web plate, and, perhaps causes stringing (stringing) not with excessive air seal not inside.
When screen printing, the shape and size of the adhesive of deposit can be controlled at an easy rate by changing the web plate through-hole pattern, make and can avoid in the encapsulation of LOC formula because of using the problem of conventional polyimide adhesive adhesive tape generation.When single web plate is applied successively to several wafer, must remove the part adhesive that sticks in the web plate back side.And necessary handled wafer in the packaging technology of following, this is because the adhesive phase of deposit forms the on-plane surface wafer surface inevitably, may cause breaking of wafer in chip back surface adhesive tape installation step.
Fig. 7 shows the adhesive deposit perspective view that adopts distribution.The wafer 120 that is supported by wafer ring 160 is assembled on the xy workbench 170, and workbench can move at x and y direction.Ingredients head 150 comprises pipe 154, is used to provide fluid binder 156; Irrigator 158 is used to keep a certain amount of adhesive; And some pins 152, be used for dispense adhesive on wafer 120.
As previously described, adhesive can be a kind of insulating material, for example polyimides, epoxy resin, Polyimidesiloxane and polyetheramides.The position of the lead-in wire join domain on the active surface of chip can be by the identification of optical system (not shown), and this recognition data can be used in the driven tool such as impulse motor or servo motor of control xy workbench 170, thereby aims at ingredients head.On correct position, ingredients head is reduced to wafer surface, and air pulse drives the lead-in wire join domain that some fluid binders are deposited to semiconductor chip from needle section.Ingredients head moves on by mobile xy workbench 170, and aims at next semiconductor chip.Air pressure can be used for controlling the distribution of the adhesive of through hole pin.
Simultaneously, if make groove shapes, just may prevent overflowing of the adhesive that distributes with reference to Fig. 4 C join domain 124 that goes between as previously described.
Adopt distribution, relative screen plate printing method, irrelevant with the size or the thickness of wafer, can guarantee more stable wafer control, this is just not finished the adhesive deposit because contact between ingredients head and wafer surface.In addition, the position of adhesive dispense, size is such as width, length, and the thickness of the adhesive of deposit can be by changing the diameter of pin, the translational speed of ingredients head and regulate air pressure and control easily.Therefore, according to structure and reliability, the encapsulation of LOC formula can be optimized.
Above-described distribution not only can once be applied to a chip, also can distribute insulating binder in once a large amount of modes.For example, shown in Fig. 8 A, in case ingredients head 150 descend, it from an end motion of wafer to the other end, so that adhesive is distributed according to the linear formula of length of label 156a mark.Perhaps shown in Fig. 8 B, if be equipped with a plurality of pin 152a to 152d on a single ingredients head 180, adhesive just can be deposited to the lead-in wire join domain of several semiconductor chips simultaneously.Once the distribution of a large amount of modes can guarantee that for all chips in the wafer, the thickness of adhesive is uniform.Even the long line mode of adhesive employing is distributed and solidified, adjacent chips also can be separated without a doubt at an easy rate, because used the scriber such as the diamond wheel of high speed rotating in the wafer segmentation procedure.
The distribution of adhesive can realize by using special-purpose proportioning machine.Such machinery requirement comprises driving arrangement, is used for moving the workbench that assembles wafer at x and y direction, and position-recognizing system, be used for ingredients head and aim at the accurate of lead-in wire join domain on the active surface of chip.Simultaneously, provide xy workbench that has the wafer that can move assembling and the conventional tube core sealing maching that is used for selecting the optical system of certain chip from wafer.Therefore, if wish and ingredients head can be combined with conventional tube core sealing maching, just can save the time and the cost that are used for the special batching machine.
Fig. 9 is the schematic diagram that has the tube core sealing maching of ingredients head.Passed through wafer fabrication steps (100 among Fig. 3); passivation layer forms step 102 and forms the step 103 of electrode pressure welding piece opening; further through the chip back surface polishing, protective tapes assembling and wafer are cut apart the step of (being scribing) again, and wafer 120 is fixed on the wafer ring 160.Although wafer 120 scribings are divided into single semiconductor chip, the protected adhesive tape 220 of these chips supports.When encircling 192 by being assembled to the wafer 120 on the expansion workbench 190, when making adhesive tape 220 expansions, the chip after the scribing is separated from each other certain distance.Expansion workbench 190 is incorporated into can be on the xy workbench 200 of x and the motion of y direction.Optical system 240 has camera 242, for example CCD (charge coupled device) camera, and monitor 244.Camera 242 picks up the position that is distributed in the chip in the wafer, and positional information is sent to display monitor central monitoring system 244.Display monitor central monitoring system 244 can display chip the position, these positional informations are used for the CD-ROM drive motor (not shown) of controlling and driving xy workbench 200 and make pick tool 230 and ingredients head 150 and wafer aligned.
After the adhesive tape expansion finished, ingredients head 150 was put on the wafer 120 and with it and aims at.Be retained in iknsulating liquid adhesive in the irrigator 158 under the air-pressure controlling that comes from air supply pipe 155,, be assigned on the lead-in wire join domain by pin 152.Distribution can be applied to semiconductor chip successively or once be widely used in several chips.
Usually in EDS (chip select of electricity tube core) test, with ink dot mark chip failing on wafer.When the distribution of each semiconductor chip of optical identification wafer in the adhesive deposit was used, adhesive can only be deposited on the non-chip failing, has prevented the waste of adhesive.
In adhesive dispense with after solidifying, have the most advanced and sophisticated crowded thruster 210 that pushes away the post (not shown) that squeezes and shift to position P1, and on push away selected chip, make it and adhesive tape 220, promptly wafer 120, fully separation.The chip that separates is sent to the die package position by pick tool 230.
Figure 10 is the chip sealing that will the separate tube core process for sealing partial view to lead frame.Lead frame 280 moves along guide rail 270 according to the direction that is marked as arrow A 1.Lead frame 280 has inner lead 282, outside lead 284 and total line 286, and inner lead and total line part are sealed to separating chips 290 by using the chip 290 active lip-deep adhesives 156 that are deposited to according to the present invention.
The semiconductor chip 290 that pick tool 230 carries separation moves along A2, then chip is placed on the tube core sealing-in position of heat block 260.Heat block 260 can moving up and down as the A4 mark.When lead frame arrives tube core sealing-in position, tube core sealing joint 250 and heat block hot pressing lead frame lead-in wire and the active surface of chip.For the conventional criteria packaging, will drip on lead frame in the P2 position such as the adhesive of silver epoxy (silver epoxy), but LOC formula of the present invention encapsulation, adhesive 156 has been formed at the lead-in wire join domain on the active surface of chip.
Above-mentioned to of the present invention open with describe be most preferred embodiment intuitively, illustrative description, therefore have the people of general technology in the art, might change and revise and do not deviate from scope and spirit of the present invention embodiment.
Claims (12)
1. method that is used to make lead type semiconductor die package on the sheet, the step that described method comprises is:
Wafer with upper surface is provided, is formed with many semiconductor chips on its upper surface, each described this semiconductor chip has the active surface that many electrode pressure welding pieces are placed at center on it;
The deposit protective layer is to the upper surface of wafer;
The deposit insulating binder is to the described channel form lead-in wire join domain of the electrode pressure welding piece both sides that are positioned at central authorities' placement;
From the described many semiconductor chips of wafer-separate;
Tube core sealing-in step, be used for by using the deposit insulating binder that the inner lead of lead frame partly is connected to the lead-in wire join domain, the described lead frame with lead-in wire is used to support the semiconductor chip of separation and the separating semiconductor chip is electrically connected to the external circuit device;
The inner lead of lead frame partly is electrically connected to many electrode pressure welding pieces of the semiconductor chip of separation; And
Form the protection packaging body, the substep that the step of wherein said deposit adhesive comprises is:
Wafer is assembled on the xy workbench that can move in the direction of x and y;
Aim at ingredients head on wafer, described ingredients head comprises the adhesive supply pipe, keeps the irrigator of a certain amount of fluid binder that comes the Autoadhesive supply pipe and the pin by its dispense adhesive;
On the lead-in wire join domain of the semiconductor chip on the wafer, distribute fluid binder; And
Solidify the adhesive that distributes.
2. method that is used to make lead type semiconductor die package on the sheet, the step that described method comprises is:
Wafer with upper surface is provided, is formed with many semiconductor chips on its upper surface, each described this semiconductor chip has the active surface that many electrode pressure welding pieces are placed at center on it;
The deposit protective layer is to the upper surface of wafer;
The deposit insulating binder is to the described channel form lead-in wire join domain of the electrode pressure welding piece both sides that are positioned at central authorities' placement;
From the described many semiconductor chips of wafer-separate;
Tube core sealing-in step, be used for by using the deposit insulating binder that the inner lead of lead frame partly is connected to the lead-in wire join domain, the described lead frame with lead-in wire is used to support the semiconductor chip of separation and the separating semiconductor chip is electrically connected to the external circuit device;
The inner lead of lead frame partly is electrically connected to many electrode pressure welding pieces of the semiconductor chip of separation; And
Form the protection packaging body,
Wherein before the lead-in wire join domain, comprise a step adhesive tape installation step at the deposit adhesive, be used to assemble the back side of protective tapes to wafer, an and step scribing step, be used for the wafer that adhesive tape assembles being carried out scribing, and the substep that the step of wherein said deposit adhesive comprises is along the scribe line that defines between the adjacent semiconductor chip on the wafer; The assembling wafer is to the xy workbench that can move along x and y direction; Aim at ingredients head on wafer, described ingredients head comprises the adhesive supply pipe, keeps the irrigator of a certain amount of fluid binder that comes the Autoadhesive supply pipe and the pin by its dispense adhesive; On the lead-in wire join domain of wafer semiconductor chip, distribute fluid binder; And the adhesive that solidifies distribution.
3. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1 or 2, the step of wherein said deposit protective layer are included in the step that forms the opening that exposes described a plurality of electrode pressure welding pieces and channel form lead-in wire join domain in the described protective layer.
4. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1 or 2, the substep that the step of wherein said deposit protective layer comprises is: with the upper surface whirl coating of liquid polyimides at wafer; Expose and described electrode pressure welding piece of opening and lead-in wire join domain; The photo mask board of the figure with electrode pressure welding piece and lead-in wire join domain is provided; The deposit photoresist is on the polyimides that covers; Use photo mask board exposure and development photoresist; And the opening of etching and formation electrode pressure welding piece and lead-in wire join domain.
5. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1 or 2, the inner lead part of wherein said electric connecting wire frame to the step of a plurality of electrode pressure welding pieces is lead bonding steps.
6. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1 or 2, wherein said insulating binder is selected from by polyimides, and epoxy resin is in the group that Polyimidesiloxane and polyetheramides constitute.
7. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1, the lead-in wire join domain of wherein said semiconductor chip are removed protective layer formation by selectivity and are had the shape of groove.
8. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1, wherein said step of distributing fluid binder by pin is applied to a plurality of semiconductor chips on the wafer in step by step mode.
9. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1, wherein said step of distributing fluid binder by pin is applied to be positioned on the wafer some semiconductor chips with delegation or same row at synchronization.
10. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 1, wherein said ingredients head comprises a plurality of pins, the step by described a plurality of pin dispense adhesive is applied to several semiconductor chips simultaneously.
11. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 2; wherein said chip separating step is to push away selecteed specific semiconductor chip on the wafer on the xy workbench from being assemblied in, so that make selecteed semiconductor chip separate from the protective tapes at chip back surface.
12. the method that is used to make lead type semiconductor die package on the sheet as claimed in claim 2, the step of wherein said distribution fluid binder comprise the markers step on the identification wafer semiconductor-on-insulator chip and are not selectively having to distribute fluid binder on the semiconductor chip of mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96112063A CN1101597C (en) | 1996-11-08 | 1996-11-08 | Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96112063A CN1101597C (en) | 1996-11-08 | 1996-11-08 | Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1182282A CN1182282A (en) | 1998-05-20 |
| CN1101597C true CN1101597C (en) | 2003-02-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96112063A Expired - Fee Related CN1101597C (en) | 1996-11-08 | 1996-11-08 | Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same |
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| Country | Link |
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| CN (1) | CN1101597C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102024671B (en) * | 2009-09-11 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | Screen and method for forming protective layer on back of wafer |
| CN104461130A (en) * | 2014-11-19 | 2015-03-25 | 业成光电（深圳）有限公司 | Panel treating method |
| CN105096046A (en) * | 2015-07-29 | 2015-11-25 | 北京科信华技术有限公司 | Tool with identity information, method for manufacturing tool, and tool system |
| CN109749404A (en) * | 2019-01-12 | 2019-05-14 | 莫爱军 | A kind of high-temperature stability electronic packaging composite material of high heat conductance and preparation method thereof |
| CN112670192A (en) * | 2020-12-25 | 2021-04-16 | 苏州科阳半导体有限公司 | Wafer level packaging process and wafer level packaging structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778910A (en) * | 1993-09-07 | 1995-03-20 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| CN1108810A (en) * | 1993-09-28 | 1995-09-20 | 国家淀粉及化学投资控股公司 | A method for applying adhesive to microelectronic chips |
-
1996
- 1996-11-08 CN CN96112063A patent/CN1101597C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778910A (en) * | 1993-09-07 | 1995-03-20 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| CN1108810A (en) * | 1993-09-28 | 1995-09-20 | 国家淀粉及化学投资控股公司 | A method for applying adhesive to microelectronic chips |
Also Published As
| Publication number | Publication date |
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| CN1182282A (en) | 1998-05-20 |
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