JPH05291260A - Forming method for bump - Google Patents

Forming method for bump

Info

Publication number
JPH05291260A
JPH05291260A JP4088802A JP8880292A JPH05291260A JP H05291260 A JPH05291260 A JP H05291260A JP 4088802 A JP4088802 A JP 4088802A JP 8880292 A JP8880292 A JP 8880292A JP H05291260 A JPH05291260 A JP H05291260A
Authority
JP
Japan
Prior art keywords
bump
electrode
bumps
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4088802A
Other languages
Japanese (ja)
Inventor
Mamoru Sasaki
衛 佐々木
Tomoaki Takubo
知章 田窪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4088802A priority Critical patent/JPH05291260A/en
Publication of JPH05291260A publication Critical patent/JPH05291260A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PURPOSE:To inexpensively form bumps having a fast forming time and uniform height only in many types of semiconductor integrated circuit chips of non- defective product by using a heater block vertically movable in a bonding tool. CONSTITUTION:A protrusion electrode 3 for connecting an electrode pad 4 on a semiconductor integrated circuit chip 5 to a substrate and a semiconductor device (package) is easily formed by using a heater block 2 vertically movable in a bonding tool 1. For example, the electrode 3 is formed by punching a material of Au, Sl, solder, etc., of a ribbon state having a thickness of about 10-50mum by the tool 1. Further, for example, the formed electrode 3 is formed by heating the electrode 3 moved down in the tool 1 by the vertically movable block 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路チップ
を半導体装置及び半導体基板への実装時に用いる接合用
突起電極の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bonding projection electrode used when mounting a semiconductor integrated circuit chip on a semiconductor device and a semiconductor substrate.

【0002】[0002]

【従来の技術】近年、半導体集積回路の分野では、大集
積化が進められており、入出力信号や電源電圧を供給す
るためのパッド数は益々増大し、動作速度の迅速化は進
む一方である。
2. Description of the Related Art In recent years, in the field of semiconductor integrated circuits, large-scale integration has been promoted, and the number of pads for supplying input / output signals and power supply voltage has been increasing more and more, while operating speed has been accelerated. is there.

【0003】このように高密度に集積化された半導体集
積回路の実装に際しては、パッド数の増大に伴い、バッ
ドピッチの縮小化がはかられている。しかし、従来のワ
イヤボンディング技術では、そのピッチは100μmが
限界であり、またパッド数の増大に伴うワイヤボンディ
ングに要する時間の増大も大きな問題となっている。
In mounting a semiconductor integrated circuit that is highly integrated as described above, the pad pitch is being reduced as the number of pads is increased. However, in the conventional wire bonding technique, the pitch is limited to 100 μm, and the increase in the time required for wire bonding due to the increase in the number of pads is also a serious problem.

【0004】そこで、このような問題点を解決するた
め、長尺状の可撓性フィルム基板上に金属箔配線を形成
し、これと電極パッドに突起電極を形成した半導体集積
回路チップとを接続するTAB(Tape Autom
ated Bonding)技術が提唱され、開発が進
められている。
Therefore, in order to solve such a problem, metal foil wiring is formed on a long flexible film substrate, and this is connected to a semiconductor integrated circuit chip having a protruding electrode formed on an electrode pad. TAB (Tape Autom)
The aged bonding technology has been proposed and is being developed.

【0005】しかしながら、フィルムキャリアと半導体
集積回路チップとの接続に用いられる突起電極(バン
プ)の形成方法は数種類あるが形成方法が容易で低コス
トしかも多品種対応という形成方法は見受けられない。
バンプ形成方法の代表的な例として (1)めっきバンプ方式 電極パッド上に多層のバリアメタルを介し、めっきによ
り金(Au)バンプまたは蒸着による半田バンプを形成
するめっきバンプ方式がある。図6は、めっきバンプ方
式のプロセスを示す工程図である。
However, although there are several methods of forming the bump electrodes (bumps) used for connecting the film carrier and the semiconductor integrated circuit chip, there is no method for forming the bump electrodes which is easy, low cost and compatible with a wide variety of products.
Typical examples of the bump forming method are (1) plating bump method, which is a plating bump method in which a gold (Au) bump or a solder bump by evaporation is formed on the electrode pad through a multi-layer barrier metal by plating. FIG. 6 is a process diagram showing a plating bump method process.

【0006】図6(a)は金属膜の被着工程であり、図
6(b)でバンプ形成のためのフォトリソグラフィ工程
を行い、フォトレジストによるめっき用パターンを形成
する。金属膜を一方の電極とし、図6(c)電解めっき
法によりパターン内にバンプを形成させる。そして図6
(d)で不要となったフォトレジストを除去し、図6
(e)で新たにバンプ上からフォトレジストを塗布し、
バリアメタルをエッチングするためのパターンを形成す
る。このフォトリソグラフィ工程では、マスク露光は、
バンプを介して行うため、高解像度を得ることができな
い。レジストパターンはバンプを含み、バンプ周縁を覆
うように形成させる。このレジストパターンをマスクと
して、ウェハ上の露出している全てのバリアメタルをエ
ッチング除去し、最後に図6(f)でレジストパターン
を除去する。
FIG. 6A shows a metal film deposition step. In FIG. 6B, a photolithography step for forming bumps is performed to form a plating pattern with a photoresist. Using the metal film as one electrode, bumps are formed in the pattern by the electrolytic plating method shown in FIG. 6C. And FIG.
The unnecessary photoresist in (d) is removed, and FIG.
In (e), a new photoresist is applied on the bumps,
A pattern for etching the barrier metal is formed. In this photolithography process, mask exposure is
Since it is performed via bumps, high resolution cannot be obtained. The resist pattern includes bumps and is formed so as to cover the periphery of the bumps. Using this resist pattern as a mask, all exposed barrier metal on the wafer is removed by etching, and finally the resist pattern is removed in FIG. 6 (f).

【0007】以上の様にめっきバンプ方式はプロセス時
にバンプを形成するので容易にバンプ形成は困難で良
品、不良品問わずバンプを形成してしまい時間及びコス
トが高くなってしまうという問題点がある。 (2)転写バンプ方式
As described above, in the plating bump method, since bumps are formed during the process, it is difficult to form bumps easily, and bumps are formed regardless of whether they are non-defective products or defective products, resulting in high time and cost. .. (2) Transfer bump method

【0008】図7は、転写法によるバンプ形成方法のプ
ロセス図である。チップ13のアルミ電極14とバンプ
形成用基板上16のバンプ15とを位置合わせし、チッ
プ13とバンプ15とを加熱・加圧させ、Au・Al合
金を形成させた後、チップ13を引き上げるとバンプ形
成用基板上16のバンプは、チップ13のアルミ電極上
14に剥離、接合される。しかし、転写するバンプの数
が増大するとパッドピッチが狭くなりバンプとパッドと
の位置合わせが難しくなってくる。 (3)ボールバンプ方式
FIG. 7 is a process diagram of a bump forming method by a transfer method. When the aluminum electrode 14 of the chip 13 and the bump 15 on the bump forming substrate 16 are aligned, the chip 13 and the bump 15 are heated / pressurized to form an Au / Al alloy, and then the chip 13 is pulled up. The bumps on the bump forming substrate 16 are separated and joined to the aluminum electrodes 14 on the chip 13. However, as the number of bumps to be transferred increases, the pad pitch becomes narrower and it becomes difficult to align the bumps and pads. (3) Ball bump method

【0009】図8は、ワイヤボンディング方式のボール
ボンディングでバンプを形成する方法を示す工程図であ
る。キャピラリ17の先端のAu線18にボールを形成
し、これを超音波を印加しながら、アルミ電極19上に
ボンディングする。次にボンディングした状態で、キャ
ピラリ17をそのまま横すべりさせ、ボール18のネッ
クでAuワイヤを切断させる。
FIG. 8 is a process chart showing a method of forming bumps by wire bonding type ball bonding. A ball is formed on the Au wire 18 at the tip of the capillary 17, and this is bonded onto the aluminum electrode 19 while applying ultrasonic waves. Next, in the bonded state, the capillary 17 is slid as it is, and the Au wire is cut by the neck of the ball 18.

【0010】この方式の課題として、電極の数だけバン
プ形成に時間を費やすこととバンプの不整にある。仮に
300電極を有するチップでは、60秒を要してしま
う。このために、ごくわずかな数チップを処理するのに
は適しているが、少なくとも量産向きではないし、量産
してもボンディング速度が常に一定であるので、バンプ
形成コストは安くならない。また、バンプ形成時に、高
温状態で少なくとも数10秒間放置されるためにパープ
ルプレーグの発生も考えられ、そしてワイヤー残りが発
生し均一なバンプ形成が困難である。 (4)メサバンプ方式
The problem with this method is that it takes time to form bumps for the number of electrodes and that bumps are irregular. If the chip has 300 electrodes, it takes 60 seconds. For this reason, it is suitable for processing a very small number of chips, but it is not suitable for mass production at least, and the bonding speed is always constant even after mass production, so the bump forming cost is not reduced. Further, when the bumps are formed, they may be left at a high temperature for at least several tens of seconds, so that it is possible that purple plague is generated, and wire remains are generated, which makes it difficult to form uniform bumps. (4) Mesa bump method

【0011】図9はメサバンプの断面図である、70μ
m厚の銅箔をエッチング加工し、リードの先端部分でL
SIチップのアルミ電極と接する領域に凸起20を形成
する。すなわち、インナーリード21に相当する部分で
先端のみを残し、他は35μm程度、エッチングしてし
まう。
FIG. 9 is a sectional view of the mesa bump, 70 μ.
Etching a copper foil of m thickness, L at the tip of the lead
The protrusion 20 is formed in a region of the SI chip that is in contact with the aluminum electrode. That is, only the tips are left in the portion corresponding to the inner leads 21, and the other portions are etched by about 35 μm.

【0012】メサバンプの特徴は、リード側にバンプを
形成しておくために、LSIチップのアルミ電極上への
処理が必要でないことである。ところが、単位接合面積
あたりの接合強度が低い及び極端に精度の高い平行度が
必要などといった課題がある。
A feature of the mesa bump is that it is not necessary to process the aluminum electrode of the LSI chip in order to form the bump on the lead side. However, there are problems such as low bonding strength per unit bonding area and extremely high parallelism required.

【0013】[0013]

【発明が解決しようとする課題】このように、半導体集
積回路チップ上の電極パッドにフィルムキャリア接続用
のバンプ形成を行う場合、バンプ形成が容易でしかも良
品チップのみに安定したバンプ形成を行うことが、不可
能であった。本発明は、前記バンプ形成方法とは形成方
法が異なり、安定したバンプを容易に供給することを目
的とする。
As described above, when bumps for film carrier connection are formed on the electrode pads on the semiconductor integrated circuit chip, bump formation is easy and stable bumps are formed only on non-defective chips. But it was impossible. The present invention is different from the above bump forming method in the forming method, and an object thereof is to easily supply stable bumps.

【0014】[0014]

【課題を解決するための手段】本発明では、ツールの内
部に昇降可能なヒーターブロックを有するボンディング
ツールを用いAu,Al,半田等を厚さ10μm〜50
μmのリボン状にした金属薄膜を、ヒーターブロックに
より加熱されたボンディングツールで半導体集積回路チ
ップの電極パッドに加圧することによりリボン状の金属
薄膜を打ち抜きバンプを形成する。この時、半導体集積
回路チップの電極パッドへのボンディングツールの位置
合わせは位置認識用カメラで精度良く位置合わせを行っ
ておく。
According to the present invention, a bonding tool having a heater block capable of moving up and down is used in the tool, and Au, Al, solder or the like having a thickness of 10 μm to 50 μm is used.
The ribbon-shaped metal thin film is punched out by pressing the ribbon-shaped metal thin film on the electrode pad of the semiconductor integrated circuit chip with a bonding tool heated by a heater block. At this time, the positioning of the bonding tool to the electrode pad of the semiconductor integrated circuit chip is performed with high accuracy by a position recognition camera.

【0015】バンプが半導体集積回路チップの電極パッ
ドに形成された後、ツール内のヒーターブロックが降下
してきてバンプを加熱することにより、電極パッドに形
成されていたバンプの形状を整える。
After the bumps are formed on the electrode pads of the semiconductor integrated circuit chip, the heater block in the tool descends to heat the bumps, thereby adjusting the shape of the bumps formed on the electrode pads.

【0016】[0016]

【作用】上記バンプ形成方法を用いれば、バンプ形成を
行う半導体集積回路チップの品種が変わっても、特性評
価後の半導体集積回路チップ良品のみに安価で容易にし
かもバンプ形成が一定であるバンプを形成することが可
能である。
According to the above bump forming method, even if the type of the semiconductor integrated circuit chip on which the bump is formed is changed, only the good semiconductor integrated circuit chip after the characteristic evaluation can be inexpensively and easily provided with the bump formed uniformly. It is possible to form.

【0017】[0017]

【実施例】以下本発明の実施例について図面を参照しつ
つ詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

【0018】図1a〜eは本発明実施例のバンプ形成方
法の断面図である。あらかじめ位置認識用カメラ22で
電極4の位置をマシン本体に登録しておく。図1aは位
置決めされた電極4の上方に、内部に昇降可能なヒータ
ーブロック2が入っているボンディングツール1が来ま
す、この時ボンディングツールの金属薄膜接触面よりも
奥にヒーターブロックが位置することを特徴とする。そ
して、ボンディングツール1と電極4の間にはリボン状
になっている金属薄膜3がある。図1bで内部のヒータ
ーブロックで加熱されたボンディングツール1が下降し
金属薄膜3に接触します。次に図1cのように金属薄膜
3接触後もボンディングツール1が下降し続けると金属
薄膜3と打ち抜き電極4に接着します。電極4にボンデ
ィング1が接着後ヒーターブロック2が下降してきて、
電極4に接着された金属薄膜3を加圧することにより電
極4と金属薄膜3の接着強度を上げ形を整形する。最後
にヒーターブロック2が上昇しバンプ形成が終了し、ボ
ンディングツール1が次の電極位置に移動しバンプ形成
を行う。図2は本発明実施例の斜視図である。次に、本
発明の第2の実施例について説明する。
1a to 1e are sectional views of a bump forming method according to an embodiment of the present invention. The position of the electrode 4 is registered in the machine body in advance by the position recognition camera 22. In Fig. 1a, a bonding tool 1 having a heater block 2 which can be moved up and down is located above the positioned electrode 4, and at this time, the heater block should be positioned deeper than the metal thin film contact surface of the bonding tool. Is characterized by. Then, between the bonding tool 1 and the electrode 4, there is a ribbon-shaped metal thin film 3. In Fig. 1b, the bonding tool 1 heated by the internal heater block descends and contacts the metal thin film 3. Next, as shown in Fig. 1c, when the bonding tool 1 continues to descend even after the contact with the metal thin film 3, it adheres to the metal thin film 3 and the punching electrode 4. After bonding the bonding 1 to the electrode 4, the heater block 2 descends,
By pressing the metal thin film 3 adhered to the electrode 4, the adhesive strength between the electrode 4 and the metal thin film 3 is increased and the shape is shaped. Finally, the heater block 2 rises to complete bump formation, and the bonding tool 1 moves to the next electrode position to form bumps. FIG. 2 is a perspective view of an embodiment of the present invention. Next, a second embodiment of the present invention will be described.

【0019】図3a〜dは実施例2の断面図である、透
明な基板6、例えば熱伝導率の良いアルミナ基板に電極
4の位置と同じ位置に低融点半田をめっき法によりバン
プを形成しておく。
3A to 3D are sectional views of the second embodiment. A bump is formed by plating a low melting point solder on the transparent substrate 6, for example, an alumina substrate having good thermal conductivity, at the same position as the electrode 4. Keep it.

【0020】この基板をバンプ形成面を裏面にして半導
体集積回路チップ5の上方に置く、この時、基板6は透
明なので基板6に形成したバンプと半導体集積回路チッ
プ5の電極4の位置合わせが容易に行うことができる、
ここでは位置認識用のカメラ22で基板6のバンプと半
導体集積回路チップ5の電極4の位置合わせを行う、位
置合わせ終了後バンプの位置に加熱されたボンディング
ツール1が基板6の上方より降下して基板6のバンプ形
成位置を加熱することにより、バンプは電極4に形成さ
れる。
This substrate is placed above the semiconductor integrated circuit chip 5 with the bump forming surface as the back surface. At this time, since the substrate 6 is transparent, the bumps formed on the substrate 6 and the electrodes 4 of the semiconductor integrated circuit chip 5 are aligned with each other. Easy to do,
Here, the position recognition camera 22 aligns the bumps of the substrate 6 with the electrodes 4 of the semiconductor integrated circuit chip 5, and after the alignment is completed, the bonding tool 1 heated to the position of the bump descends from above the substrate 6. The bumps are formed on the electrodes 4 by heating the positions where the bumps are formed on the substrate 6.

【0021】図4は実施例2の斜視図である。図5は本
発明で用いられるボンディングツールであり、Aのボン
ディングツールは先端が平になっており、Bのボンディ
ングツールは先端が丸みをおびている。
FIG. 4 is a perspective view of the second embodiment. FIG. 5 shows a bonding tool used in the present invention. The bonding tool A has a flat tip, and the bonding tool B has a rounded tip.

【0022】[0022]

【発明の効果】以上説明してきたように、本発明を用い
てバンプ形成を行うと、多品種の半導体集積回路チップ
の良品のみに、形成時間が速く高さが均一なバンプを安
価に形成できることができる。
As described above, when bumps are formed by using the present invention, it is possible to inexpensively form bumps having a high formation time and a uniform height only on non-defective products of various kinds of semiconductor integrated circuit chips. You can

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1のバンプ形成方法断面図。FIG. 1 is a sectional view of a bump forming method according to a first embodiment of the present invention.

【図2】 本発明の実施例1のバンプ形成方法斜視図。FIG. 2 is a perspective view of the bump forming method according to the first embodiment of the present invention.

【図3】 本発明の実施例2のバンプ形成方法断面図。FIG. 3 is a sectional view of a bump forming method according to a second embodiment of the present invention.

【図4】 本発明の実施例2のバンプ形成方法斜視図。FIG. 4 is a perspective view of a bump forming method according to a second embodiment of the present invention.

【図5】 本発明に用いられるボンディングツールの形
成を示す外観図。
FIG. 5 is an external view showing formation of a bonding tool used in the present invention.

【図6】 従来例1のめっきバンプ方式を示す工程図。FIG. 6 is a process diagram showing a plating bump method of Conventional Example 1.

【図7】 従来例2の転写バンプ方式を示す工程図。FIG. 7 is a process diagram showing a transfer bump method of Conventional Example 2.

【図8】 従来例3のボールバンプ方式を示す工程図。FIG. 8 is a process diagram showing a ball bump method of Conventional Example 3;

【図9】 従来例4のメサバンプ方式を示す一部側面
図。
FIG. 9 is a partial side view showing a mesa bump method of Conventional Example 4.

【符号の説明】[Explanation of symbols]

1…ボンディングツール 2…ヒーターブロック 3…金属薄膜 4…電極 5・13…半導体集積回路チップ 6…透明な基板 7・14・19…電極パッド 8…バリアメタル 9…保護膜 10・12…フォトレジスト 11・15…バンプ 16…バンプ形成用基板 17…キャピラリイ 18…ワイヤ 20…凸起 21…インナーリード 22…CCDカメラ 1 ... Bonding tool 2 ... Heater block 3 ... Metal thin film 4 ... Electrode 5.13 ... Semiconductor integrated circuit chip 6 ... Transparent substrate 7-14.19 ... Electrode pad 8 ... Barrier metal 9 ... Protective film 10/12 ... Photoresist 11.15 ... Bump 16 ... Bump forming substrate 17 ... Capillary 18 ... Wire 20 ... Projection 21 ... Inner lead 22 ... CCD camera

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】ボンディングツール内を昇降可能なヒータ
ーブロックを用いることにより、半導体集積回路チップ
上の電極パッドに基板及び半導体装置(パッケージ)接
合用の突起電極を容易に形成できることを特徴とするバ
ンプ形成方法。
1. A bump characterized in that a bump electrode for bonding a substrate and a semiconductor device (package) can be easily formed on an electrode pad on a semiconductor integrated circuit chip by using a heater block that can move up and down in a bonding tool. Forming method.
【請求項2】前記、突起電極は、Au、Al、半田等の
材料を10μm〜50μm程度の厚さを持ったリボン状
としたものを前記ボンディングツールで打ち抜いて形成
することを特徴とする請求項1記載のバンプ形成方法。
2. The bump electrode is formed by punching with a bonding tool a ribbon-shaped material having a thickness of about 10 μm to 50 μm made of a material such as Au, Al or solder. Item 7. The bump forming method according to Item 1.
【請求項3】前記形成された突起電極を昇降可能なヒー
ターブロックが、ボンディングツール内を降下してきて
突起電極を加熱することによりフォーミングする事を特
徴とする請求項2記載のバンプ形成方法。
3. The bump forming method according to claim 2, wherein a heater block capable of raising and lowering the formed protruding electrode descends in a bonding tool to heat the protruding electrode for forming.
JP4088802A 1992-04-09 1992-04-09 Forming method for bump Pending JPH05291260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4088802A JPH05291260A (en) 1992-04-09 1992-04-09 Forming method for bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4088802A JPH05291260A (en) 1992-04-09 1992-04-09 Forming method for bump

Publications (1)

Publication Number Publication Date
JPH05291260A true JPH05291260A (en) 1993-11-05

Family

ID=13953008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4088802A Pending JPH05291260A (en) 1992-04-09 1992-04-09 Forming method for bump

Country Status (1)

Country Link
JP (1) JPH05291260A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153764A (en) * 1993-11-29 1995-06-16 Nec Corp Method for forming solder bump
JPH07201861A (en) * 1993-12-28 1995-08-04 Nec Corp Bump formation device and method for forming very small bump
US6929170B2 (en) * 2003-09-30 2005-08-16 Ted Ju Solder deposition method
KR100612048B1 (en) * 2005-07-04 2006-08-14 한국전자통신연구원 Chip bonding method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07153764A (en) * 1993-11-29 1995-06-16 Nec Corp Method for forming solder bump
JPH07201861A (en) * 1993-12-28 1995-08-04 Nec Corp Bump formation device and method for forming very small bump
US6929170B2 (en) * 2003-09-30 2005-08-16 Ted Ju Solder deposition method
KR100612048B1 (en) * 2005-07-04 2006-08-14 한국전자통신연구원 Chip bonding method

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