JP2888036B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a TAB package, and more particularly, to a method for forming an inner lead to be connected to a device electrode of a chip.

[0002]

2. Description of the Related Art Memory chips have a remarkable increase in storage capacity due to the improvement in microfabrication technology of semiconductor devices, and chip dimensions tend to be larger. The type of memory chip package is
The dimensions and the arrangement and position of the external terminals are standardized by semiconductor manufacturers, so that it is extremely difficult to store a large memory chip having a large storage capacity in a standardized package. As a package form for accommodating such a large-sized memory chip, a lead frame type package 19 of a LOC (lead-on-chip, hereinafter referred to as LOC) system shown in FIG. 5A is used. This method has a memory chip (semiconductor chip) in which element electrodes 21 provided in the periphery of a conventional chip are arranged in the center of the chip as shown in FIG. 1) The wire bonding 39 between the bonding lead 22 ′ of the lead frame 22 and the element electrode 21 of the semiconductor chip 20 is performed in the center of the semiconductor chip 20.
The bonding regions W1 and W2 around the semiconductor chip 20 which are required in the conventional package shown in FIG. 3C are not required, so that the package width W3 can be reduced by about 20%, and the size of the package can be reduced. 2) The wiring length (not shown) of the signal and the power supply is shortened in the central arrangement of the element electrode 21 (signal, power supply, GND electrode), and the wiring delay and the noise are reduced by the reduction of the wiring capacitance and the wiring resistance, so that the memory access is reduced It is possible to increase the speed and significantly improve the electrical characteristics of the semiconductor chip 20. 3) Since the lead frame 22 has no die pad 18 for die bonding the semiconductor chip 20, the lead frame 22 and the molding resin
Cracks at the interface of No. 3 hardly occur, and the moisture resistance can be improved. 4) Since the lead frame 22 does not have a die pad, even when the type of the semiconductor chip 20 is changed due to a change in the cell structure and the cell arrangement of the semiconductor chip 20, the lead frame 22 can be used.
And a mold forming die can be used, and the manufacturing cost can be reduced.

[0003] It has the following features. But,
In recent years, LOC-type TAB using a thin film carrier for mounting a large number of memory packages at high density for the purpose of reducing the size, weight, and functionality of electronic devices.
A type package has been developed.

[0004] (D in the same figure) LO by film carrier
1 shows a C-type TAB type package 24. As a bonding method of the TAB type package 24, in a memory chip having such a large chip size and a relatively small number of device electrodes of 20 to 40, the inner leads 26 of the film carrier 25 are used instead of the conventional gang bonding method (collective bonding). (Fig. 6)
As shown in (1), a single point method (individual bonding) is used, in which each point is individually pressed by a bonding tool 28 having a pressure contact surface 27 close to the size of the element electrode 21 of the semiconductor chip 20, similarly to wire bonding. This method uses a flexible film 29 made of polyimide for approximately 3
This uses a film carrier 25 in which leads are formed of rolled copper having a thickness of 5 microns. As described above, the semiconductor chip 20 has the device electrode 21 provided at the center of the chip, and the inner lead 26 and the device electrode 21 are joined via the Au bump 31.

FIG. 6 shows a joining method in the single point method. FIG. 1A shows a film carrier 25 and a semiconductor chip 20 in which bumps 30 are formed on inner leads 26 by the transfer bump method. First, the inner leads 26 are aligned with the device electrodes 21 of the semiconductor chip 20. . After alignment, inner lead 2
6 are pressed one by one by a bonding tool 28 from above the inner lead 26 and ultrasonic waves are applied to plastically deform the bump 30 formed on the inner lead 26, and the inner lead 26 and the device electrode 21 of the semiconductor chip 20 are (FIG. B). The bonding is performed by the amount of the element electrodes 21 of the semiconductor chip 20, that is, by the number of the inner leads 26.
The above step B is repeatedly performed (FIG.
D).

Accordingly, the package thickness is reduced by about 80% by the lead frame thickness and the bonding wire loop height.
As shown in FIG. 7, several stages of the TAB package 24 are stacked and mounted on a circuit board 32 of an electronic device (not shown), so that the electronic device is small, light, and highly functional. Can be easily realized.

[0007]

However, when a memory chip is packaged in a TAB type, an insulating material having a shielding effect on radioactive impurities is provided on the element surface of the chip for electrical insulation and for preventing malfunction due to radioactive impurities in the memory cell. It has a structure in which 38 to 38 microns of polyimide is formed in a film form. Therefore, as shown in FIG. 8A, between the inner lead 26 derived from the film carrier and the element electrode 21 of the chip 20, 25 to 1
A spacing H of 25 microns results. This interval H is determined by the step of transferring bumps to the inner leads 26 and the inner leads 2.
6 and the element electrode 21 of the semiconductor chip 20, the stepped portion serves as a fulcrum P and the inner lead 26 is bonded in an isolated manner, so that a bonding displacement L is generated between the element electrode 21 and the bump 30 of the inner lead 26. Inevitably occurs. In the prior art, the inner lead 26
Since the element electrodes 21 of the semiconductor chip 20 are located directly below the bumps 30, no bonding displacement L occurs. Therefore, the required bonding area cannot be obtained due to the bonding deviation L, so that the bonding strength is significantly reduced. Further, when forming the inner lead of the conventional film carrier, the inner lead is formed by being sandwiched by a mold (not shown) adapted to the forming shape and state. At this time, the forming is usually carried out by the film carrier maker after the production of the film carrier.
As shown in FIG.
3 and bump drop-off 34 occurred. For example, in the case of a film carrier with bumps, product defects such as bump drop-off occurred. On the other hand, even when the inner lead 26 is formed by the user, similarly to the case where the mold design and the forming conditions (pressure, time, temperature) of the mold are inappropriate, the bumps 34 and the displacement 33 of the bumps cause the same. Lead crack 35 due to poor bonding and metal fatigue at the bent portion of the inner lead 26 due to forced forming by a forming die.
And the lead plating film 36 was damaged. As a result, Cu 37 as a base of the inner lead 26 is exposed, disconnection and corrosion occur in the inner lead due to thermal stress in the resin molding process and the environmental test of the package, and the reliability is reduced. It is necessary to prepare a forming die for each type, and there is a problem that the manufacturing cost of the TAB package is significantly increased.

SUMMARY OF THE INVENTION In view of the above problems, when mounting a memory chip on a TAB type package of a LOC system using a film carrier, the present invention provides a method for forming, regulating, and positioning an inner lead with a bonding tool, and then removing the inner lead. By joining with the chip's device electrode, there is no decrease in joining strength due to joining misalignment,
It is another object of the present invention to provide a low-cost TAB package of a memory chip which does not require a forming die or the like.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a method of bonding and transferring a bump to an inner lead on a film and a method of connecting a bump of an inner lead to which a bump has been transferred to an inner lead. At the time of bonding with the element electrode of the above, the bonding tool is brought into contact with the inner lead to push down the inner lead by the thickness of the insulating material, and deform the inner lead along the step of the thickness of the insulating material. The bonding transfer with the bump or the bonding between the bump of the inner lead and the device electrode of the semiconductor chip is performed.

[0010]

According to the present invention, the spacing between the inner leads and the bumps formed by the insulating material of the film and the device electrodes of the semiconductor chip is regulated and deformed one by one by a bonding tool. Thus, by bonding the leads to the device electrodes of the semiconductor chip by pressurizing the leads, a bonding shift due to a step does not occur at the time of bonding, and the reliability of bonding between the bump and the semiconductor chip is not impaired. Further, a forming step of the film carrier is not required, and a significantly expensive forming mold is not required. In addition, a forming die for each product type is not required for chips having different device electrode arrangement positions, and thus product types can be changed quickly and easily. Furthermore, metal fatigue is less likely to occur in the inner lead than in the case of forced inner lead molding using a forming die, thereby reducing bonding defects such as disconnection and peeling of the inner lead due to thermal stress such as resin molding. The reliability can be greatly improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention in which a method of forming an inner lead during a step of transferring a bump of a film carrier to an inner lead is shown. In FIG. 1A, the bump-forming substrate 1
The bumps 5 formed on the film carrier 4 and the inner leads 2 of the film carrier 4 are aligned. Next, the bonding tool 6 is brought into contact with A of the inner lead 2 led out from the film carrier 4 to lower the bonding tool 6 along the side surface direction of the insulating film 3 to push down the inner lead 2 to the vicinity of the bump 5 (FIG. B). . The bonding tool 6 is moved onto the inner lead 2 aligned with the bump 5, and the inner lead 2 is pressed and heated to apply the bump 5.
Is transferred to the inner lead 2 (FIG. 2C). The bump transfer of the other inner leads 2 is similarly performed for the inner leads 2.
A, the bonding tool 6 is brought into contact with A, the bonding tool 6 is lowered along the side surface direction of the insulating film 3, and the inner lead 2 is pushed down to the vicinity of the bump 5 (FIG. 3D), and the bonding tool 6 is aligned with the bump 5. The bumps 5 are transferred onto the inner leads 2, and the bumps 5 are transferred and formed on the inner leads 2 by applying pressure and heat to the inner leads 2 (FIG. E). The bump transfer is performed for the number of the inner leads 2 in this manner.

Next, FIG. 2 shows a method of forming the inner lead in the step of joining the bump-transferred inner lead and the device electrode of the semiconductor chip according to the second embodiment of the present invention. is there. (A in the figure)
Then, the inner leads 2 having the bumps 5 formed on the inner leads 2 are aligned with the device electrodes 10 of the semiconductor chip 9. Next, after aligning the inner leads 2 with the device electrodes 10 of the semiconductor chip 9, the bonding tool 6 is gradually lowered to the vicinity A of the base of the inner leads 2 led out from the film carrier 4, and along the side direction of the insulating film 3. Then, the bonding tool 6 is lowered by the thickness of the insulating film 3 to shape the inner lead 2 (FIG. 2B). Next, the bonding tool 6 is moved to the tip of the inner lead 2, and the side of the tip of the inner lead 2 is slightly moved in the XY direction by the bonding tool 6 to align the bump 5 with the device electrode 10 of the semiconductor chip 9. .
After alignment, inner lead 2 with bonding tool 6
The bump 5 is pressed from above 7 and ultrasonic waves are applied to plastically deform the bump 5 of the inner lead 2 to join the bump 5 and the element electrode 10 of the semiconductor chip 9 (FIG. C). The bonding is performed by the formation of the device electrode 10 of the semiconductor chip 9, that is,
The bonding tool 6 is moved by the number of the inner leads 2 (FIG. D), and the above A to C are repeated to join the element electrodes 10 of the semiconductor chip 9 and the inner leads 2 (FIG. E). .

Thus, when the inner lead 2 is joined to the device electrode 10 of the semiconductor chip 9, the gap between the inner lead 2 and the device electrode 10 of the semiconductor chip 9 occurs due to the thickness of the insulating film 3 by the bonding tool 6 used for joining. Inner leads 2 along the side of insulating film 3 with respect to H
Can be formed, and the position of the bumps 5 can be adjusted by the bonding tool 6, thereby enabling more accurate bonding.

As a third embodiment (FIG. 3), a film carrier 4 is mounted on a stage 1 having a flat surface as shown in FIG.
1 and the inner lead 2 is attached to the bonding tool 6
After only forming is performed in advance (A in the same figure), the inner leads 2 and the device electrodes 1 of the semiconductor chip 9 are formed.
It is also possible to position the inner lead 2 by pressure bonding (not shown) with a bonding tool 6 and to apply ultrasonic waves to join the inner leads 2 (FIG. B). FIG. 4 is a trajectory diagram showing an operation sequence of the bonding tool 6 when the inner lead 2 is pressed by the bonding tool 6 to form. The vertical axis H indicates the height of the bonding tool 6, and the horizontal axis T indicates the elapsed time. The inner lead 2 is bent along the side surface of the insulating film 3 until the bonding tool 6 reaches the height of H2 for a certain time T1.
To form the inner lead 2. Then, at a short time T2, the bonding tool 6 is further lowered to the height of H3. The pressing force of T1 and T2 is T
2 is set higher. As a result, the plastic deformation due to the bending of the inner lead 2 is decisive, and the forming amount of each inner lead, that is, the bending state of the inner lead 2 can be stabilized, and the forming with excellent reproducibility without variation can be performed. .

This eliminates the need for a separate step of forming the inner leads 2 of the film carrier 4 and expensive forming dies and equipment, thereby reducing the manufacturing cost and enabling highly accurate bonding to the device electrodes.
In addition, a forming die for each product type is not required even for chips having different element electrode arrangement positions, and thus product types can be changed quickly and easily. Furthermore, metal fatigue is less likely to occur in the inner lead than in the case of forced inner lead molding using a forming die, thereby reducing bonding defects such as disconnection and peeling of the inner lead due to thermal stress such as resin molding. The reliability can be greatly improved. The bonding tool can be freely controlled and set by controlling the bonding tool when the inner lead is formed and when forming the inner lead by providing a pattern recognition function and a fine movement operation mechanism for the element electrode in the bonding apparatus. In the bonding of the inner lead by the single point method in the present invention, any of a transfer bump method in which a bump is transferred to the inner lead in advance and a wafer bump method in which the bump 30 is formed directly on the element electrode 21 can be applied. Needless to say, the present invention can be applied to bumps made of materials other than Au, for example, solder.

[0017]

As described above, according to the present invention, the leads are regulated and deformed before bonding by a bonding tool, and then the leads are pressed by the bonding tool to be bonded to the device electrodes of the semiconductor chip, thereby forming a film carrier. No process is required, and an expensive forming mold is not required. In addition, a forming die for each product type is not required for chips having different device electrode arrangement positions, and thus product types can be changed quickly and easily. The forming shape of the inner lead can be freely set according to the moving speed, angle and moving amount of the bonding tool, and the forming can be accurately realized by inputting such information to the automatic bonder. Furthermore, compared to the forced molding of the inner lead using a forming mold, it is possible to reduce bonding defects such as disconnection and peeling of the inner lead due to thermal stress of resin mold, etc., which is less likely to cause metal fatigue on the inner lead, and reliability. Can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a trajectory diagram showing an operation sequence of the bonding tool according to the present invention.

FIG. 5 is a configuration diagram of a conventional semiconductor device.

FIG. 6 is a process sectional view of a conventional semiconductor device manufacturing method.

FIG. 7 is a cross-sectional view showing a conventional semiconductor device mounting method in the embodiment.

FIG. 8 is a sectional view for explaining a problem in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bump forming board 2 Inner lead 3 Insulating film 4 Film carrier 5 Bump 6 Bonding tool 7 Pressure welding 9 Semiconductor chip 10 Element electrode 11 Stage

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-13497 (JP, A) JP-A-4-334037 (JP, A) JP-A-59-139636 (JP, A) JP-A-5-139636 291355 (JP, A) JP-A-5-90354 (JP, A) JP-A-2-82038 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/60 311

Claims (1)

(57) [Claims] A step of aligning a plurality of projecting electrodes formed on a substrate with leads on a film; and contacting a bonding tool with each of the leads on the film to push the leads down to near the projecting electrodes. Deforming the lead, pressurizing and heating the lead, transferring the projecting electrode to the lead, and aligning the projecting electrode transferred to the lead with the electrode of the semiconductor chip. And contacting the bonding tool with the lead to align the projecting electrode of the lead with the electrode of the semiconductor chip, and pressurizing and applying heat to the lead to join the projecting electrode and the electrode of the semiconductor chip. And a method of manufacturing a semiconductor device.