JPH0526760Y2 - - Google Patents
Info
- Publication number
- JPH0526760Y2 JPH0526760Y2 JP1987036375U JP3637587U JPH0526760Y2 JP H0526760 Y2 JPH0526760 Y2 JP H0526760Y2 JP 1987036375 U JP1987036375 U JP 1987036375U JP 3637587 U JP3637587 U JP 3637587U JP H0526760 Y2 JPH0526760 Y2 JP H0526760Y2
- Authority
- JP
- Japan
- Prior art keywords
- island
- chip
- lead frame
- resin
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 description 14
- 239000000463 material Substances 0.000 description 9
- 239000012778 molding material Substances 0.000 description 7
- 229920002050 silicone resin Polymers 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
（技術分野）
本考案はICやLSIなどの半導体集積回路装置チ
ツプ（以下ICチツプという）単独で、又はICチ
ツプと他の電子部品とを樹脂封止法によつてパツ
ケージングした実装体に関するものである。[Detailed description of the invention] (Technical field) The invention is based on the use of a semiconductor integrated circuit device chip (hereinafter referred to as an IC chip) such as an IC or an LSI, or an IC chip and other electronic components by resin encapsulation. This relates to a packaged assembly.
（従来技術）
ICチツプをパツケージングする１つの方法と
して樹脂封止法がある。(Prior Art) One method for packaging IC chips is a resin encapsulation method.
第４図は樹脂封止法によつてパツケージングさ
れたDIPタイプの実装体を表わしている。２はリ
ードフレームであり、リードフレーム２のアイラ
ンド４にICチツプ６が固定され、ICチツプ６と
リードフレーム２とがワイヤ８によつてボンデイ
ングされている。ICチツプ６の周りはモールド
材１０によつて封止されている。 FIG. 4 shows a DIP type mounting body packaged using the resin sealing method. 2 is a lead frame, and an IC chip 6 is fixed to an island 4 of the lead frame 2, and the IC chip 6 and the lead frame 2 are bonded with wires 8. The area around the IC chip 6 is sealed with a molding material 10.
リードフレーム２とアイランド４は一体的に形
成されるものであるが、これらの材質としては例
えばFe−Ni合金や銅系材料が用いられ、モール
ド材１０としては例えばエポキシ系樹脂を主成分
とする樹脂が使用される。 The lead frame 2 and the island 4 are integrally formed, and their material is, for example, Fe-Ni alloy or copper-based material, and the molding material 10 is, for example, mainly composed of epoxy resin. resin is used.
樹脂封止法による実装体では、リードフレーム
のアイランド４とモールド材１０との熱膨張率が
大きく異なつているので、アイランド４の面積が
大きい場合、アイランド４の周辺とモールド材１
０との間で応力集中が発生し、パツケージにクラ
ツク１２が発生することがある。 In a packaged using the resin sealing method, the thermal expansion coefficients of the island 4 of the lead frame and the molding material 10 are significantly different.
0, stress concentration may occur and cracks 12 may occur in the package.
クラツク１２が発生するとそこから湿気などが
侵入してICチツプ６の性能が劣化する。 When a crack 12 occurs, moisture enters through the crack 12 and the performance of the IC chip 6 deteriorates.
（目的）
本考案はリードフレームのアイランドとモール
ド材との間の応力集中を緩和することによつてパ
ツケージにクラツクが発生することを防止するこ
とを目的とするものである。(Purpose) The purpose of the present invention is to prevent the occurrence of cracks in the package by alleviating stress concentration between the island of the lead frame and the mold material.
（構成）
本考案はICチツプ等が樹脂封止された実装体
であつて、ICチツプ等が固定されているリード
フレーム・アイランドの少なくとも裏面には軟性
樹脂層が設けられている。(Configuration) This device is a mounting body in which an IC chip or the like is resin-encapsulated, and a soft resin layer is provided on at least the back surface of the lead frame island to which the IC chip or the like is fixed.
軟性樹脂としてはポリイミド樹脂やシリコン樹
脂を用いることができる。 As the soft resin, polyimide resin or silicone resin can be used.
リードフレームのアイランドの少なくとも裏面
にポリイミド樹脂やシリコン樹脂などの軟性樹脂
層を設けることによつて、アイランドとモールド
材との間で発生する応力をその軟性樹脂で緩和す
ることができ、クラツクの発生を防止することが
できる。 By providing a soft resin layer such as polyimide resin or silicone resin on at least the back surface of the island of the lead frame, the stress generated between the island and the mold material can be alleviated by the soft resin, thereby preventing the occurrence of cracks. can be prevented.
以下、実施例について具体的に説明する。 Examples will be specifically described below.
第１図は一実施例を表わす。 FIG. 1 represents one embodiment.
リードフレーム２のアイランド４にはICチツ
プ６が固定され、ICチツプ６とリードフレーム
２がワイヤ８によつてボンデイングされている。
アイランド４の裏面にはポリイミドフイルム１４
が接着されており、ICチツプ６とアイランド４
の周りがモールド材１０によつて封止されてい
る。 An IC chip 6 is fixed to the island 4 of the lead frame 2, and the IC chip 6 and the lead frame 2 are bonded by wires 8.
Polyimide film 14 is placed on the back side of island 4.
are glued together, and IC chip 6 and island 4
The surrounding area is sealed with a molding material 10.
リードフレーム２、アイランド４の材質は従来
と同じくFe−Ni合金や銅系材料であり、モール
ド材１０も従来と同じく主成分のエポキシ系樹脂
にシリコン、硬化促進剤及び顔料を添加したもの
である。 The lead frame 2 and island 4 are made of Fe-Ni alloy or copper-based material as before, and the molding material 10 is also made of epoxy resin as the main component, with silicone, hardening accelerator, and pigment added, as before. .
アイランド１４の裏面に設けられるポリイミド
フイルム１４に代えてポリイミド樹脂液を吹き付
けロールにより塗布し焼成してもよい。 Instead of the polyimide film 14 provided on the back surface of the island 14, a polyimide resin liquid may be applied with a spray roll and fired.
ポリイミド樹脂フイルム１４に変えてシリコン
樹脂を用いることもできる。シリコン樹脂はアイ
ランド４の裏面に塗布した後に焼成すればよい。 Silicone resin can also be used instead of the polyimide resin film 14. The silicone resin may be baked after being applied to the back surface of the island 4.
ポリイミド樹脂やシリコン樹脂のフイルムや塗
布膜はリードフレーム２にICチツプ６を組み込
む前に設けてもよく、又はICチツプ６を組み込
んだ後に設けてもよい。いずれにしても、モール
ド材１０でICチツプ６の周りを封止する前にポ
リイミドフイルム１４などが設けられていればよ
い。 The film or coating film of polyimide resin or silicone resin may be provided before the IC chip 6 is incorporated into the lead frame 2, or may be provided after the IC chip 6 is incorporated. In any case, a polyimide film 14 or the like may be provided before sealing around the IC chip 6 with the molding material 10.
第２図は他の実施例を表わすものである。 FIG. 2 shows another embodiment.
アイランド４にICチツプ６を固定し、ワイヤ
８でボンデイングを施した後に、ICチツプ６と
アイランド４の周りをシリコン樹脂１６によつて
取り囲んだものである。 After an IC chip 6 is fixed to the island 4 and bonded with a wire 8, the IC chip 6 and the island 4 are surrounded by a silicone resin 16.
これによつてもアイランド４とモールド材１０
との間で発生する応力集中を防止することができ
る。 With this, the island 4 and the mold material 10
It is possible to prevent stress concentration that occurs between the
第３図はさらに他の実施例を表わす。 FIG. 3 shows yet another embodiment.
ICチツプ１０を固定するアイランド４の裏面
にポリイミドフイルム１８が接着されているが、
このポリイミドフイルム１８には紙面垂直方向に
溝２０が形成されていることによつて、段差が形
成されている。 A polyimide film 18 is adhered to the back surface of the island 4 to which the IC chip 10 is fixed.
A groove 20 is formed in the polyimide film 18 in a direction perpendicular to the plane of the paper, thereby forming a step.
このようにポリイミドフイルム１８に段差を設
けることによつてアイランド４とモールド材１０
との間で発生する応力が段差の部分に分散され、
応力集中を防止する効果が一層向上する。アイラ
ンド４の裏面にメツシユ状のポリイミドフイルム
を設けることによつても、段差をもつポリイミド
フイルム１８と同様に応力を分散させて緩和する
効果を発揮することができる。 By providing a step in the polyimide film 18 in this way, the island 4 and the molding material 10
The stress generated between the
The effect of preventing stress concentration is further improved. By providing a mesh-like polyimide film on the back surface of the island 4, it is possible to exert the effect of dispersing and relaxing stress in the same way as the polyimide film 18 having steps.
実施例では１個のICチツプ６を実装する場合
を例示しているが、複数のICチツプを実装する
場合やICチツプと他の電子部品を実装する場合
においても本考案を適用することができる。 Although the embodiment illustrates the case where one IC chip 6 is mounted, the present invention can also be applied when mounting multiple IC chips or when mounting an IC chip and other electronic components. .
（考案の効果）
本考案の実装体では、アイランドの少なくとも
裏面に軟性樹脂層を設けたので、アイランドとモ
ールド材との間で発生する応力の集中を避けるこ
とができ、モールド材にクラツクが発生すること
を防止することができる。(Effects of the invention) In the mounting body of this invention, a soft resin layer is provided on at least the back surface of the island, so it is possible to avoid concentration of stress that occurs between the island and the mold material, which may cause cracks in the mold material. This can be prevented.
第１図及び第２図はそれぞれ実施例を示す断面
図、第３図は他の実施例のアイランド部分を示す
側面図、第４図は従来の実装体を示す断面図であ
る。
２……リードフレーム、４……アイランド、６
……ICチツプ、１０……モールド材、１４，１
８……ポリイミドフイルム、１６……シリコン樹
脂。
1 and 2 are sectional views showing an embodiment, FIG. 3 is a side view showing an island portion of another embodiment, and FIG. 4 is a sectional view showing a conventional mounting body. 2...Lead frame, 4...Island, 6
...IC chip, 10...Mold material, 14,1
8...Polyimide film, 16...Silicone resin.
Claims (1)
がワイヤボンデイング法により組み込まれ、その
半導体集積回路装置チツプ等の周囲が樹脂で封止
されている実装体において、前記半導体集積回路
装置チツプ等が固定されているリードフレーム・
アイランドの少なくとも裏面には軟性樹脂層が設
けられていることを特徴とする実装体。 A semiconductor integrated circuit device chip, etc. is fixed in a mounting body in which a semiconductor integrated circuit device chip, etc. is assembled into a lead frame by a wire bonding method, and the periphery of the semiconductor integrated circuit device chip, etc. is sealed with resin. Lead frame·
A mounting body characterized in that a soft resin layer is provided on at least the back surface of the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987036375U JPH0526760Y2 (en) | 1987-03-11 | 1987-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987036375U JPH0526760Y2 (en) | 1987-03-11 | 1987-03-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63142855U JPS63142855U (en) | 1988-09-20 |
| JPH0526760Y2 true JPH0526760Y2 (en) | 1993-07-07 |
Family
ID=30846719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987036375U Expired - Lifetime JPH0526760Y2 (en) | 1987-03-11 | 1987-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0526760Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2734443B2 (en) * | 1996-03-19 | 1998-03-30 | 日本電気株式会社 | Resin-sealed semiconductor device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS525584U (en) * | 1975-06-27 | 1977-01-14 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 | ||
| JPS58440B2 (en) * | 1971-11-20 | 1983-01-06 | フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ | Method for producing 17,21-dihydroxy-20-ketopregnans |
| JPS5988854A (en) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | Semiconductor device |
| JPS59116122A (en) * | 1982-12-01 | 1984-07-04 | ユニ−・ヴアン・クンストメストフアブリ−ケン・ベスロ−テム・ベンノツトシヤツプ | Manufacture of boric acid |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS60195955A (en) * | 1984-03-19 | 1985-10-04 | Hitachi Ltd | Semiconductor device |
| JPS6123348A (en) * | 1984-07-12 | 1986-01-31 | Nec Corp | Resin sealing type semiconductor device |
| JPS61185955A (en) * | 1985-02-13 | 1986-08-19 | Toshiba Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58440U (en) * | 1981-06-25 | 1983-01-05 | 富士通株式会社 | plastic packaging |
-
1987
- 1987-03-11 JP JP1987036375U patent/JPH0526760Y2/ja not_active Expired - Lifetime
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58440B2 (en) * | 1971-11-20 | 1983-01-06 | フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ | Method for producing 17,21-dihydroxy-20-ketopregnans |
| JPS525584U (en) * | 1975-06-27 | 1977-01-14 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 | ||
| JPS5988854A (en) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | Semiconductor device |
| JPS59116122A (en) * | 1982-12-01 | 1984-07-04 | ユニ−・ヴアン・クンストメストフアブリ−ケン・ベスロ−テム・ベンノツトシヤツプ | Manufacture of boric acid |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS60195955A (en) * | 1984-03-19 | 1985-10-04 | Hitachi Ltd | Semiconductor device |
| JPS6123348A (en) * | 1984-07-12 | 1986-01-31 | Nec Corp | Resin sealing type semiconductor device |
| JPS61185955A (en) * | 1985-02-13 | 1986-08-19 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63142855U (en) | 1988-09-20 |
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