JP2844586B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2844586B2 JP2844586B2 JP4048083A JP4808392A JP2844586B2 JP 2844586 B2 JP2844586 B2 JP 2844586B2 JP 4048083 A JP4048083 A JP 4048083A JP 4808392 A JP4808392 A JP 4808392A JP 2844586 B2 JP2844586 B2 JP 2844586B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor chip
- bus bar
- semiconductor integrated
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に、半導体チップとインナーリードを絶縁する絶縁部
材の構成を簡素化し、かつパッケージの薄型化を実現す
ることが可能な半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit capable of simplifying the configuration of an insulating member for insulating a semiconductor chip and inner leads and realizing a thin package.
【０００２】[0002]
【従来の技術】従来の半導体集積回路は、例えば、半導
体チップを積載するためのタブ部と，各リードが接触し
ないように所定の間隔で配置されたインナーリードと，
インナーリードに対して内側に配置される電源接続用の
バスバーが設けられたリードフレームを使用し、半導体
チップのボンディングパットにインナーリードおよびバ
スバーをワイヤボンディングした後にリードフレームお
よび半導体チップを封止樹脂によってモールド成形して
形成されている。2. Description of the Related Art A conventional semiconductor integrated circuit includes, for example, a tab portion for mounting a semiconductor chip, and inner leads arranged at predetermined intervals so that the leads do not come into contact with each other.
Using a lead frame provided with a bus bar for power connection arranged inside the inner lead, wire bonding the inner lead and the bus bar to the bonding pad of the semiconductor chip, and then bonding the lead frame and the semiconductor chip with a sealing resin It is formed by molding.
【０００３】半導体集積回路は近年、集積化および高密
度化に伴って半導体チップが大型化する傾向にある。こ
のため、大型化した半導体チップをリードフレームに積
載するためにタブ部が大きくなり、半導体チップとの間
に所定の間隔を有したインナーリードを有したリードフ
レームを形成することが困難になってきている。[0005] In recent years, semiconductor integrated circuits tend to be larger in size with higher integration and higher density. For this reason, the tab portion becomes large in order to load the large-sized semiconductor chip on the lead frame, and it becomes difficult to form a lead frame having inner leads with a predetermined interval between the semiconductor chip and the semiconductor chip. ing.
【０００４】上記した問題を解決するため、図２，図３
に示されるように半導体チップ４を絶縁性接着剤による
絶縁層３１を両面に有する絶縁性フィルム３３より形成
された絶縁部材３０を介してリードフレームのインナー
リード１およびバスバー２に固定し、インナーリード１
およびバスバー２と半導体チップ４のボンディングパッ
ト６をボンディングワイヤ５によって電気的に接続した
半導体集積回路がある。In order to solve the above problem, FIGS.
As shown in (1), the semiconductor chip 4 is fixed to the inner lead 1 and the bus bar 2 of the lead frame via an insulating member 30 formed of an insulating film 33 having an insulating layer 31 made of an insulating adhesive on both sides. 1
There is also a semiconductor integrated circuit in which a bus bar 2 and a bonding pad 6 of a semiconductor chip 4 are electrically connected by a bonding wire 5.
【０００５】この半導体集積回路によると、インナーリ
ード１およびバスバー２に半導体チップ４を接着して固
定するため、タブ部を省略することができるのでリード
フレームと封止樹脂との接触面積が減少し、その結果、
両者の密着性の低さに基づくクラックの発生を抑え、か
つ半導体チップ４の大型化によるパッケージの大型化を
抑えることができる。According to this semiconductor integrated circuit, since the semiconductor chip 4 is bonded and fixed to the inner lead 1 and the bus bar 2, the tab portion can be omitted, so that the contact area between the lead frame and the sealing resin is reduced. ,as a result,
The occurrence of cracks due to the low adhesion between the two can be suppressed, and the size of the package due to the increase in the size of the semiconductor chip 4 can be suppressed.
【０００６】ところが、上記した半導体集積回路では、
インナーリードを半導体チップに接続するボンディング
ワイヤがバスバーとの電気的な接触を避けるためにバス
バーの上部にループ状に配線されて形成されるので、ボ
ンディングワイヤの長さが増し、さらに封止樹脂による
モールド成形時にループされたボンディングワイヤによ
って厚み方向の高さが増すという問題がある。However, in the above-mentioned semiconductor integrated circuit,
Since the bonding wire connecting the inner lead to the semiconductor chip is formed by being looped and formed on the upper portion of the bus bar in order to avoid electrical contact with the bus bar, the length of the bonding wire is increased, and the sealing resin is used. There is a problem that the height in the thickness direction is increased by the bonding wire looped during molding.
【０００７】このバスバーとボンディングワイヤの電気
的な接触を防止する半導体集積回路として、図４，図５
および図６に示されるようにバスバー２の表面に絶縁性
接着剤３２あるいは絶縁性フィルム３３による絶縁被覆
を形成した半導体集積回路がある。ボンディングワイヤ
５の接続は、図５において半導体チップ４のボンディン
グパット６とインナーリード１およびバスバー２に串型
に設けられた接続部２０によって行われ、図６において
は半導体チップ４のボンディングパット６とインナーリ
ード１および絶縁フィルム３３に開口部７が設けられた
バスバー２に行われる。FIGS. 4 and 5 show a semiconductor integrated circuit for preventing electrical contact between the bus bar and the bonding wires.
As shown in FIG. 6, there is a semiconductor integrated circuit in which an insulating coating with an insulating adhesive 32 or an insulating film 33 is formed on the surface of the bus bar 2. The connection of the bonding wire 5 is performed by the bonding pad 6 of the semiconductor chip 4 and the connecting portion 20 provided in a skewer shape on the inner lead 1 and the bus bar 2 in FIG. 5, and in FIG. This is performed on the bus bar 2 in which the opening 7 is provided in the inner lead 1 and the insulating film 33.
【０００８】バスバー２の表面に絶縁性接着剤３２ある
いは絶縁性フィルム３３による絶縁被覆を形成すること
によって、ボンディングワイヤ５の配線を低いループで
バスバー２上に形成してもボンディングワイヤ５のバス
バー２への電気的な接触が防止される。従って、ボンデ
ィングワイヤ５による厚み方向の高さの増加が抑制され
る。By forming an insulating coating with an insulating adhesive 32 or an insulating film 33 on the surface of the bus bar 2, even if the wiring of the bonding wire 5 is formed on the bus bar 2 with a low loop, the bus bar 2 of the bonding wire 5 is formed. Electrical contact to the device is prevented. Therefore, an increase in the height in the thickness direction due to the bonding wire 5 is suppressed.
【０００９】[0009]
【発明が解決しようとする課題】しかし、従来の半導体
集積回路は、リードフレームと半導体チップを固定する
絶縁部材が、絶縁性接着剤と絶縁性フィルムの積層体で
あることから所定の厚みを有するため、半導体チップの
厚みに絶縁部材の厚みが加わってモールドの厚みを増加
させることから、形成されるパッケージの厚みが増加す
るという問題がある。従って、本発明の目的はパッケー
ジの薄型化された半導体集積回路を提供することにあ
る。However, the conventional semiconductor integrated circuit has a predetermined thickness because the insulating member for fixing the lead frame and the semiconductor chip is a laminate of an insulating adhesive and an insulating film. Therefore, since the thickness of the mold is increased by adding the thickness of the insulating member to the thickness of the semiconductor chip, there is a problem that the thickness of the formed package increases. Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having a thin package.
【００１０】[0010]
【課題を解決するための手段】本発明はパッケージを薄
型化するため、半導体チップを、フィラー等の絶縁物の
添加された絶縁性接着剤を加圧および加熱処理すること
により形成された一層構造の絶縁層によって、リードフ
レームに接着固定されるようにした半導体集積回路を提
供する。Since the present invention SUMMARY OF] is that thinner package, the semiconductor chip, even formed by pressurizing and heating an added insulating adhesive insulation fillers such structure The present invention provides a semiconductor integrated circuit that is bonded and fixed to a lead frame by the insulating layer.
【００１１】[0011]
【作用】本発明の半導体集積回路によると、絶縁性接着
剤にフィラー等の絶縁物が添加された絶縁性接着剤に加
圧および加熱処理を施して半導体チップをリードフレー
ムに固定するときの絶縁層を形成する。その結果、絶縁
層の組成が密になり、絶縁特性の向上した所定の厚みを
有する一層構造の絶縁層が形成される。According to the semiconductor integrated circuit of the present invention, the insulating adhesive in which an insulating material such as a filler is added to the insulating adhesive is subjected to pressure and heat treatment to fix the semiconductor chip to the lead frame. Form a layer. As a result, the composition of the insulating layer becomes dense, and a single-layer insulating layer having a predetermined thickness and improved insulating properties is formed.
【００１２】[0012]
【実施例１】以下、本発明の半導体集積回路を図面を基
に詳細に説明する。図１は本発明の半導体集積回路の一
実施例を示し、リードフレームを形成するインナーリー
ド１およびバスバー２と，インナーリード１およびバス
バー２に半導体チップ４を接着し固定する絶縁部材３
と，半導体チップ４のボンディングパット（図示せず）
とインナーリード１およびバスバー２を電気的に接続す
るボンディングワイヤ５より構成されている。Embodiment 1 Hereinafter, a semiconductor integrated circuit of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention, in which an inner lead 1 and a bus bar 2 forming a lead frame and an insulating member 3 for bonding and fixing a semiconductor chip 4 to the inner lead 1 and the bus bar 2 are shown.
And the bonding pad (not shown) of the semiconductor chip 4
And a bonding wire 5 for electrically connecting the inner lead 1 and the bus bar 2 to each other.
【００１３】インナーリード１およびバスバー２の半導
体チップ固定面に形成される絶縁部材３は、例えば、ポ
リエーテルアミドイミドを材料とする絶縁性接着剤に、
絶縁性を有する添加物として平均粒径１０μｍのＳｉＯ
2 が混入されたものにより構成されている。The insulating member 3 formed on the semiconductor chip fixing surface of the inner lead 1 and the bus bar 2 is made of, for example, an insulating adhesive made of polyetheramideimide.
SiO with an average particle size of 10 μm as an additive having insulating properties
2 is mixed.
【００１４】半導体集積回路の組み立ては、まず、イン
ナーリード１およびバスバー２に前述した絶縁物の添加
された絶縁性接着剤を塗布する。この塗布によってイン
ナーリード１およびバスバー２に３０μｍ程度の絶縁性
接着剤の被膜が形成される。In assembling a semiconductor integrated circuit, first, the above-described insulating adhesive to which the insulating material is added is applied to the inner lead 1 and the bus bar 2. By this application, a coating of an insulating adhesive of about 30 μm is formed on the inner lead 1 and the bus bar 2.
【００１５】次に、絶縁性接着剤の塗布されたインナー
リード１およびバスバー２に半導体チップ４を接着し、
このインナーリード１およびバスバー２と半導体チップ
４に加圧および加熱処理を施す。このことによって絶縁
性接着剤の厚みが１５μｍ程度まで減少された一層構造
の絶縁部材３が形成されるとともに、半導体チップ４が
この絶縁部材３によってインナーリード１およびバスバ
ー２に固定される。この後にインナーリード１およびバ
スバー２と半導体チップ４のボンディングパッドをボン
ディングワイヤ５によって電気的に接続し、封止樹脂に
よってモールド成形してパッケージを形成する。Next, the semiconductor chip 4 is bonded to the inner lead 1 and the bus bar 2 to which the insulating adhesive has been applied,
The inner leads 1 and the bus bars 2 and the semiconductor chip 4 are subjected to pressure and heat treatment. As a result, the thickness of the insulating adhesive is reduced to about 15 μm, thereby forming a single layer structure.
Together with the insulating member 3 is formed, the semiconductor chip 4 is fixed by the insulating member 3 to the inner leads 1 and the bus bar 2. Thereafter, the inner leads 1 and the bus bars 2 are electrically connected to the bonding pads of the semiconductor chip 4 by bonding wires 5, and are molded by a sealing resin to form a package.
【００１６】上記した方法によると、ＳｉＯ2 の添加さ
れた絶縁性接着剤が加圧および加熱処理されることによ
って組成が密になることから、形成される絶縁部材３の
絶縁性が向上する。また、絶縁部材３がＳｉＯ2 の添加
された絶縁性接着剤の単層被膜によって形成されること
から絶縁部材３の厚みの増加が抑制され、その結果、パ
ッケージの薄型化を図ることができる。本実施例では、
バスバー２の上に絶縁層が形成されていないが、図４よ
り図６に示すように絶縁層が設けられても良い。According to the above-described method, the insulating adhesive to which SiO 2 is added is subjected to pressure and heat treatments, so that the composition becomes dense, so that the insulating property of the formed insulating member 3 is improved. Further, since the insulating member 3 is formed of a single-layer film of an insulating adhesive to which SiO 2 is added, an increase in the thickness of the insulating member 3 is suppressed, and as a result, the package can be made thinner. In this embodiment,
Although no insulating layer is formed on the bus bar 2, an insulating layer may be provided as shown in FIG. 4 to FIG.
【００１７】[0017]
【発明の効果】以上説明した通り、本発明の半導体集積
回路によると、半導体チップを、フィラー等の絶縁物の
添加された絶縁性接着剤を加圧および加熱処理すること
によって形成された一層構造の絶縁層によりリードフレ
ームに接着固定されるようにしたため、絶縁部材の構成
を簡素化することによってパッケージを薄型化すること
ができる。As described above, according to the semiconductor integrated circuit of the present invention, a single- layer structure formed by subjecting a semiconductor chip to pressure and heat treatment of an insulating adhesive to which an insulator such as a filler is added. The package can be thinned by simplifying the configuration of the insulating member because the insulating layer is bonded and fixed to the lead frame.
【図１】本発明の一実施例を示す半導体集積回路の断面
図である。FIG. 1 is a sectional view of a semiconductor integrated circuit showing one embodiment of the present invention.
【図２】従来の半導体集積回路を示す断面図である。FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit.
【図３】従来の半導体集積回路を示す説明図である。FIG. 3 is an explanatory diagram showing a conventional semiconductor integrated circuit.
【図４】従来の半導体集積回路を示す説明図である。FIG. 4 is an explanatory diagram showing a conventional semiconductor integrated circuit.
【図５】従来の半導体集積回路を示す説明図である。FIG. 5 is an explanatory diagram showing a conventional semiconductor integrated circuit.
【図６】従来の半導体集積回路を示す説明図である。FIG. 6 is an explanatory diagram showing a conventional semiconductor integrated circuit.
１ インナーリード ２ バスバー ３，３０ 絶縁部材 ４ 半導体チッ
プ ５ ボンディングワイヤ ６ ボンディン
グパット ７ 開口部 ２０ 接続部 ３１ 絶縁層 ３２ 絶縁性接着
剤 ３３ 絶縁性フィルムDESCRIPTION OF SYMBOLS 1 Inner lead 2 Bus bar 3, 30 Insulating member 4 Semiconductor chip 5 Bonding wire 6 Bonding pad 7 Opening 20 Connection part 31 Insulating layer 32 Insulating adhesive 33 Insulating film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川村 敏雄 茨城県土浦市木田余町3550番地 日立電 線株式会社 システムマテリアル研究所 内 (72)発明者 大高 達也 茨城県土浦市木田余町3550番地 日立電 線株式会社 システムマテリアル研究所 内 (56)参考文献 特開 平２−39443（ＪＰ，Ａ) 特開 平２−168636（ＪＰ，Ａ) 特開 平２−36542（ＪＰ，Ａ) 特開 平５−235246（ＪＰ，Ａ) 特開 平４−75355（ＪＰ，Ａ) 特開 平５−152353（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/52 58 H01L 23/50──────────────────────────────────────────────────の Continued on the front page (72) Inventor Toshio Kawamura 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Within Hitachi Materials, Ltd. (56) References JP-A-2-39443 (JP, A) JP-A-2-168636 (JP, A) JP-A-2-36542 (JP, A) JP JP-A-5-235246 (JP, A) JP-A-4-75355 (JP, A) JP-A-5-152353 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21 / 52 58 H01L 23/50
Claims (1)
スバーに絶縁体を介して半導体チップが固定され、前記
インナーリードおよび前記バスバーがボンディングワイ
ヤを介して前記半導体チップに接続され、前記インナー
リードの前記ボンディングワイヤが前記バスバー上を通
過している構成の半導体集積回路において、 前記半導体チップは、フィラー等の絶縁物の添加された
絶縁性接着剤を加圧および加熱処理することにより形成
された一層構造の絶縁層によって、前記リードフレーム
に接着固定されることを特徴とする半導体集積回路。1. A semiconductor chip is fixed to an inner lead and a bus bar of a lead frame via an insulator, the inner lead and the bus bar are connected to the semiconductor chip via a bonding wire, and the bonding wire of the inner lead is provided. In the semiconductor integrated circuit having a structure in which the semiconductor chip passes over the bus bar, the semiconductor chip has a one- layer structure formed by subjecting an insulating adhesive to which an insulator such as a filler is added to pressure and heat. A semiconductor integrated circuit, which is bonded and fixed to the lead frame by a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4048083A JP2844586B2 (en) | 1992-02-04 | 1992-02-04 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4048083A JP2844586B2 (en) | 1992-02-04 | 1992-02-04 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218111A JPH05218111A (en) | 1993-08-27 |
| JP2844586B2 true JP2844586B2 (en) | 1999-01-06 |
Family
ID=12793436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4048083A Expired - Fee Related JP2844586B2 (en) | 1992-02-04 | 1992-02-04 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2844586B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09162205A (en) * | 1995-12-01 | 1997-06-20 | Hitachi Ltd | Pickup device |
-
1992
- 1992-02-04 JP JP4048083A patent/JP2844586B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218111A (en) | 1993-08-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |