KR970030697A - Semiconductor chip attaching method and structure using solder ball - Google Patents

Semiconductor chip attaching method and structure using solder ball Download PDF

Info

Publication number
KR970030697A
KR970030697A KR1019950041845A KR19950041845A KR970030697A KR 970030697 A KR970030697 A KR 970030697A KR 1019950041845 A KR1019950041845 A KR 1019950041845A KR 19950041845 A KR19950041845 A KR 19950041845A KR 970030697 A KR970030697 A KR 970030697A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
heat sink
semiconductor
solder ball
chip
Prior art date
Application number
KR1019950041845A
Other languages
Korean (ko)
Other versions
KR100201379B1 (en
Inventor
신원선
이정관
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950041845A priority Critical patent/KR100201379B1/en
Publication of KR970030697A publication Critical patent/KR970030697A/en
Application granted granted Critical
Publication of KR100201379B1 publication Critical patent/KR100201379B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 솔더볼(Solder Ball)을 이용한 반도체 칩 부착방법 및 구조에 관한 것으로, 히트싱크의 상면 외측으로 다수의 리드가 접착되고, 상기 히트싱크의 상면 중심부에는 접착수단에 의해 반도체 칩이 부착되며, 상기 반도체 칩 상에 구비된 칩패드와 리드는 와이어로 본딩되고, 그 외부는 산화 및 부식을 방지하기 위하여 컴파운드로 몰딩된 반도체 패키지 구조에 있어서, 상기 접착수단으로 솔더볼을 사용하여 반도체 칩을 부착시킴으로서 열방출 및 접착력을 향상시킴은 물론, 보이드의 발생을 방지하여 반도체 패키지의 신뢰성을 향상시키도록 된 솔더볼을 이용한 반도체 칩 부착방법이다.The present invention relates to a method and a structure for attaching a semiconductor chip using a solder ball, wherein a plurality of leads are bonded to an outer side of an upper surface of a heat sink, and a semiconductor chip is attached to an upper surface center of the heat sink by an adhesive means. A chip pad and a lead provided on the semiconductor chip are bonded by wires, and the outside thereof is a compound packaged semiconductor compound structure to prevent oxidation and corrosion, by attaching a semiconductor chip using solder balls as the bonding means. A method of attaching a semiconductor chip using solder balls to improve heat dissipation and adhesion, as well as to prevent generation of voids to improve reliability of a semiconductor package.

Description

솔더볼(Solder Ball)을 이용한 반도체 칩 부착방법 및 구조Semiconductor chip attaching method and structure using solder ball

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2도는 본 발명에 따른 반도체 패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a semiconductor package according to the present invention.

제 3도는 본 발명에 따른 제 1실시예를 나타낸 반도체 패키지의 단면도.3 is a cross-sectional view of a semiconductor package showing a first embodiment according to the present invention.

제 4도는 본 발명에 따른 제 2실시예를 나타낸 반도체 패키지의 단면도.4 is a cross-sectional view of a semiconductor package showing a second embodiment according to the present invention.

Claims (4)

히트싱크의 상면 외측으로 접착테이프를 이용하여 리드프레임의 리드를 부착하는 단계와, 상기 리드가 부착된 히트싱크의 상면 중심부에 플럭스(Flux)를 도포하는 단계와, 상기 플럭스(Flux)위에 솔더볼을 위치시키고, 그 위에 반도체 칩을 위치시키는 단계와, 노(爐; Furnace)에서 솔더볼을 녹여 반도체 칩을 부착하는 단계와, 상기 리드와 반도체 칩에 구비된 칩패드를 와이어로 본딩하는 단계와, 외부로부터 산화 및 부식을 방지하기 위하여 그 외부를 컴파운드로 몰딩하는 단계로 이루어진 것을 특징으로 하는 솔더볼을 이용한 반도체 칩 부착방법.Attaching the lead of the lead frame to the outer surface of the heat sink by using an adhesive tape; applying flux to the center of the upper surface of the heat sink to which the lead is attached; Positioning the semiconductor chip thereon, melting the solder balls in the furnace to attach the semiconductor chip, bonding the lead and the chip pad provided on the semiconductor chip with wires, and externally Method for attaching a semiconductor chip using a solder ball, characterized in that the step of molding the outside of the compound to prevent oxidation and corrosion from the. 히트싱크의 상면 외측으로 다수의 리드가 접착되고, 상기 히트싱크의 상면 중심부에는 접착수단에 의해 반도체 칩이 부착되며, 상기 반도체 칩 상에 구비된 칩패드와 리드는 와이어로 본딩되고, 그 외부는 산화 및 부식을 방지하기 위하여 컴파운드로 몰딩된 반도체 패키지 구조에 있어서, 상기 접착수단은 히트싱크의 상면에 플럭스(Flux)를 도포하고, 그 위에 솔더볼을 안착시켜 반도체 칩을 부착한 것을 특징으로 하는 반도체 패키지 구조.A plurality of leads are bonded to the outside of the top surface of the heat sink, and a semiconductor chip is attached to the center of the top surface of the heat sink by adhesive means, chip pads and leads provided on the semiconductor chip are bonded by wires, In the semiconductor package structure molded with a compound to prevent oxidation and corrosion, the bonding means is a semiconductor characterized in that the semiconductor chip is attached by applying a flux (Flux) on the upper surface of the heat sink, the solder ball is seated thereon Package structure. 제 2항에 있어서, 솔더볼이 안착되는 위치의 히트싱크 상면에는 다수의 솔더볼 안착홈이 형성되어 있는 것을 특징으로 하는 반도체 패키지 구조.The semiconductor package structure as claimed in claim 2, wherein a plurality of solder ball seating grooves are formed on an upper surface of the heat sink in which the solder balls are seated. 제 2항에 있어서, 상기 히트싱크 상면에 반도체 칩의 크기보다 약간 크게 홈을 형성하여서 된 것을 특징으로 하는 반도체 패키지 구조.The semiconductor package structure according to claim 2, wherein a groove is formed on the heat sink top surface slightly larger than the size of the semiconductor chip. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950041845A 1995-11-17 1995-11-17 Attaching method of semiconductor chip using a solder ball and structure of the same KR100201379B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950041845A KR100201379B1 (en) 1995-11-17 1995-11-17 Attaching method of semiconductor chip using a solder ball and structure of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950041845A KR100201379B1 (en) 1995-11-17 1995-11-17 Attaching method of semiconductor chip using a solder ball and structure of the same

Publications (2)

Publication Number Publication Date
KR970030697A true KR970030697A (en) 1997-06-26
KR100201379B1 KR100201379B1 (en) 1999-06-15

Family

ID=19434434

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950041845A KR100201379B1 (en) 1995-11-17 1995-11-17 Attaching method of semiconductor chip using a solder ball and structure of the same

Country Status (1)

Country Link
KR (1) KR100201379B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030047688A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394179B (en) * 2021-05-14 2022-05-17 南通华达微电子集团股份有限公司 Electronic component with multilayer carrier structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030047688A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor package

Also Published As

Publication number Publication date
KR100201379B1 (en) 1999-06-15

Similar Documents

Publication Publication Date Title
US6545347B2 (en) Enhanced leadless chip carrier
US20090189261A1 (en) Ultra-Thin Semiconductor Package
KR930020649A (en) Lead frame, semiconductor integrated circuit device using same, and manufacturing method thereof
EP0848423A4 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
KR970018451A (en) Method for manufacturing semiconductor package with heat sink and its structure
CN101118895A (en) Semiconductor element with embedded heat sink
JP2010524260A (en) Optical coupler package
CN101180726A (en) System and method for die attach using a backside heat spreader
US6768212B2 (en) Semiconductor packages and methods for manufacturing such semiconductor packages
JPH04207061A (en) Semiconductor device
KR970030697A (en) Semiconductor chip attaching method and structure using solder ball
JPS60171733A (en) Semiconductor device
US7009304B2 (en) Resin-sealed semiconductor device
JP2005327967A (en) Semiconductor device
US20040000703A1 (en) Semiconductor package body having a lead frame with enhanced heat dissipation
JPH0526760Y2 (en)
KR970023917A (en) Semiconductor package to prevent short circuit of wire
KR960000149Y1 (en) Semiconductor device
KR970053689A (en) Structure and Manufacturing Method of Chip Size Package
KR0179808B1 (en) Blp package
JPH04245462A (en) Semiconductor integrated circuit device and its manufacture
KR970063687A (en) Power package with direct electrical connection structure between dummy leads and heat sink
KR970024122A (en) Stacked Chip Packages with Same Bonding Direction
KR970013137A (en) Manufacturing method of a multichip package having a chip cavity
KR870000753A (en) Resin Sealed Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
N231 Notification of change of applicant
FPAY Annual fee payment

Payment date: 20120309

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20130307

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee