KR0179808B1 - Blp package - Google Patents
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- KR0179808B1 KR0179808B1 KR1019950068662A KR19950068662A KR0179808B1 KR 0179808 B1 KR0179808 B1 KR 0179808B1 KR 1019950068662 A KR1019950068662 A KR 1019950068662A KR 19950068662 A KR19950068662 A KR 19950068662A KR 0179808 B1 KR0179808 B1 KR 0179808B1
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- lead
- package
- semiconductor chip
- paddle
- blp
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 비엘피 패키지에 관한 것으로, 종래의 비엘피 패키지가 제조작업의 작업성이 좋지 않고 열방출특성이 불량하며 제조원가가 많이 드는 문제점이 있어 이를 해결하기 위한 것이다. 이와 같은 본 발명은 리드프레임(13)의 패들(14)에 액체형 접착제(17)를 사용하여 반도체칩(12)을 부착하고, 상기 리드프레임(13)의 인너리드(16)와 상기 반도체칩(12)의 칩패드(12')를 와이어(18)로 연결하며, 상기 반도체칩(12)과 인너리드(16)를 일정 면적몰딩하여 패키지몸체(11)를 형성하여, 상기 리드프레임(13)의 바탐리드(15)와 패들(14)의 하면을 패키지몸체(11)의 하면으로 드러나도록 하여 납도금한다. 이와 같은 본 발명에 의하면 패키지의 열방출특성 및 제조작업의 작업성이 좋아지고 제조원가가 절감되는 이점이 있다.The present invention relates to a BLP package, and a conventional BLP package has a problem in that workability of a manufacturing operation is poor, heat dissipation characteristics are poor, and manufacturing cost is high. In the present invention, the semiconductor chip 12 is attached to the paddle 14 of the lead frame 13 using the liquid adhesive 17, and the inner lead 16 of the lead frame 13 and the semiconductor chip ( The chip pad 12 ′ of 12 is connected with a wire 18, and the package body 11 is formed by molding a predetermined area of the semiconductor chip 12 and the inner lead 16 to form the lead frame 13. The bottom surface of the batam lead 15 and the paddle 14 is exposed to the lower surface of the package body 11 to lead plating. According to the present invention as described above there is an advantage that the heat release characteristics of the package and the workability of the manufacturing operation is improved and the manufacturing cost is reduced.
Description
제1도는 종래 기술에 의한 비엘피 패키지의 단면구조를 도시한 단면도.1 is a cross-sectional view showing a cross-sectional structure of the BLP package according to the prior art.
제2도는 종래 기술에 의한 비엘피 패키지의 저면구조를 도시한 저면도.2 is a bottom view showing the bottom structure of the BLP package according to the prior art.
제3도는 본 발명에 의한 비엘피 패키지의 일실시례의 단면구조를 도시한 단면도.3 is a cross-sectional view showing a cross-sectional structure of an embodiment of a BLP package according to the present invention.
제4도는 본 발명에 의한 비엘피 패키지의 일실시례의 저면구조를 도시한 저면도.Figure 4 is a bottom view showing the bottom structure of one embodiment of a BLP package according to the present invention.
제5도는 본 발명에 의한 비엘피 패키지의 다른 실시례의 단면구조를 도시한 단면도.5 is a cross-sectional view showing a cross-sectional structure of another embodiment of a BLP package according to the present invention.
제6도는 본 발명에 의한 비엘피 패키지의 다른 실시례의 저면구조를 도시한 저면도.Figure 6 is a bottom view showing the bottom structure of another embodiment of a BLP package according to the present invention.
제7도는 본 발명에 의한 비엘피 패키지의 제조방법을 순차적으로 표시한 순서도.7 is a flow chart sequentially showing the manufacturing method of the BLP package according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 패키지몸체 12 : 반도체칩11: package body 12: semiconductor chip
12' : 칩패드 13 : 리드프레임12 ': chip pad 13: lead frame
14 : 패들 15 : 바탐리드14: paddle 15: batam lead
15' : 납도금 16 : 인너리드15 ': Lead Plating 16: Inner Lead
17 : 접착제 18 : 와이어17: adhesive 18: wire
본 발명은 비엘피(Bottom Leaded Package)패키지에 관한 것으로, 반도체칩을 리드프레임의 패들상에 접착제를 사용, 부착하여 작업성 및 열방출성을 개선한 비엘피 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BLP package, and to a BLP package having improved workability and heat dissipation by attaching and attaching a semiconductor chip to a paddle of a lead frame.
제1도는 종래 기술에 의한 비엘피 패키지의 단면구조를 도시한 단면도이고, 제2도는 종래 기술에 의한 비엘피 패키지의 저면구조를 도시한 저면도이다.1 is a cross-sectional view showing a cross-sectional structure of the BLP package according to the prior art, and FIG. 2 is a bottom view showing the bottom structure of the BLP package according to the prior art.
이에 도시된 바와 같이, 종래 기술에 의한 비엘피 패키지(1)는 반도체칩(2)이 리드프레임(3)의 바탐리드(5)상에 부착되어 있고, 상기 반도체칩(2)의 본드패드(2')와 리드프레임(3)의 인너리드(4)가 와이어(6)로 본딩되어 있으며, 상기 반도체칩(2)과 리드프레임(3)이 일정 면적 몰딩되어 패키지몸체(1')를 형성하게 된다.As shown in the drawing, in the BLP package 1 according to the related art, the semiconductor chip 2 is attached to the battam lead 5 of the lead frame 3, and the bond pads of the semiconductor chip 2 are formed. 2 ') and the inner lead 4 of the lead frame 3 are bonded to the wire 6, and the semiconductor chip 2 and the lead frame 3 are molded in a predetermined area to form the package body 1'. Done.
상기 바탐리드(5)는, 제2도에 도시된 바와 같이, 패키지몸체(1')의 저면으로 드러나도록 몰딩되어 있으며, 이와 같이 패키지몸체(1')의 저면으로 드러나 있는 바탐리드(5)에는 바탐리드(5)의 부식을 방지하고 기판(미도시)에의 실장을 용이하게 하기 위한 납도금(5')이 되어 있다.As shown in FIG. 2, the battam lead 5 is molded to be exposed to the bottom of the package body 1 ′, and thus the battam lead 5 exposed to the bottom of the package body 1 ′. The lead plating 5 'is used to prevent corrosion of the battam lead 5 and to facilitate mounting on the substrate (not shown).
상기 바탐리드(5)상에 반도체칩(2)을 부착하는 것은 접착테이프나 고형접착제를 사용하여 수행하게 된다.Attaching the semiconductor chip 2 on the battam lead (5) is performed using an adhesive tape or a solid adhesive.
상기한 바와 같은 종래 기술에 의한 비엘피 패키지(1)를 제조하는 방법은 다음과 같다.The method of manufacturing the BLP package 1 according to the prior art as described above is as follows.
먼저, 바탐리드(5) 상부에 반도체칩(2)을 부착을 위한 접착테이프나 고형접착제(7)가 구비된 리드프레임(3)에 반도체칩(2)을 부착하고 와이어(6)를 사용하여 상기 반도체칩(2)의 본드패드(2')와 인너리드(4)를 전기적으로 연결하여 준다.First, the semiconductor chip 2 is attached to the lead frame 3 having the adhesive tape or the solid adhesive 7 for attaching the semiconductor chip 2 to the top of the battam lead 5, and then using the wire 6. The bond pad 2 'and the inner lead 4 of the semiconductor chip 2 are electrically connected to each other.
그리고, 상기 반도체칩(2)과 리드프레임(3)을 외부의 충격이나 환경으로부터 보호하기 위해 일정면적 몰딩하여 패키지몸체(1')를 형성하여 주게 된다. 이때, 상기 리드프레임(3)의 바탐리드(5)는 상기 패키지몸체(1')의 저면으로 드러나도록하여 준다.In order to protect the semiconductor chip 2 and the lead frame 3 from external impact or the environment, a predetermined area is molded to form the package body 1 ′. At this time, the battam lead 5 of the lead frame 3 is exposed to the bottom surface of the package body (1 ').
상기와 같이 한 후, 상기 패키지몸체(1')의 저면으로 드러나 있는 바탐리드(5)상에 납도금(5')을하여 패키지(1)를 기판(미도시)상에 실장할 때 납땜성을 좋게 하고 바탐리드(5)의 부식을 방지하여 주도록 한다.After the above, the soldering property when the package 1 is mounted on a substrate (not shown) by performing a lead plating 5 'on the battam lead 5 exposed to the bottom surface of the package body 1'. Good to prevent the corrosion of the battam lead (5).
그러나, 상기한 바와 같은 종래 기술에 의한 비엘피 패키지(1)는 반도체칩(2)과 리드프레임(3)의 접착을 위해 고형접착제나 접착테이프(7)를 사용하게 되는데, 이와 같은 접착테이프나 고형접착제(7)는 고가의 제품이며 이와 같은 접착제부착을 위한 공정이 추가됨으로 인한 패키지제조작업의 작업성 저하되는 문제점이 있다.However, the BLP package 1 according to the prior art as described above uses a solid adhesive or an adhesive tape 7 to bond the semiconductor chip 2 and the lead frame 3. The solid adhesive 7 is an expensive product and there is a problem in that workability of a package manufacturing operation is reduced due to the addition of a process for attaching such an adhesive.
그리고, 상기와 같이 리드프레임(3)의 바탐리드(5) 상부에 구비된 고형접착제나 접착테이프(7)에 반도체칩(2)을 부착하는 작업은 매우 번거로운 작업이므로 작업성이 떨어지고 이와 같은 작업을 위한 설비가 고가이어서 제조원가가 크게 높아지는 문제점이 있다.As described above, the operation of attaching the semiconductor chip 2 to the solid adhesive or the adhesive tape 7 provided on the battam lead 5 of the lead frame 3 is very cumbersome, resulting in poor workability. There is a problem that the manufacturing cost is greatly increased because the equipment for the expensive.
또한 상기와 같은 종래 기술에 의한 비엘피 패키지(1)에서는 반도체칩(2)에서 발생되는 열이 패키지몸체(1')의 외부로 방출될 수 있는 통로가 바탐리드(5)밖에 없어 열방출특성이 좋지 않은 문제점이 있다.In addition, in the BLP package 1 according to the related art, there is only a batam lead 5 through which the heat generated from the semiconductor chip 2 can be released to the outside of the package body 1 ′. This is a bad problem.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로 반도체칩을 리드프레임에 부착하는 공정을 저가의 접착제를 사용하여 용이하게 수행하도록 하는 것이다.An object of the present invention is to solve the problems of the prior art as described above to facilitate the process of attaching a semiconductor chip to a lead frame using a low-cost adhesive.
본 발명의 다른 목적은 반도체칩에서 발생되는 열을 패키지몸체의 외부로 보다 원활하고 신속하게 방출하여 반도체칩의 동작특성을 향상시키는 것이다.Another object of the present invention to improve the operating characteristics of the semiconductor chip by releasing heat generated from the semiconductor chip to the outside of the package body more smoothly and quickly.
상기한 바와 같은 본 발명의 목적은 리드프레임의 패들에 액체형 접착제를 사용하여 반도체칩을 부착하고, 상기 리드프레임의 인너리드와 상기 반도체칩의 칩패드를 와이어로 연결하며, 상기 반도체칩과 인너리드를 일정면적몰딩하여 패키지몸체를 형성하여, 상기 리드프레임의 바탐리드와 패들의 하면을 패키지몸체의 하면으로 드러나도록하여 납도금함을 특징으로 하는 비엘피 패키지에 의해 달성된다.An object of the present invention as described above is to attach a semiconductor chip using a liquid adhesive to the paddle of the lead frame, connecting the inner lead of the lead frame and the chip pad of the semiconductor chip with a wire, the semiconductor chip and the inner lead It is achieved by the BLP package, characterized in that by molding a certain area to form a package body, the lower surface of the battam lead and paddle of the lead frame to be exposed to the lower surface of the package body.
상기 패들에는 다수개의 요입부를 구비하여 상기 리드프레임의 바탐리드가 위치되도록하여 상기 바탐리드를 통해 반도체칩에서 발생되는 열을 방출하도록 된다.The paddle is provided with a plurality of recesses so that the battam lead of the lead frame is positioned to dissipate heat generated from the semiconductor chip through the battam lead.
한편, 상기 패키지몸체의 하면으로 드러난 바탐리드에만 납도금하고 패들의 하면에는 납도금하지 않을 수도 있으며, 상기 패들에는 방향표시부가 구비된다.On the other hand, it may be lead-plated only to the batam lead exposed to the lower surface of the package body and not to the lower surface of the paddle, the direction of the paddle is provided.
상기한 바와 같은 본 발명에 의한 비엘피 패키지의 실시례들을 첨부된 도면을 참고하여 상세히 설명하면 다음과 같다.Embodiments of the BLP package according to the present invention as described above will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 의한 비엘피 패키지의 일실시례의 단면구조를 도시한 단면도이고, 제4도는 본 발명에 의한 비엘피 패키지의 일실시례의 저면구조를 도시한 저면도이다.3 is a cross-sectional view showing a cross-sectional structure of one embodiment of a BLP package according to the present invention, and FIG. 4 is a bottom view showing a bottom structure of an embodiment of a BLP package according to the present invention.
이에 도시된 바와 같이, 본 발명의 일실시례에 의한 비엘피 패키지(10)는 리드프레임(13)의 패들(14)에 액체형 접착제 또는 에폭시수지(17)를 사용하여 반도체칩(12)을 부착하고, 상기 리드프레임(13)의 인너리드(16)와 상기 반도체칩(12)의 칩패드(12')를 와이어(18)로 연결함, 상기 반도체칩(12)과 인너리드(16)를 일정면적몰딩하여 패키지몸체(11)를 형성하여 구성된다.As shown in the drawing, the BLP package 10 according to an embodiment of the present invention attaches the semiconductor chip 12 to the paddle 14 of the lead frame 13 by using a liquid adhesive or an epoxy resin 17. The inner lead 16 of the lead frame 13 and the chip pad 12 ′ of the semiconductor chip 12 are connected by wires 18, and the semiconductor chip 12 and the inner lead 16 are connected to each other. It is formed by forming a package body 11 by molding a predetermined area.
그리고, 상기 패키지몸체(11)를 형성할 때, 상기 리드프레임(13)의 바탐리드(15)와 패들(14)의 하면을 패키지몸체(11)의 하면으로 드러나도록하여 바탐리드(15)와 패들(14)의 부식을 방지하고 기판(미도시)상에의 실장이 용이하게 수행되도록 납도금(15', 14')하여 준다. 그러나, 이와 같은 납도금(15')은 상기 바탐리드(15)에만 수행하여 줄 수도 있다.When the package body 11 is formed, the bottom surface of the battam lead 15 and the paddle 14 of the lead frame 13 is exposed to the bottom surface of the package body 11 so as to expose the battam lead 15. Lead plating 15 'and 14' is provided to prevent corrosion of the paddle 14 and to facilitate mounting on a substrate (not shown). However, such lead plating 15 ′ may be performed only on the battam lead 15.
그리고 상기 리드프레임(13)의 바탐리드(15)는 제4도에 도시된 바와 같이, 패들(14)의 양측에 나란히 배열된다.And the battam lead 15 of the lead frame 13 is arranged side by side on both sides of the paddle 14, as shown in FIG.
또한, 상기 패들(14)의 일측에는 패키지의 방향표시를 위한 방향표시부(14P)가 구비된다.In addition, one side of the paddle 14 is provided with a direction display unit 14P for displaying the direction of the package.
상기한 바와 같은 본 발명의 일실시례에 의한 비엘피 패키지(10)의 작용효과는 다음과 같다.Effects of the BLP package 10 according to an embodiment of the present invention as described above are as follows.
상기와 같은 본 발명에 의한 비엘피 패키지(10)는 종래의 비엘피 패키지와는 달리 반도체칩(12)을 리드프레임(13)의 패들(14)에 에폭시수지나 액체형접착제(17)를 사용하여 접착시켜 주므로 제조작업의 작업성이 좋아지게 된다. 그리고, 그 저면이 패키지몸체(11)의 저면으로 드러나 있는 패들(14)상에 반도체칩(12)이 부착되어 있으므로 반도체칩(12)에서 발생되는 열의 방출이 원활하게 이루어지게 된다.In the BLP package 10 according to the present invention as described above, unlike the conventional BLP package, the semiconductor chip 12 uses the epoxy resin or the liquid adhesive 17 to the paddle 14 of the lead frame 13. Because of the adhesion, the workability of the manufacturing work is improved. Since the semiconductor chip 12 is attached to the paddle 14 whose bottom surface is exposed to the bottom of the package body 11, the heat generated from the semiconductor chip 12 is smoothly discharged.
한편, 본 발명에 의한 다른 실시례의 비엘피 패키지(11')가 제5도 및 제6도에 도시되어 있는데, 이에 도시된 바와 같이 본 발명의 다른 실시례의 구성을 반도체칩(12)이 부착되는 리드프레임(13)의 패들(14)에 다수개의 요입부(14G)를 구비하고 이와 같은 요입부(14G)에 리드프레임(13)의 바탐리드(15)가 위치되도록 한 것이다.Meanwhile, the BLP package 11 ′ of another embodiment according to the present invention is shown in FIGS. 5 and 6, and as shown in FIG. The paddle 14 of the lead frame 13 to be attached is provided with a plurality of recesses 14G, and the battam lead 15 of the lead frame 13 is positioned at the recesses 14G.
상기와 같이 되면 제5도에 도시된 바와 같이 패들(14)에 부착되어 있는 반도체칩(12)의 양측변 하측과 상기 리드프레임(13)의 바탐리드(15)의 상면이 인접하게 되어 상기 바탐리드(15)를 통해서도 반도체칩(12)에서 발생되는 열이 방출된다.In this case, as shown in FIG. 5, the lower side of both sides of the semiconductor chip 12 attached to the paddle 14 and the upper surface of the battam lead 15 of the lead frame 13 are adjacent to each other. Heat generated in the semiconductor chip 12 is also released through the lead 15.
그리고, 상기 반도체칩(12)을 리드프레임(13)의 상면에 부착하는 것은 에폭시수지나 액체형 접착제(17)를 사용하여서 이루어진다.The semiconductor chip 12 is attached to the upper surface of the lead frame 13 by using an epoxy resin or a liquid adhesive 17.
이와 같은 본 발명의 다른 실시례에 의한 비엘피 패키지(11')도 역시 패들(14)에 방향표시부(14P)가 구비되어 있다.The BLP package 11 ′ according to another embodiment of the present invention is also provided with a direction display portion 14P on the paddle 14.
그외의 다른 구성은 본 발명의 상기 일실시례와 동일하므로 여기서는 그 설명을 생략한다.Other configurations are the same as the above-described embodiment of the present invention, so the description thereof is omitted here.
상기한 바와 같은 본 발명의 다른 실시례에 의한 비엘피 패키지(11')의 작용효과는 다음과 같다.Effects of the BLP package 11 'according to another embodiment of the present invention as described above are as follows.
즉, 반도체칩(12)을 리드프레임(13)의 패들(14)에 액체형 접착제나 에폭시수지(17)를 사용하여 부착하게 되므로 그 작업이 매우 용이하게 수행된다. 그리고 상기와 같은 비엘피 패키지(11')가 사용될 때, 반도체칩(12)에서 발생되는 열은 반도체칩(12)이 부착되어 있는 패들(14)을 통해서 패키지몸체(11)의 외부로 방출될 뿐 만 아니라, 상기 패들(14)의 요입부(14G)에 배치되어 반도체칩(12)의 하면에 위치되는 리드프레임(13)의 바탐리드(15)를 통해서도 이루어지게 되므로 열방출이 매우 원활하게 된다.That is, since the semiconductor chip 12 is attached to the paddle 14 of the lead frame 13 using a liquid adhesive or epoxy resin 17, the operation is very easily performed. When the BLP package 11 'is used as described above, heat generated from the semiconductor chip 12 may be discharged to the outside of the package body 11 through the paddle 14 to which the semiconductor chip 12 is attached. In addition, heat dissipation is very smoothly performed through the battam lead 15 of the lead frame 13 disposed on the recess 14G of the paddle 14 and positioned on the bottom surface of the semiconductor chip 12. do.
상기에서 설명한 본 발명에 의한 비엘피 패키지의 제조방법을 설명하면 다음과 같다.Referring to the manufacturing method of the BLP package according to the present invention described above are as follows.
먼저, 리드프레임(13)의 패들(14) 상면에 에폭시수지나 액체형 접착제(17)를 도포하고 반도체칩(12)을 부착하여 준다. 그리고, 와이어(18)를 사용하여 반도체칩(12)의 패드(12')와 리드프레임(13)의 인너리드(16)를 전기적으로 결선시킨다.First, an epoxy resin or a liquid adhesive 17 is applied to the upper surface of the paddle 14 of the lead frame 13 and the semiconductor chip 12 is attached. Then, the wire 18 is used to electrically connect the pad 12 ′ of the semiconductor chip 12 and the inner lead 16 of the lead frame 13.
그리고, 상기 반도체칩(12)과 인너리드(16) 및 와이어(18) 등을 외부의 충격이나 환경으로부터 보호하기 위해 일정면적 몰딩하여 패키지몸체(11)를 형성하여 주게 된다. 이때, 상기 리드프레임(13)의 바탐리드(15)와 패들(14)의 저면은 패키지몸체(11)의 저면으로 드러나도록 한다.In order to protect the semiconductor chip 12, the inner lead 16, the wire 18, and the like from an external impact or environment, the package body 11 is formed by molding a predetermined area. At this time, the bottom of the battam lead 15 and the paddle 14 of the lead frame 13 is exposed to the bottom of the package body (11).
상기와 같이 한 후, 상기 패키지몸체(11)의 저면으로 드러나 있는 바탐리드(15) 및 패들(14)에 납도금(15', 14')을 하여 패키지(10)를 기판(미도시)상에 실장할 때 납땜성을 좋게 하고 바탐리드(15) 및 패들(14)의 부식을 방지한다. 이와 같은 납도금은 필요한 경우 상기 바탐리드(15)에만 수행할 수도 있다.After the above process, lead plating 15 ′ and 14 ′ are applied to the battam lead 15 and the paddle 14 exposed to the bottom surface of the package body 11 to form the package 10 on a substrate (not shown). The solderability is improved when mounted on the and the corrosion of the battam lead 15 and the paddle 14 is prevented. Such lead plating may be performed only on the battam lead 15 if necessary.
그리고 나서, 절단작업과 외관검사 및 전기적기능검사 등을 수행하여 단품패키지를 완성하게 된다.Then, the cutting and visual inspection and electrical functional inspection is performed to complete the single package.
위에서 상세히 설명한 바와 같은 본 발명에 의한 비엘피 패키지는 반도체칩을 리드프레임의 리드상에 부착하지 않고 패들에 액체형 접착제나 에폭시수지를 사용하여 접착하여 주게 되므로 반도체칩 부착작업의 작업성이 현저하게 개선됨은 물론 제조원가의 면에서도 많은 절감효과를 가져올 수 있다.(일반적으로 리드프레임의 리드에 접착테이프나 고형접착제가 구비되어 있는 것은 그렇지 않은 것에 비해 제조원가가 5배이상 높다.)The BLP package according to the present invention as described above is attached to the paddle using a liquid adhesive or epoxy resin without attaching the semiconductor chip on the lead of the lead frame, thereby significantly improving the workability of the semiconductor chip attaching operation. Of course, it can also bring a lot of savings in terms of manufacturing cost. (In general, the adhesive tape or solid adhesive is provided on the lead of the lead frame, which is 5 times higher than the manufacturing cost.)
그리고, 반도체칩에서 발생되는 열을 패들이나 바탐리드를 통해 패키지몸체의 외부로 원활하게 방출할 수 있으므로 열방출이 원활하게 이루어져 패키지의 열특성이 개선되는 효과가 있으며, 패들에 패키지 방향표시부가 구비되어 있어 패키지의 방향식별이 용이하게 되는 효과가 있다.In addition, since the heat generated from the semiconductor chip can be smoothly discharged to the outside of the package body through the paddle or battam lead, the heat is released smoothly to improve the thermal characteristics of the package, and the package direction indicator is provided on the paddle. Since the direction of the package can be easily identified.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950068662A KR0179808B1 (en) | 1995-12-30 | 1995-12-30 | Blp package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950068662A KR0179808B1 (en) | 1995-12-30 | 1995-12-30 | Blp package |
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| KR970053779A KR970053779A (en) | 1997-07-31 |
| KR0179808B1 true KR0179808B1 (en) | 1999-03-20 |
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| KR1019950068662A KR0179808B1 (en) | 1995-12-30 | 1995-12-30 | Blp package |
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