KR940006580B1 - Semicondoctor package structure and manufacturing method thereof - Google Patents
Semicondoctor package structure and manufacturing method thereof Download PDFInfo
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- KR940006580B1 KR940006580B1 KR1019910018124A KR910018124A KR940006580B1 KR 940006580 B1 KR940006580 B1 KR 940006580B1 KR 1019910018124 A KR1019910018124 A KR 1019910018124A KR 910018124 A KR910018124 A KR 910018124A KR 940006580 B1 KR940006580 B1 KR 940006580B1
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- adhesive
- semiconductor chip
- package
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
제1도 및 제2도는 통상적인 반도체 패키지의 구성을 보이는 단면도로서, 제1도는 SOJ타입(Small Out Lead J-form Type)1 and 2 are cross-sectional views showing the structure of a conventional semiconductor package, and FIG. 1 is a small out lead J-form type.
제 2 도는 SOP타입 (Small Out Lead Package)2nd figure is SOP type (Small Out Lead Package)
제3도의 (a)(b)는 종래의 반도체 패키지에 사용되는 리드프레임의 구조도.3A and 3B are structural diagrams of a lead frame used in a conventional semiconductor package.
제4도는 본 발명에 의한 접착리드를 이용한 반도체 패키지의 구성을 보이는 단면도.4 is a cross-sectional view showing the configuration of a semiconductor package using the adhesive lead according to the present invention.
제5도는 본 발명에 의한 접착리드에 반도체칩이 와이어본딩된 상태를 도시한 평면도.5 is a plan view showing a state in which a semiconductor chip is wire-bonded to an adhesive lead according to the present invention.
제6도는 제5도의 저면도.6 is a bottom view of FIG.
제7도는 제5도의 A부 상세도.7 is a detailed view of portion A of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체칩 12 : 접착리드11 semiconductor chip 12 adhesive lead
12a : 안착부 12b,12c : 내·외부리드12a: Seating part 12b, 12c: Inner and outer lead
13 : 금속와이어 14 : 에폭시몰딩컴파운드(EMC)13: metal wire 14: epoxy molding compound (EMC)
17 : 접착제 18 : 폴리이미드계접착테이프17 adhesive 18 polyimide adhesive tape
본 발명은 접착리드를 이용한 반도체 패키지 구조 및 그 제조방법에 관한 것으로, 특히 종래의 리드프레임 사용을 배제하고 패키지의 저면부로 패키지 실장을 위한 복수개의 접착리드가 노출되도록 하여 인쇄회로기판(PCB)상에 실장시킬 수 있도록 구성함으로써 실장면적을 줄이고 내습성 및 전기적 특성을 향상시키며 패키지 제조원가 절감에 적당하도록 한 접착리드를 이용한 반도체 패키지 구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure using an adhesive lead and a method of manufacturing the same. In particular, a plurality of adhesive leads for package mounting are exposed on a bottom surface of a package without the use of a conventional lead frame, thereby printing on a PCB. The present invention relates to a semiconductor package structure using an adhesive lead and a method for manufacturing the same, which reduce the mounting area, improve moisture resistance and electrical properties, and reduce the cost of manufacturing a package.
일반적인 리드프레임을 이용한 플라스틱 반도체 패키지는 통상 다음과 같은 공정의 순으로 제작되는 바,이를 간단히 설명하면 다음과 같다.A plastic semiconductor package using a general lead frame is usually manufactured in the following order, which is briefly described as follows.
즉, 통상적인 플라스틱 반도체 패키지의 제조공정은 소잉(Sawing)공정을 거친 반도체칩을 리드프레임의 패들위에 부착하는 다이어태치(Die Attachment)공정과, 그 반도체칩의 외부연결단자인 본드패드와 리드프레임의 인너리드를 와이어를 이용하여 전기적으로 접속 연결하는 와이어본딩(Wire Bonding)공정과, 와이어본딩공정이 끝난 칩을 보호하기 위해 상기 반도체칩과 리드프레임의 아웃리드를 포함하는 일정부위를 몰딩컴파운드를 이용하여 밀폐시키는 몰딩(Molding)공정과, 몰딩이 끝난 패키지에 연결되어 있는 리드프레임의 리드와 리드사이의 댐버(Dam Bar)를 절단하는 트리밍(Trimming) 공정과, 트리밍이 끝난 패키지의 리드를 절곡하여 모양을 헝성하는 포밍(forming) 공정과, 통상적인 플래팅(Plating) 공정 및 마이킹(Marking) 공정의 순으로 제작되며, 상기 포밍공정에 의한 리드의 절곡 모양에 따라 SOJ(Small Out Lead J-form)패키지, SOP, DIP, QFP등의 종류로 구분된다.In other words, the manufacturing process of a conventional plastic semiconductor package includes a die attach process for attaching a sawing process to a paddle of a lead frame, and a bond pad and lead frame, which are external connection terminals of the semiconductor chip. Wire bonding process for electrically connecting and connecting the inner lead using a wire, and a molding compound is formed in a predetermined portion including the out lead of the semiconductor chip and the lead frame to protect the chip after the wire bonding process is completed. Molding process to seal by using, Trimming process to cut the dam between the lead and lead of the lead frame connected to the molded package, and bending the lead of the trimmed package Forming in order of forming a shape, and then forming a fabric in order of a conventional plating process and a marking process. According to the bending shape of the lead is divided into according to the kinds of SOJ (Small Out Lead J-form) package, SOP, DIP, QFP.
상기한 바와 같은 제조공정을 통하여 제작된 종래의 반도체 패키지가 제1도 및 제2도에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.Conventional semiconductor packages fabricated through the manufacturing process as described above are shown in FIGS. 1 and 2, which will be briefly described as follows.
즉, 제1도는 패키지의 리드가 제이-폼(J-form) 형태인 SOJ타입 반도체 패키지의 구성을 보이는 단면도이고, 제2도는 리드의 형태가 걸-폼(Gu1l form)인 SOP타입 패키지의 단면도로서, 이에 도시한 바와같이 종래의 반도체 패키지는 리드프레임(1)의 패들(2)위에 반도체칩(3)이 접착제(4)에 의해 부착고정되고, 상기 반도체칩(3)은 금속와이어(5)에 의해 리드프레임(1)의 인너리드(6)와 전기적으로 접속연결되며, 에폭시몰딩컴파운드(7)에 의해 몰딩된 구성으로 되어 있다.That is, FIG. 1 is a cross-sectional view showing the configuration of an SOJ type semiconductor package in which the lead of the package is J-form, and FIG. 2 is a cross-sectional view of the SOP type package in which the lead is gu- form. As shown in the drawing, the conventional semiconductor package is fixed to the semiconductor chip 3 by the adhesive 4 on the paddle 2 of the lead frame 1, the semiconductor chip 3 is a metal wire (5) Is electrically connected to the inner lead 6 of the lead frame 1, and is molded by the epoxy molding compound 7.
도면에서 미설명 부호 8은 리드프레임(1)의 아웃리드를 보인 것이고, 9는 인쇄회로기판(PCB)을 보인 것이며, 10은 상기의 아웃리드(8)를 인쇄회로기판(9)에 접속고정하기 위한 솔더를 보인 것이다.In the drawing, reference numeral 8 denotes an outlead of the lead frame 1, 9 denotes a printed circuit board (PCB), and 10 denotes the connection of the outlead 8 to the printed circuit board 9. I showed solder to do it.
제3도의 (a)(b)는 일반적인 리드프레임의 패들 위에 반도체칩이 부착고정되어 와이어본딩된 상태를 도시한 평면도로서 이에 도시한 바와같이 반도체칩(3)의 양측 가장자리에 구비된 복수개의 본드패드(3a)와 리드프레임(1)의 인너리드(6)가 금속와이어(5)에 의해 전기적으로 접속 연결되어 있다.(A) and (b) of FIG. 3 is a plan view showing a state in which a semiconductor chip is attached and fixed to a paddle of a general lead frame, and a plurality of bonds provided at both edges of the semiconductor chip 3 as shown in FIG. The pad 3a and the inner lead 6 of the lead frame 1 are electrically connected to each other by the metal wire 5.
그러나 상기한 바와 같은 종래의 반도체 패키지는 반도체 패키지를 인쇄회로기판에 실장시 패키지의 몰딩부위 밖으로 리드프레임(1)의 아웃리드(9)가 돌출되는 구조이므로 실장면적이 많이 필요하게 되고, 패키지내에 금속성의 패들(2)이 존재하게 되므로 리플로워 솔더(Reflow Solder)시 칩(3)과 패들(2)간의 열팽창계수 차이로 인한 패키지 깨짐 불량이 발생하는 것이었으며, 아웃리드(8)와 본드패드(3a)간의 거리가 길어 전기적 특성이 저하되는 결함이 있었다.However, the conventional semiconductor package as described above has a structure in which the outlead 9 of the lead frame 1 protrudes out of the molding part of the package when the semiconductor package is mounted on a printed circuit board, and thus requires a large mounting area. Since the metallic paddle 2 is present, a package breakage defect occurs due to the difference in thermal expansion coefficient between the chip 3 and the paddle 2 during reflow soldering. The outlead 8 and the bond pad The distance between (3a) was long, and there existed a defect in which an electrical characteristic fell.
또한, 몰딩이후의 공정 즉, 트리밍/포밍공정등이 필요하므로 패키지의 제조원가가 상승하는 등의 결함이 있는 것이었다.In addition, a process after molding, i.e., a trimming / forming process, is required, so that the manufacturing cost of the package is increased.
이를 감안하여 창안한 본 발명의 목적은 종래의 리드프레임 사용을 배제하고 패키지의 저면부로 복수개의 접착리드가 노출되도록 하여 인쇄회로기판(PCB)에 실장시킬 수 있도록 구성함으로써 상술한 바와 같은 종래의 여러문제점을 해소할 수 있는 접착리드를 이용한 반도체 패키지를 제공함에 있다.In view of this, an object of the present invention is to eliminate the use of a conventional lead frame and to allow a plurality of adhesive leads to be exposed to the bottom of the package to be mounted on a printed circuit board (PCB). It is to provide a semiconductor package using an adhesive lead that can solve the problem.
본 발명의 다른 목적은 접착리드를 사용함으로써 몰딩이후의 공정을 제거하여 패키지 제조원가를 절감시킬 수 있는 접착리드를 이용한 반도체 패키지 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor package using an adhesive lead that can reduce the manufacturing cost of the package by removing the process after molding by using the adhesive lead.
상기한 바와 같은 목적을 갖는 본 발명은 폴리이미드계 접착테이프에 복수개의 접착리드를 부착하여 그위에 반도체칩을 부착하고 와이어본딩한 후, 에폭시수지등으로 몰딩하여 경화시킨 다음 상기 폴리이미드계 접착테이프를 제거하여 접착리드의 하면 즉, 실장용 외부리드가 몰딩부위의 저면으로 노출되도록 제작함으로써 달성되는 것이다.According to the present invention having the above object, a plurality of adhesive leads are attached to a polyimide adhesive tape, a semiconductor chip is attached thereto and wire-bonded, and then cured by molding with an epoxy resin or the like. It is achieved by removing so that the lower surface of the adhesive lead, that is, the mounting external lead is exposed to the bottom of the molding portion.
이와같이 된 본 발명에 의한 반도체 패키지는 몰딩부위의 외부로 돌출되는 리드가 없으므로 실장면적을 줄일 수 있고 내습성 및 전기적 특성을 향상시킬 수 있으며 몰딩이후의 공정을 제거할 수 있으므로 패키지 제조원가를 절감시킬 수 있는 등의 여러 이점이 있다.Since the semiconductor package according to the present invention has no leads protruding to the outside of the molding part, the mounting area can be reduced, the moisture resistance and electrical properties can be improved, and the process after molding can be eliminated, thereby reducing the package manufacturing cost. There are several advantages, such as being.
이하에서는 이와같은 본 발명을 첨부한 도면 제4도 내지 제7도를 참조하여 보다 상세히 설명하겠다.Hereinafter will be described in more detail with reference to FIGS. 4 to 7 attached to the present invention.
제4도는 본 발명에 의한 접착리드를 이용한 반도체 패키지의 구성을 보이는 단면도이고, 제5도는 접착리드에 반도체칩이 부착되어 와이어본딩된 상태를 보이는 평면도로서 이에 도시한 바와같이 본 발명에 의한 반도체 패키지는 반도체칩(11)과, 그 반도체칩(11)이 안착되는 안착부(12a)가 구비되며, 반도체칩(11)과의 접속을 위한 내부리드(12b) 및 실장용 외부리드(12c)를 가지는 접착리드(l2)와, 내부리드(12b)를 전기적으로 접속연결하는 금속와이어(13)와, 상기 반도체칩(11)을 보호하기 위해 몰딩하는 에폭시몰딩컴파운드(14)로 구성되어 있으며, 실장시 패키지의 저면으로 노출된 접착리드(12)의 외부리드(l2c)를 이용하여 인쇄회로기판(15)상에 솔더(Solder)(16)를 이용 직접 실장하도록 되어 있다.4 is a cross-sectional view showing the configuration of a semiconductor package using an adhesive lead according to the present invention, Figure 5 is a plan view showing a state in which a semiconductor chip is attached to the adhesive lead wire bonded as shown in the semiconductor package according to the present invention Is provided with a semiconductor chip 11 and a seating portion 12a on which the semiconductor chip 11 is mounted, and includes an inner lead 12b and a mounting outer lead 12c for connection with the semiconductor chip 11. The branch is composed of an adhesive lead l2, a metal wire 13 for electrically connecting and connecting the inner lead 12b, and an epoxy molding compound 14 molded to protect the semiconductor chip 11. The solder 16 is directly mounted on the printed circuit board 15 by using the outer lead l2c of the adhesive lead 12 exposed to the bottom of the sea package.
그리고, 반도체칩(11)은 접착제(17)에 의해 접착리드(12)의 안착부(12a)에 부착고정되며, 상기 접착제(17)는 폴리이미드계 접착제나 절연성 페이스트를 이용할 수 있다.The semiconductor chip 11 is fixed to the seating portion 12a of the adhesive lead 12 by the adhesive 17, and the adhesive 17 may use a polyimide adhesive or an insulating paste.
상기 접착리드(12)는 도면에 도시한 개략 "L"자 형상으로 구성된 것에 한정하지 않고 그외에도 반도체칩이 부착고정되는 안착부(12a)와 전기적 접속을 위한 내부리드(12b) 및 표면실장용 외부리드(12c)를 구비한 어떠한 형상도 무방하며 예를들어, 도면에 도시한 접착리드(12)의 양측면부에 각을 주어 그 상면이 그 하면보다 크게 형성하여 미케니컬 록킹(mechanical locking)을 시킬 수 있도록 구성할 수도 있다.The adhesive lead 12 is not limited to the shape of the "L" shape shown in the drawings, but also for the internal lead 12b and the surface mount for electrical connection with the mounting portion 12a to which the semiconductor chip is fixed. Any shape having an outer lead 12c may be used. For example, angles are provided on both side surfaces of the adhesive lead 12 shown in the drawing, and an upper surface thereof is formed larger than the lower surface thereof so that mechanical locking is achieved. It can also be configured to let.
첨부한 도면 제6도 및 제7도는 본 발명의 이해를 돕기 위한 제5도의 저면도 및 A부 상세도로서 이에 도시한 바와같이 패키지의 저면에는 복수개의 표면실장용 외부리드(12c)들이 노출되어 있고, 반도체칩(11)은 폴리이미드계 접착테이프(l8)에 부착된 접착리드(12)의 안착부(12a)에 부착고정되어 금속와이어(13)에 의해 칩의 본드패드(1la)와 접착리드(12)의 내부리드(12b)가 전기적으로 접속 연결된다.6 and 7 are a bottom view and a detailed view of a portion A of FIG. 5 for better understanding of the present invention. As shown therein, a plurality of surface mount external leads 12c are exposed on the bottom of the package. The semiconductor chip 11 is attached to and fixed to the seating portion 12a of the adhesive lead 12 attached to the polyimide adhesive tape l8 to be bonded to the bond pad 1la of the chip by the metal wire 13. The inner lead 12b of the lead 12 is electrically connected and connected.
이와같이 구성된 본 발명에 의한 반도체 패키지의 제조공정을 살펴보면 다음과 같다.Looking at the manufacturing process of the semiconductor package according to the present invention configured as described above are as follows.
먼저, 폴리이미드계 접착테이프(18)에 복수개의 접착리드(12)를 공급하여 부착하고, 그 접착리드(12)의 안착부(12a)에 폴리이미드계 접착제 및 절연페이스트 등의 접착제(17)로 반도체칩(11)을 부착한다. 칩을 부착한 후 알루미늄이나 구리등의 금속와이어(13)를 이용하여 반도체칩(11)의 본드패드(1la)와 접착리드(12)의 내부리드(12b)를 전기적으로 접속 연결한 다음 에폭시몰딩컴파운드(14)로 몰딩하여 경화시킨다. 다음, 폴리이미드계 접착테이프(18)를 제거하고, 디플래쉬(Deflash)를 실시하여 접착리드(12)의 외부리드(12c)가 패키지의 외부로 노출되도록 함으로써 패키지의 제작이 완료되는 것이다.First, a plurality of adhesive leads 12 are supplied to and attached to the polyimide adhesive tape 18, and an adhesive 17 such as a polyimide adhesive and an insulating paste is attached to the seating portion 12a of the adhesive lead 12. The semiconductor chip 11 is attached thereto. After attaching the chip, the bond pad 1la of the semiconductor chip 11 and the inner lead 12b of the adhesive lead 12 are electrically connected to each other using a metal wire 13 such as aluminum or copper, and then epoxy molding. Molding with compound 14 cures. Next, the fabrication of the package is completed by removing the polyimide adhesive tape 18 and deflashing so that the outer lead 12c of the adhesive lead 12 is exposed to the outside of the package.
이상에서 상세히 설명한 바와같이 본 발명에 의한 반도체 패키지는 접착리드를 사용하여 제작함으로써 실장시 패키지 외부로 돌출되는 아웃리드가 없으므로 실장면적을 줄일 수 있고 강제포밍(forming)으로 인한 패키지의 마이크로갭(Micro Gab)이 제거되므로 내습성이 향상되며, 패키지 내부에 패들이 제거되므로 칩과 패들간의 열팽창계수 차이로 인한 패키지 깨짐 불량을 감소시킬 수 있는 효과와 아울러 와이어본딩을 위한 접착리드의 내부리드와 본드패드와의 거리가 짧아지므로 전기적 특성을 향상시킬 수 있으며 몰딩이후의 공정이 제거되므로 운반시 불량 및 패키지 제조원가를 다운시킬 수 있고 포장이 용이하며 열방출을 극대화시킬 수 있는 등의 효과가 있다.As described in detail above, the semiconductor package according to the present invention is manufactured by using an adhesive lead, so that there is no outlead that protrudes out of the package at the time of mounting, thereby reducing the mounting area and forming a micro gap of the package due to forced forming. Moisture resistance is improved by the removal of Gab), and the paddle is removed inside the package, which reduces the package breakage defect due to the difference in thermal expansion coefficient between the chip and the paddle, and the inner lead and bond of the adhesive lead for wire bonding. As the distance from the pad is shortened, the electrical characteristics can be improved, and the process after molding is eliminated, so that defects in packaging and manufacturing costs can be reduced, packaging is easy, and heat dissipation can be maximized.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910018124A KR940006580B1 (en) | 1991-10-15 | 1991-10-15 | Semicondoctor package structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910018124A KR940006580B1 (en) | 1991-10-15 | 1991-10-15 | Semicondoctor package structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930009035A KR930009035A (en) | 1993-05-22 |
| KR940006580B1 true KR940006580B1 (en) | 1994-07-22 |
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ID=19321272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910018124A KR940006580B1 (en) | 1991-10-15 | 1991-10-15 | Semicondoctor package structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940006580B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393926B1 (en) * | 1997-06-30 | 2003-11-28 | 오끼 덴끼 고오교 가부시끼가이샤 | Mounting structure for electronic parts |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2300698C (en) | 1999-02-19 | 2003-10-07 | J. Garfield Purdon | Broad spectrum decontamination formulation and method of use |
-
1991
- 1991-10-15 KR KR1019910018124A patent/KR940006580B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393926B1 (en) * | 1997-06-30 | 2003-11-28 | 오끼 덴끼 고오교 가부시끼가이샤 | Mounting structure for electronic parts |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930009035A (en) | 1993-05-22 |
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