KR200148118Y1 - Stacked semiconductor package - Google Patents
Stacked semiconductor package Download PDFInfo
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- KR200148118Y1 KR200148118Y1 KR2019950038043U KR19950038043U KR200148118Y1 KR 200148118 Y1 KR200148118 Y1 KR 200148118Y1 KR 2019950038043 U KR2019950038043 U KR 2019950038043U KR 19950038043 U KR19950038043 U KR 19950038043U KR 200148118 Y1 KR200148118 Y1 KR 200148118Y1
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- semiconductor chip
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 고안은 적층형 반도체 패키지에 관한 것으로, 종래의 반도체 패키지는 고밀도의 집적도 향상을 위한 적층이 용이치 못한 문제점이 있었고, 반도체 칩과 인너리드가 에폭시로 몰딩된 형태로서 열방출이 안되어 패키지의 크랙을 발생시키는 문제점이 이었던바, 본 고안은 인너리드(11)를 반도체 칩(10)의 상면까지 연장형성하고, 그 인너리드(11)의 상면이 외부로 노출되도록 몰딩하여, 그 인너리드(11)의 상면에 다른 패키지를 적층할 수 있도록 함으로써 패키지의 집적도 향상이 용이한 효과가 있을뿐 아니라, 상기 노출된 인너리드를 통하여 외부로 열방출이 용이하여 패키지의 크랙발생이 방지되는 효과가 있다.The present invention relates to a stacked semiconductor package, and a conventional semiconductor package has a problem in that stacking is not easy for high density integration, and a semiconductor chip and an inner lead are molded with epoxy to prevent heat from being released as a package. The present invention was a problem that occurs, the present invention extends the inner lead 11 to the upper surface of the semiconductor chip 10, molding the upper surface of the inner lead 11 is exposed to the outside, the inner lead 11 By stacking another package on the upper surface of the package, not only the integration density of the package can be easily improved, but also heat is easily released to the outside through the exposed inner lead, thereby preventing the occurrence of cracking of the package.
Description
제1도는 종래 반도체 패키지의 구성을 보인 종단면도.1 is a longitudinal sectional view showing a configuration of a conventional semiconductor package.
제2도는 본 고안 적층형 반도체 패키지의 구성을 보인 종단면도.Figure 2 is a longitudinal cross-sectional view showing the configuration of the present invention laminated semiconductor package.
제3도는 제2도의 다른 실시예를 보인 종단면도.3 is a longitudinal sectional view showing another embodiment of FIG.
제4도는 제2도의 또다른 실시예를 보인 종단면도.4 is a longitudinal sectional view showing yet another embodiment of FIG.
제5도는 제2도의 또다른 실시예를 보인 종단면도.5 is a longitudinal sectional view showing another embodiment of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10a : 칩패드 10 : 반도체 칩10a: chip pad 10: semiconductor chip
11a : 접착부재 11 : 인너리드11a: adhesive member 11: inner lead
12 : 금속 와이어 13 : 몰딩부12 metal wire 13 molding part
14 : 솔더 15 : 아웃리드14 solder 15 outlead
본 고안은 적층형 반도체 패키지에 관한 것으로, 특히 인너리드(inner lead)를 아웃리드와는 반대방향에서 외부회로에 접속될 수 있게 몰딩부의 일측면으로 부분노출되도록 하고, 그 인너리드의 노출부분에 다른 패키지의 아웃리드(out lead)를 전기접속 상태로 적층할 수 있도록 함으로써 실장밀도를 향상시키도록 하는데 적합한 적층형 반도체 패키지에 관한 것이다.The present invention relates to a stacked semiconductor package, and in particular, to allow the inner lead to be partially exposed to one side of the molding part so that the inner lead can be connected to an external circuit in a direction opposite to the outlead, and is different from the exposed part of the inner lead. The present invention relates to a laminated semiconductor package suitable for improving the mounting density by allowing the out lead of the package to be laminated in an electrically connected state.
제1도는 일반적인 종래 반도체 패키지의 구성을 보인 개략구성도로서, 도시된 바와 같이, 종래의 반도체 패키지는 리드프레임(1)의 패들(1a) 상면에 접착제(2)로 반도체 칩(3)이 부착되어 있고, 상기 리드프레임(1)의 인너리드(1b)와 상기 반도체 칩(3)의 칩패드(3a)는 와이어(4)로 각각 연결되어 있으며, 상기 인너리드(1b), 반도체칩(3), 와이어(4)를 포함하는 일정면적을 에폭시로 몰딩한 몰딩부(5)가 설치되어 있고, 상기 인너리드(1b)에 연장하여 몰딩부(5)의 외측으로는 아웃리드(1c)가 형성되어 있다.FIG. 1 is a schematic diagram showing the structure of a conventional conventional semiconductor package. As shown in the drawing, the semiconductor chip 3 is attached to the upper surface of the paddle 1a of the lead frame 1 with an adhesive 2. The inner lead 1b of the lead frame 1 and the chip pad 3a of the semiconductor chip 3 are connected with wires 4, respectively. The inner lead 1b and the semiconductor chip 3 are connected to each other. ), A molding part 5 in which a predetermined area including the wires 4 is molded with epoxy is provided, and the lead part 1c extends to the inner lead 1b and the outer lead 1c is formed outside the molding part 5. Formed.
상기와 같이 구성되어 있는 종래 반도체 패키지의 제조방법을 설명하면 다음과 같다.Referring to the manufacturing method of the conventional semiconductor package is configured as described above is as follows.
먼저, 리드프레임(1)의 패들(1a) 상면에 접착제(2)를 이용하여 반도체 칩(3)을 부착하는 다이본딩공정을 실시하고, 상기 반도체 칩(3)의 칩패드(3a)와 리드프레임(1)의 인너리드(1b)를 각각 와이어(4)로 연결하는 와이어 본딩공정을 실시하며, 상기 인너리드(1b), 반도체 칩(3), 와이어(4)를 포함하는 일정면적을 에폭시로 몰딩하는 몰딩 공정을 실시하고, 상기 리드프레임(1)의 댐바등 불필요한 부분을 제거하는 트리밍(trimming)공정을 실시하며, 상기 리드프레임(1)의 아웃리드(1c)를 소정의 형태로 절곡하는 포밍(forming)공정을 실시하여 패키지가 완성되는 것이다.First, a die bonding process of attaching the semiconductor chip 3 to the upper surface of the paddle 1a of the lead frame 1 by using an adhesive 2 is performed, and the chip pad 3a and the lead of the semiconductor chip 3 are attached. A wire bonding process of connecting the inner leads 1b of the frame 1 to the wires 4 is performed, and a predetermined area including the inner leads 1b, the semiconductor chip 3, and the wires 4 is epoxy. A molding process of molding the mold, a trimming process of removing unnecessary portions such as a dam bar of the lead frame 1, and bending the outlead 1c of the lead frame 1 to a predetermined shape. The package is completed by performing a forming step.
그러나, 종래의 일반적인 반도체 패키지는 고밀도의 집적도 향상을 위한 적층이 용이치 못한 문제점이 있었고, 반도체 칩(3)과 인너리드(1b)가 에폭시로 몰딩된 형태로서 열방출이 안되어 패키지의 크랙을 발생시키는 문제점이 있었다.However, the conventional semiconductor package has a problem in that stacking is not easy for high density integration, and the semiconductor chip 3 and the inner lead 1b are epoxy-molded to prevent heat dissipation and thus cause cracks in the package. There was a problem letting.
본 고안의 주목적은 상기와 같은 여러 문제점을 갖지 않는 적층형 반도체 패키지를 제공함에 있다.An object of the present invention is to provide a stacked semiconductor package that does not have various problems as described above.
본 고안의 다른 목적은 고밀도 실장을 위한 다른 패키지의 적층이 용이한 적층형 반도체 패키지를 제공함에 있다.Another object of the present invention is to provide a stacked semiconductor package that is easy to stack other packages for high-density mounting.
본 고안의 또다른 목적은 패키지 작동시 외부로의 열방출이 용이하여 패키지의 크랙발생을 방지하도록 하는데 적합한 적층형 반도체 패키지에 관한 것이다.Another object of the present invention relates to a stacked semiconductor package suitable for preventing heat generation of the package by facilitating heat dissipation to the outside during package operation.
상기와 같은 본 고안의 목적을 달성하기 위하여, 일측면에 배열된 칩패드를 가지는 반도체 칩과, 이 반도체 칩 주위에 배열되어 각각 칩패드와 금속 와이어로 접속된 인너리드와, 상기 반도체 칩과 인너리드 주위에 몰딩된 몰딩부와, 각 인너리드에서 연장되어 몰딩부 외부로 돌출되는 아웃리드로 이루어지는 반도체 패키지에 있어서, 상기한 인너리드의 단부가 상기한 반도체 칩의 칩패드가 있는 일측면과 대향하는 타측면 위에 얹히도록 연장 및 벤딩되어 그 타측면에 접착제로 접착되고 그 접착된 단부의 표면이 상기한 몰딩부에서 외부로 노출되며, 상기한 아웃리드가 그 몰딩부의 측면에서 관통되어 인너리드의 노출부분과반대방향에서 접속가능하게 벤딩되어 있는 것을 특징으로 하는 적층형 반도체 패키지가 제공된다.In order to achieve the above object of the present invention, a semiconductor chip having a chip pad arranged on one side, an inner lead arranged around the semiconductor chip and connected to the chip pad and a metal wire, respectively, and the semiconductor chip and inner In a semiconductor package consisting of a molded portion molded around a lead and an outlead extending from each inner lead and protruding out of the molding portion, the end of the inner lead faces one side with the chip pad of the semiconductor chip. Extends and bends so as to rest on the other side, and the surface of the bonded end is exposed to the outside from the molding part, and the outlead penetrates from the side of the molding part so that A stacked semiconductor package is provided which is bent to be connectable in an opposite direction to an exposed portion.
상기와 같은 본 고안 적층형 반도체 패키지의 일실시예를 첨부된 도면을 참고하여 보다 상세히 설명하면 다음과 같다.An embodiment of the inventive layered semiconductor package as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 고안 적층형 반도체 패키지의 구성을 보인 종단면도로서, 도시된 바와 같이, 본 고안의 적층형 반도체 패키지는 반도체 칩(10)의 수개의 칩패드(10a)가 있는 하면과 대향하는 상면으로 수개의 인너리드(11)의 단부가 연장 및 벤딩(bending)되어 테이프 형태의 접착부재(11a)에 의해 그 상면에 부착되어 있고, 상기 반도체 칩(10)의 하면에 형겅되어 있는 수개의 칩패드(10a)와 상기 인너리드(11)의 하면은 금속 와이어(12)로 전기적인 연결이 되어 있으며, 상기 반도체 칩(10)과 인너리드(11) 및 금속 와이어(12)를 포함하는 일정면적은 상기 인너리드(11)의 연장된 단부의 상면이 외부로 노출되도록 에폭시 수지로 몰딩되어 있는 몰딩부(13)가 형성되어 있다.2 is a longitudinal cross-sectional view showing the configuration of the stacked semiconductor package of the present invention. As shown in the drawing, the stacked semiconductor package of the present invention may be formed on the upper surface of the semiconductor chip 10 opposite to the lower surface of the chip pad 10a. Ends of the two inner leads 11 are extended and bent to be attached to the upper surface by the adhesive member 11a in the form of tape, and the plurality of chip pads formed on the lower surface of the semiconductor chip 10 ( 10a) and the lower surface of the inner lead 11 are electrically connected to the metal wire 12, and a predetermined area including the semiconductor chip 10, the inner lead 11, and the metal wire 12 is The molding part 13 molded with an epoxy resin is formed so that the upper surface of the extended end of the inner lead 11 is exposed to the outside.
그리고, 상기 외부로 노출된 수개의 인너리드(11) 단부의 상면에는 상부에 설치되는 다른 패키지의 리드접속부나 외부회로를 접속하는데 용이하게 하는 솔더(14)가 각각 형성되어 있고, 상기 인너리드(11)에는 몰딩부(13)의 측면부를 관통하여 외부로 돌출되도록 연장되고 그 몰딩부(13)의 측면부에서 하면측으로 벤딩되어 상기한 인너리드(11) 단부의 노출된 상면과 반대방향에서 다른 패키지나 외부회로를 접속할 수 있게 된 걸 타입(gull type)의 아웃리드(15)가 형성되어 있다.In addition, solders 14 are formed on upper surfaces of the end portions of the inner leads 11 exposed to the outside, respectively, to facilitate connecting the lead connecting portions or the external circuits of the other packages installed thereon. 11) extends so as to protrude outwardly through the side portion of the molding portion 13 and bends from the side portion of the molding portion 13 to the lower surface side so as to be different from the exposed upper surface of the end of the inner lead 11. A gull type outlead 15 is formed in which external circuits can be connected.
상기와 같은 구조는 인너리드(11) 단부의 상면을 외부로 노출시키고, 그 노출된 인너리드(11)의 상면에 솔더(14)를 형성시켜 다른 패키지의 적층이 용이하며, 패키지가 작동시 발생한 열이 노출된 인너리드(11)를 통하여 패키지의 외부로 방출되어 패키지의 크랙발생이 방지되는 것이다.The above structure exposes the upper surface of the end of the inner lead 11 to the outside, and forms a solder 14 on the exposed upper surface of the inner lead 11 to facilitate stacking of other packages. Heat is emitted to the outside of the package through the inner lead 11 exposed to prevent cracking of the package.
제3도는 제2도의 다른 실시예를 보인 종단면도로서, 도시된 바와 같이, 피시비기판(16)의 상면에 걸 타입의 패키지를 2개 적층하였으며, 하부 패키지(P)의 인너리드(11) 상면에 형성된 솔더(14)에 상부 패키지(P')의 아웃리드(15')를 설치한 것이다.FIG. 3 is a longitudinal cross-sectional view of another embodiment of FIG. 2, and as shown in FIG. 3, two hook-type packages are stacked on an upper surface of the PCB 16 and an upper surface of the inner lid 11 of the lower package P is illustrated. The out lead 15 'of the upper package P' is installed in the solder 14 formed in the solder 14.
제5도는 제2도의 또다른 실시예를 보인 종단면도로서, 도시된 바와 같이, 피시비기판(16)의 상면에 QFP 타입 패키지인 하부 패키지(P) 1개를 설치하고, 그 하부 패키지(P)의 인너리드(11) 상면에 솔더(14)를 이용하여 상부 패키지(P')의 아웃리드(15')를 연결설치한 것이다.FIG. 5 is a longitudinal cross-sectional view showing another embodiment of FIG. 2, and as shown in FIG. 5, one lower package P, which is a QFP type package, is installed on an upper surface of the PCB 1 and the lower package P is shown in FIG. Inner lid 11 of the upper surface of the upper package (P ') using the solder 14 is connected to the lead 15'.
이상에서 상세히 설명한 바와 같이, 본 고안 적층형 반도체 패키지는 인너리드를 반도체 칩의 상면까지 연장형성하고, 그 인너리드의 상면이 외부로 노출되도록 몰딩하여, 그 인너리드의 상면에 다른 패키지를 적층할 수 있도록 함으로써 패키지의 집적도 향상이 용이한 효과가 있을 뿐 아니라, 상기 노출된 인너리드를 통하여 외부로 열방출이 용이하여 패키지의 크랙발생이 방지되는 효과가 있다.As described above in detail, the inventive multilayer semiconductor package may extend the inner lead to the upper surface of the semiconductor chip, and may be molded so that the upper surface of the inner lead is exposed to the outside, thereby stacking another package on the upper surface of the inner lead. As a result, the integration density of the package is not only easily improved, but heat is easily released to the outside through the exposed inner lead, thereby preventing the occurrence of cracking of the package.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950038043U KR200148118Y1 (en) | 1995-12-04 | 1995-12-04 | Stacked semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950038043U KR200148118Y1 (en) | 1995-12-04 | 1995-12-04 | Stacked semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970046889U KR970046889U (en) | 1997-07-31 |
| KR200148118Y1 true KR200148118Y1 (en) | 1999-06-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950038043U KR200148118Y1 (en) | 1995-12-04 | 1995-12-04 | Stacked semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR200148118Y1 (en) |
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1995
- 1995-12-04 KR KR2019950038043U patent/KR200148118Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970046889U (en) | 1997-07-31 |
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