KR19990054825A - Multilayer semiconductor package and manufacturing method thereof - Google Patents
Multilayer semiconductor package and manufacturing method thereof Download PDFInfo
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- KR19990054825A KR19990054825A KR1019970074702A KR19970074702A KR19990054825A KR 19990054825 A KR19990054825 A KR 19990054825A KR 1019970074702 A KR1019970074702 A KR 1019970074702A KR 19970074702 A KR19970074702 A KR 19970074702A KR 19990054825 A KR19990054825 A KR 19990054825A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
본 발명은 적층형 반도체 패키지 및 그 제조방법에 관한 것으로, 종래에는 부피가 크고 무거울 뿐만 아니라 다단계의 연결부위가 노출되어 접합부위가 약하게 되며, 상기 칩패드에서 피시비까지의 신호선이 길어 고속동작시 신호지연 및 간섭소음 등이 발생되거나, 또는 여러단계의 접합단계를 거쳐야 하므로, 구성재료의 변형 및 계면접착력이 약화되는 것은 물론, 공정수가 많아지고 복잡하여 생산비용 및 생산성이 저하되는 문제점이 있었던 바, 본 발명에서는 다수개의 솔더범프가 각 회로 일단에 연결되도록 형성된 서브 스트레이트와, 그 서브 스트레이트의 상면에 고정됨과 아울러 솔더범프와 연결되는 와이어가 노출되도록 일체된 수개의 반도체 칩과, 그 반도체 칩이 모두 감싸듯이 일괄적으로 몰딩되는 봉지부 및 방열캡과, 상기 서브 스트레이트의 회로 타단에 연결되어 피시비 기판에 접착되는 외부단자로 구성함으로써, 구조적으로 작고 가벼울 뿐만 아니라 접합부위가 강하고 고속동작시에도 신호지연 및 간섭소음이 발생되지 않게 되는 것은 물론, 이러한 적층형 반도체 패키지는 제조함에 있어서 변형 및 계면접착력이 강하면서도 제조과정이 간단하고 용이하여 생산비용은 절감되면서 생산성은 향상되는 효과가 있다.The present invention relates to a stacked semiconductor package and a method of manufacturing the same. In the related art, a bulky, heavy, and exposed connection stage of multiple stages is exposed to weaken the junction, and a signal line from the chip pad to the PCB is long, so that the signal delay is high. And interference noises or the like, or through several stages of joining, the deformation and the interfacial adhesion of the constituent materials are weakened, and the number of processes is increased and complicated, resulting in a reduction in production cost and productivity. In the present invention, a plurality of solder bumps are formed to be connected to one end of each circuit, and several semiconductor chips integrally fixed to the upper surface of the sub straight and exposed to the wires connected to the solder bumps, as if the semiconductor chips are all wrapped. The encapsulation portion and the heat dissipation cap which are molded at the same time, and the substress By configuring the external terminal connected to the other end of the circuit board and bonded to the PCB, the laminated semiconductor package is not only small in structure and light in weight, but also has a strong junction and no signal delay and interference noise during high-speed operation. In manufacturing, the deformation and interfacial adhesion is strong, but the manufacturing process is simple and easy, thereby reducing the production cost and improving productivity.
Description
본 발명은 적층형 반도체 패키지 및 그 제조방법에 관한 것으로, 특히 경박단소하면서도 고속, 과열 칩의 메모리 증가에 적합한 적층형 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package suitable for increasing the memory of a high speed, superheated chip, and a manufacturing method thereof.
최근들어 전자제품들이 소형화, 다기능화되어감에 따라 그에 적용되는 패키지 역시 경박단소하면서도 고속동작에 적합하도록 제작됨은 물론, 보다 다용량화하기 위한 적층형 반도체 패키지가 다양하게 제시되고 있다.Recently, as electronic products are miniaturized and multifunctional, packages applied thereto are also made to be thin and light, and suitable for high-speed operation, as well as various stacking semiconductor packages for higher capacity.
도1은 종래의 초소형 패키지인 TSOP를 보인 종단면도이고, 도 2a 및 도 2b는 종래 TSOP를 적층시키는 과정을 정면에서 보인 종단면도이며, 도 3은 종래 TSOP를 적층한 상태를 측면에서 보인 정면도이다.Figure 1 is a longitudinal cross-sectional view showing a TSOP, which is a conventional ultra-small package, Figures 2a and 2b is a longitudinal cross-sectional view showing a process of stacking a conventional TSOP, Figure 3 is a front view showing a side stacked state of a conventional TSOP. .
이에 도시된 바와 같이 종래의 초소형 패키지인 TSOP(Thin Small Outline Package)는, 다수개의 리드프레임(1)의 중앙부 상면에 반도체 칩(2)이 부착되어 있고, 상기 리드프레임(1)과 칩패드(2a)가 골드와이어(3)로 연결되어 있으며, 그 골드와이어(3)가 외부충격으로부터 보호되도록 반도체 칩(2)의 상면까지 에폭시로 봉지부(4)가 형성되어 있다.As shown in the drawing, a conventional ultra small package (TSOP) includes a semiconductor chip 2 attached to an upper surface of a central portion of a plurality of lead frames 1, and the lead frame 1 and the chip pad ( 2a) is connected to the gold wire 3, and the encapsulation portion 4 is formed of epoxy to the upper surface of the semiconductor chip 2 so that the gold wire 3 is protected from external impact.
상기 리드프레임(1)은 전체적으로 그 두께가 얇게 형성되는 것으로, 일부는 봉지부(4)에 포함되고,나머지는 그 길이가 짧게 절단되어 봉지부(4)의 외부로 노출되어 있다.The lead frame 1 is formed to have a thin thickness as a whole, a part of which is included in the encapsulation part 4, and the rest of the lead frame 1 is shortly cut and exposed to the outside of the encapsulation part 4.
이러한 패키지를 형성하기 위하여는, 먼저 얇은 리드프레임(1)의 상면에 반도체 칩(2)을 절연테이프(미도시)를 이용하여 부착하고, 그 리드프레임(1)의 각 내측단 저면과 반도체 칩(2)의 저면 중앙에 형성된 칩패드(2a)를 골드와이어(3)로 본딩한 이후에, 소정형상의 금형(미도시)에 안치시켜 에폭시를 주입하여 봉지부(4)를 형성하며, 상기 봉지부(4)의 외부로 노출된 리드프레임(1)을 짧게 절단하여 단품의 TSOP를 제조하는 것이었다.In order to form such a package, first, the semiconductor chip 2 is attached to the upper surface of the thin lead frame 1 by using an insulating tape (not shown), and the bottom surface of each inner end of the lead frame 1 and the semiconductor chip. After bonding the chip pad (2a) formed in the center of the bottom of the (2) with a gold wire (3), it is placed in a mold (not shown) of a predetermined shape to inject epoxy to form a sealing portion (4), The lead frame 1 exposed to the outside of the encapsulation portion 4 was cut short to produce a single piece of TSOP.
상기와 같이 구성된 종래의 TSOP를 이용하여 적층시키는 과정은 도 2a 및 도2b에 도시된 바와 같이, 각각 아우터 리드(11)가 소정길이로 절단된 제1 패키지(10A)의 상면에 역시 아우터 리드(11)가 소정길이로 절단된 제2 패키지(10B)를 폴리머와 같은 접착제로 부착시키고, 상기 제1,제2 패키지(10A,10B)의 각 아우터 리드(11)가 끼워지도록 삽입홈(21)이 형성된 레일(20)을 이용하여 각 아우터 리드(11)를 연결하는데, 이때 상기 각 레일(20)의 상단을 패키지 방향으로 절곡하여 제2 패키지(10B)의 상면에 접착시킨 이후에, 상기 삽입홈(21)에 솔더(미도시)를 부착한 다음에 열을 가해 그 솔더가 용융되면서 각 아우터 리드(11)를 고정하도록 하는 것이었다.In the stacking process using the conventional TSOP configured as described above, as illustrated in FIGS. 2A and 2B, the outer lead 11 is also formed on the upper surface of the first package 10A having the outer lead 11 cut to a predetermined length. Attached to the second package (10B) cut 11) to a predetermined length with an adhesive such as a polymer, the insertion groove 21 so that each outer lead 11 of the first and second packages (10A, 10B) is fitted The outer leads 11 are connected by using the formed rails 20. At this time, the upper ends of the rails 20 are bent in the package direction and bonded to the upper surface of the second package 10B. A solder (not shown) was attached to the groove 21 and heat was applied to fix each outer lead 11 while the solder was melted.
한편, 상기 각 레일(20)의 하단은 바깥쪽으로 절곡하여 그 저면에 통상의 피시비 기판(미도시)에 실장하는 것이었다.On the other hand, the lower end of each of the rails 20 was bent outward and mounted on an ordinary PCB substrate (not shown) on the bottom thereof.
그러나, 상기와 같은 종래의 적층형 반도체 패키지에 있어서는, 먼저 구조적으로 부피가 크고 무거울 뿐만 아니라 다단계의 연결부위가 노출되어 접합부위가 약하게 되며, 상기 칩패드(2a)에서 피시비(미도시)까지의 신호선(3)이 길어 고속동작시 신호지연 및 간섭소음 등이 발생되는 문제점이 있었다.However, in the conventional stacked semiconductor package as described above, not only the structure is bulky and heavy, but also the connection sites are weakened by exposing the multi-stage connection sites, and the signal lines from the chip pads 2a to the PCBs (not shown). (3) is long, there is a problem that the signal delay and interference noise occurs during high speed operation.
또한, 여러단계의 접합단계를 거쳐야 하므로, 구성재료의 변형 및 계면접착력이 약화되는 것은 물론, 공정수가 많아지고 복잡하여 생산비용 및 생산성이 저하되는 문제점도 있었다.In addition, since a plurality of joining steps are required, the deformation and the interfacial adhesion of the constituent materials are weakened, as well as the number of processes and the complexity, resulting in a reduction in production cost and productivity.
따라서, 본 발명은 상기와 같은 종래의 적층형 반도체 패키지가 가지는 제반 문제점을 감안하여 안출한 것으로, 구조적으로 작고 가벼울 뿐만 아니라 접합부위가 강하고 고속동작시에도 신호지연 및 간섭소음이 발생되지 않는 적층형 반도체 패키지를 제공하려는데 본 발명의 목적이 있다.Accordingly, the present invention has been made in view of the above-mentioned problems of the conventional multilayer semiconductor package. The multilayer semiconductor package is not only structurally small and light, but also has a strong junction and no signal delay and interference noise even at high speed. It is an object of the present invention to provide.
또한, 이러한 적층형 반도체 패키지를 제조함에 있어서 변형 및 계면접착력이 강하면서도 제조과정이 간단하고 용이하여 생산비용의 절감은 물론 생산성을 향상시킬 수 있는 적층형 반도체 패키지의 제조방법을 제공하려는데도 본 발명의 목적이 있다.The present invention also provides a method of manufacturing a multilayer semiconductor package that can reduce production costs and improve productivity by having a high deformation and interfacial adhesion force and a simple and easy manufacturing process in manufacturing the multilayer semiconductor package. There is this.
제1도는 종래의 초소형 패키지인 TSOP를 보인 종단면도.1 is a longitudinal sectional view showing a TSOP which is a conventional ultra-small package.
제2a도 및 제2b도는 종래 TSOP를 적층시키는 과정을 정면에서 보인 종단면도.2a and 2b is a longitudinal cross-sectional view showing a conventional process of stacking the TSOP.
제3도는 종래 TSOP를 적층한 상태를 측면에서 보인 정면도.3 is a front view showing a state in which a conventional TSOP is stacked.
제4도는 본 발명에 의한 반도체 패키지의 일례를 보인 종단면도.4 is a longitudinal sectional view showing an example of a semiconductor package according to the present invention.
제5a도 내지 제5f도는 본 발명에 의한 반도체 패키지를 제조하는 과정으로 보인 사시도 및 종단면도.5a to 5f are a perspective view and a longitudinal cross-sectional view shown in the process of manufacturing a semiconductor package according to the present invention.
제6a도 및 제6b도는 본 발명에 의한 반도체 패키지의 제조과정에 있어서, 와이어본딩 과정을 보인 상세도.6a and 6b is a detailed view showing a wire bonding process in the manufacturing process of the semiconductor package according to the present invention.
제7도는 본 발명에 의한 반도체 패키지의 다른 실시예를 보인 종단면도.7 is a longitudinal sectional view showing another embodiment of the semiconductor package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
100 : 서브 스트레이트 110 : 솔더범프100: sub straight 110: solder bump
200 : 반도체 칩 210 : 골드와이어200: semiconductor chip 210: gold wire
300,310 : 봉지부 320 : 방열캡300,310: encapsulation part 320: heat dissipation cap
400 : 솔더볼 500 : 다이본딩 테이프400: solder ball 500: die bonding tape
600 : 칩고정용 테이프600: Chip Fixing Tape
이와 같은 본 발명의 목적을 달성하기 위하여, 다수개의 솔더범프가 각 회로 일단에 연결되도록 형성된 서브 스트레이트와, 그 서브 스트레이트의 상면에 고정됨과 아울러 솔더범프와 연결되는 와이어가 노출되도록 일체된 수개의 반도체 칩과, 그 반도체 칩이 모두 감싸듯이 일괄적으로 몰딩되는 봉지부와, 상기 서브 스트레이트의 회로 타단에 연결되어 피시비 기판에 접착되는 외부단자로 구성되는 것을 특징으로 하는 적층형 반도체 패키지가 제공된다.In order to achieve the object of the present invention, a plurality of semiconductors are integrally formed so that a plurality of solder bumps are connected to one end of each circuit, and fixed to the upper surface of the sub straights and the wires connected to the solder bumps are exposed. There is provided a stacked semiconductor package comprising a chip, an encapsulation portion which is collectively molded as if all of the semiconductor chips are wrapped, and an external terminal connected to the circuit other end of the sub-straight and bonded to a PCB substrate.
이하, 본 발명에 의한 적층형 반도체 패키지를 첨부도면에 도시된 일실시예에 의거하여 상세하게 설명한다.Hereinafter, a multilayer semiconductor package according to the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.
도4는 본 발명에 의한 반도체 패키지의 일례를 보인 종단면도이고, 도 5a내지 도5f는 본 발명에 의한 반도체 패키지를 제조하는 과정으로 보인 사시도 및 종단면도이며, 도 6a 및 도 6b는 본 발명에 의한 반도체 패키지의 제조과정에 있어서, 와이어본딩과정을 보인 상세도이다.Figure 4 is a longitudinal cross-sectional view showing an example of a semiconductor package according to the present invention, Figures 5a to 5f is a perspective view and a longitudinal cross-sectional view showing a process for manufacturing a semiconductor package according to the present invention, Figures 6a and 6b is a present invention In the manufacturing process of the semiconductor package according to the present invention, a detailed view showing a wire bonding process.
이에 도시된 바와 같이 본 발명에 의한 패키지는, 다수개의 솔더범프(110)가 각 회로 일단에 열결되도록 형성된 서브 스트레이트(100)와, 그 서브 스트레이트(100)의 상면에 일률적으로 세워져 고정됨과 아울러 솔더범프(11)와 연결되는 와이어(210)가 노출되도록 일체된 수개의 반도체 칩(200)과, 그 반도체 칩(200)이 모두 감싸듯이 일괄적으로 몰딩되는 봉지부(300)와, 상기 서브 스트레이트(100)의 회로 타단에 연결되어 피시비 기판(미도시)에 접착되는 솔더볼(400)로 구성된다.As shown therein, the package according to the present invention includes a sub straight 100 formed so that a plurality of solder bumps 110 are connected to one end of each circuit, and fixedly fixed on the upper surface of the sub straight 100 and soldered. Several semiconductor chips 200 integrated so that the wires 210 connected to the bumps 11 are exposed, the encapsulation portion 300 which is molded in a batch as if all the semiconductor chips 200 are wrapped, and the sub straight. It is composed of a solder ball 400 is connected to the other end of the circuit 100 is bonded to the PCB substrate (not shown).
상기 서브 스트레이트(100)의 상면에는 수개의 칩 고정홈조(120)가 길게 형성되고, 그 각 칩 고정홈조(120)의 바닥면에는 각 반도체 칩(200)을 부착 고정하기 위한 다이본딩 테이프(500) 또는 페이스트 접착제가 부착된다.A plurality of chip fixing grooves 120 are formed long on the upper surface of the sub straight 100, and a die bonding tape 500 for attaching and fixing each semiconductor chip 200 to the bottom surface of each chip fixing groove 120. Or paste adhesive is attached.
상기 각 반도체 칩(200)의 안정성을 고려하여 각 칩의 사이에는 칩고정용 테이프(600)가 부착 개재되는 것이 바람직하다.In consideration of the stability of each semiconductor chip 200, it is preferable that a chip fixing tape 600 is interposed between the chips.
상기와 같은 본 발명에 의한 패키지를 제조하는 과정은 다음과 같다.The process of manufacturing a package according to the present invention as described above is as follows.
즉, 통상적인 서브 스트레이트(100)의 상면에 수개의 칩 고정홈조(120)를 형성하고, 그 각각의 칩 고정홈조(120)에 다이본딩 테이프(500)를 접착시킴과 아울러 각 칩 고정홈조(120)의 사이마다에는 회로와 연결되는 솔더범프(110)를 형성시키며, 상기 각 칩 고정홈조(120)마다에 반도체 칩(200)을 세워서 부착 고정시킴과 아울러 그 각 반도체 칩(200)의 사이마다에는 절연테이프(600)를 부착 개재시키고, 상기 각 반도체 칩(200)의 패드(200a)에는 솔더범프(110)와 대응되도록 와이어(210)를 노출 형성시키며, 상기 서브 스트레이트(100) 및 반도체 칩(200)을 예열하면서 각 반도체 칩(200)을 가압하여 서브 스트레이트(100)에 완전 고정시키고, 상기 서브 스트레이트(100)에 일정한 온도로 리플로우시켜 도 6a 및 도 6b에 도시된 바와 같이 솔더범프(110)와 와이어(210)가 융착시키며, 상기 반도체 칩(200)전체를 일괄적으로 몰딩하고, 상기 서브 스트레이트(100)의 저면에 외부단자용 솔더볼(400)을 부착하는 단계로 수행하는 것이다.That is, several chip fixing grooves 120 are formed on the upper surface of the conventional sub straight 100, and the die bonding tape 500 is attached to each of the chip fixing grooves 120, and each chip fixing groove group ( The solder bumps 110 connected to the circuits are formed in each of the 120, and the semiconductor chips 200 are erected and fixed in each chip fixing groove 120, and the semiconductor chips 200 are fixed between the semiconductor chips 200. The insulating tape 600 is attached to each other, and the wires 210 are exposed to the pads 200a of the semiconductor chips 200 to correspond to the solder bumps 110, and the sub straight 100 and the semiconductors are exposed. While preheating the chip 200, each semiconductor chip 200 is pressurized to be completely fixed to the sub straight 100, and reflowed to the sub straight 100 at a constant temperature so as to show solder as shown in FIGS. 6A and 6B. Bump 110 and the wire 210 is fused, phase The entire semiconductor chip 200 is collectively molded, and the external terminal solder balls 400 are attached to the bottom of the sub straight 100.
본 발명에 의한 다른 실시예가 있는 경우는 다음과 같다.If there is another embodiment according to the present invention is as follows.
즉, 전술한 일례에서는 서브 스트레이트(100)의 상면에 반도체 칩(200)이 모두 감싸듯이 일괄적으로 몰딩되도록 봉지부(300)를 형성하는 것이었으나, 본 실시예에 있어서는 다수개의 솔더범프(미도시)가 각 회로 일단에 열결되도록 형성된 서브 스트레이트(100)와, 그 서브 스트레이트(100)의 상면에 고정됨과 아울러 솔더범프(미도시)와 연결되는 와이어(미도시)가 노출되도록 일체된 수개의 반도체 칩(200)과, 상기 솔더범프(미도시)와 와이어(미도시)를 보호하기 위하여 각 반도체 칩(200)의 일부만 몰딩되는 봉지부(310)와, 그 봉지부(310)이외의 부위를 보호함과 아울러 열을 방출시키기 위하여 반도체 칩(200)이 일괄적으로 덮여씌워지는 방열캡(320)과, 상기 서브 스트레이트(100)의 회로 타단에 연결되어 피시비 기판(미도시)에 접착되는 솔더볼(400)로 구성되는 것으로, 전술한 일실시예에서 반도체 칩(200) 전체를 일괄적으로 몰딩하는 단계를 대신하여 상기 각 솔더범프(미도시)와 와이어(미도시)가 결합된 부위만을 몰딩하고 나머지는 방열캡(320)으로 일괄 밀봉한 다음에, 상기 서브 스트레이트(100)의 저면에 외부단자용 솔더볼(400)을 부착하는 단계로 수행하는 것이다.That is, in the above-described example, the encapsulation part 300 is formed on the upper surface of the sub straight 100 so that the semiconductor chip 200 is collectively molded as if all of the semiconductor chips 200 are wrapped. However, in the present embodiment, a plurality of solder bumps (not shown) are formed. The sub straight 100 formed so as to be connected to one end of each circuit, and fixed to the upper surface of the sub straight 100, and several wires integrated to expose the wires (not shown) connected to the solder bumps (not shown). In order to protect the semiconductor chip 200, the solder bumps (not shown) and the wires (not shown), an encapsulation part 310 formed by molding a part of each semiconductor chip 200, and portions other than the encapsulation part 310. In order to protect the heat dissipation and to dissipate heat, the semiconductor chip 200 is covered with the heat dissipation cap 320, which is connected to the other end of the circuit of the sub straight 100 and bonded to a PCB substrate (not shown). Consisting of solder balls (400) In the above-described embodiment, instead of molding the entire semiconductor chip 200 in a batch, only the portions in which the solder bumps (not shown) and the wires (not shown) are combined and the heat dissipation cap ( After the package is sealed in a batch 320, the solder ball 400 for the external terminal is attached to the bottom of the sub straight 100.
도면중 미설명 부호인 500은 반도체 칩을 서브 스트레이트에 부착시키기 위한 다이본딩 테이프이고, 600은 각 칩을 고정하기 위한 칩고정용 테이프이다.In the figure, reference numeral 500 denotes a die-bonding tape for attaching the semiconductor chip to the sub straight, and 600 denotes a chip fixing tape for fixing each chip.
이로써, 집적도가 우수하여 짧은 신호 경로로 고속 디바이스 적층시 탁월한 성능을 발휘하게 되는 것이며, 서브 스트레이트를 통해 열방출이 발생되는 것은 물론, 특히 방열캡을 적용하는 경우에는 칩의 표면에 냉각유체가 접촉하게 되어 대류에 의한 열전달을 발생시키므로 열방출율이 현저하게 개선될 수 있다.As a result, excellent integration results in excellent performance when stacking high-speed devices in a short signal path, and heat dissipation occurs through sub-straights, and especially when a heat dissipation cap is applied, the cooling fluid contacts the surface of the chip. Since heat transfer by convection is generated, the heat release rate can be remarkably improved.
또한, 단품의 패키지를 개별적으로 생산한 다음에 다시 각 패키지를 적층하는 것이 아니라, 패키지 공정과 적층 공정이 동시에 진행되므로, 공정이 단순하여 제조비용이 절감됨은 물론 제조시간도 줄어들게 된다.In addition, instead of separately producing individual packages and then stacking each package again, the packaging process and the lamination process are performed at the same time, thereby simplifying the manufacturing process and reducing manufacturing time.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 패키지 및 그 제조방법은, 다수개의 솔더범프가 각 회로 일단에 연결되도록 형성된 서브 스트레이트와, 그 서브 스트레이트의 상면에 고정됨과 아울러 솔더범프와 연결되는 와이어가 노출되도록 일체된 수개의 반도체 칩과, 그 반도체 칩이 모두 감싸듯이 일괄적으로 몰딩되는 봉지부 및 방열캡과, 상기 서브 스트레이트의 회로 타단에 연결되어 피시비 기판에 접착되는 외부단자로 구성함으로써, 구조적으로 작고 가벼울 뿐만 아니라 접합부위가 강하고 고속동작시에도 신호지연 및 간섭소음이 발생되지 않게 되는 것은 물론, 이러한 적층형 반도체 패키지를 제조함에 있어서 변형 및 계면접착력이 가하면서도 제조과정이 간단하고 용이하여 생산비용은 절감되면서 생산성은 향상되는 효과가 있다.As described above, a semiconductor package and a method of manufacturing the same according to the present invention include a substraight formed so that a plurality of solder bumps are connected to one end of each circuit, and a wire connected to the solder bumps while being fixed to an upper surface of the substraight. It consists of several semiconductor chips integrally integrated with each other, an encapsulation portion and a heat dissipation cap which are collectively molded as if all of the semiconductor chips are wrapped, and an external terminal connected to the other end of the sub straight circuit and bonded to the PCB substrate. In addition to being small and light, the joints are strong and signal delay and interference noise are not generated during high-speed operation. In addition, the manufacturing process is simple and easy while the deformation and interfacial adhesion force is applied in manufacturing the stacked semiconductor package. Productivity can be improved while being saved.
Claims (7)
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| KR1019970074702A KR100253390B1 (en) | 1997-12-26 | 1997-12-26 | Lamination type semiconductor package and method of fabricating thereof |
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| CN110010600B (en) * | 2018-12-31 | 2020-12-29 | 浙江臻镭科技股份有限公司 | Interconnection structure for vertically placing radio frequency chip module and manufacturing method thereof |
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